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完善迭代压缩模块的代码
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@ -58,3 +58,8 @@
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//定义 SM3 字扩展模式-----------------------
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`define SM3_EXPND_PRE_LOAD_REG
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//定义 SM3 迭代压缩中的加法方式-----------------------
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//直接使用加法符，使工具推断
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`define SM3_CMPRSS_DIRECT_ADD
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`define SM3_CMPRSS_CSA_ADD
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127
rtl/sm3_cmprss_ceil_comb.v
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127
rtl/sm3_cmprss_ceil_comb.v
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@ -0,0 +1,127 @@
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`timescale 1ns / 1ps
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`include "sm3_cfg.v"
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//////////////////////////////////////////////////////////////////////////////////
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// Author: ljgibbs / lf_gibbs@163.com
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// Create Date: 2020/07/28
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// Design Name: sm3
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// Module Name: sm3_cmprss_ceil_comb
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// Description:
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// SM3 单轮迭代压缩模块 由组合逻辑构成
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//
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// Dependencies:
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// inc/sm3_cfg.v
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// Revision:
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// Revision 0.01 - File Created
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//////////////////////////////////////////////////////////////////////////////////
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module sm3_cmprss_ceil_comb(
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input cmprss_round_sm_16_i,
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input [31:0] tj_i,
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input [31:0] reg_a_i,
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input [31:0] reg_b_i,
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input [31:0] reg_c_i,
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input [31:0] reg_d_i,
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input [31:0] reg_e_i,
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input [31:0] reg_f_i,
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input [31:0] reg_g_i,
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input [31:0] reg_h_i,
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input [31:0] wj_i,
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input [31:0] wjj_i,
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output [31:0] reg_a_o,
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output [31:0] reg_b_o,
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output [31:0] reg_c_o,
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output [31:0] reg_d_o,
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output [31:0] reg_e_o,
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output [31:0] reg_f_o,
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output [31:0] reg_g_o,
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output [31:0] reg_h_o
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);
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//wire
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wire [31:0] tmp_for_ss1_0 ;
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wire [31:0] tmp_for_ss1_2 ;
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wire [31:0] ss1 ;
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wire [31:0] ss2 ;
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wire [31:0] tmp_for_tt1_0 ;
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wire [31:0] tmp_for_tt1_1 ;
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wire [31:0] tt1 ;
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wire [31:0] tmp_for_tt2_0 ;
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wire [31:0] tmp_for_tt2_1 ;
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wire [31:0] tt2 ;
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wire [31:0] tt2_after_p0 ;
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wire [31:0] TJ = tj_i;
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//加法器0
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`ifdef SM3_CMPRSS_DIRECT_ADD
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assign tmp_for_ss1_0 = {reg_a_i[31-12:0], reg_a_i[31:31-12+1]} + reg_e_i;
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assign tmp_for_ss1_2 = tmp_for_ss1_0 + TJ;
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`else
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sm3_adder U_ss1(
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.A({reg_a_i[31-12:0], reg_a_i[31:31-12+1]}),
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.B(reg_e_i),
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.C(TJ),
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.R(tmp_for_ss1_2)
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);
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`endif
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assign ss1 = {tmp_for_ss1_2[31 - 7 : 0], tmp_for_ss1_2[31 : 31 - 7 + 1]};
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assign ss2 = ss1 ^ {reg_a_i[31 - 12 : 0], reg_a_i[31 : 31 - 12 + 1]};
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//加法器1
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assign tmp_for_tt1_0 = cmprss_round_sm_16_i? reg_a_i ^ reg_b_i ^ reg_c_i : (reg_a_i & reg_b_i | reg_a_i & reg_c_i | reg_b_i & reg_c_i);
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`ifdef SM3_CMPRSS_DIRECT_ADD
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assign tmp_for_tt1_1 = reg_d_i + ss2 + wjj_i;
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assign tt1 = tmp_for_tt1_0 + tmp_for_tt1_1;
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`else
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//tmp_for_tt1_1 = reg_d_i + tmp_for_tt1_0 + wjj_i
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sm3_adder U_tmp_for_tt1_1(
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.A(reg_d_i),
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.B(tmp_for_tt1_0),
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.C(wjj_i),
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.R(tmp_for_tt1_1)
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);
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//tt1 = ss2 + tmp_for_tt1_1
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adder_32b U_tt1(
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.A(ss2),
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.B(tmp_for_tt1_1),
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.R(tt1)
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);
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`endif
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//加法器2
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assign tmp_for_tt2_0 = cmprss_round_sm_16_i? reg_e_i ^ reg_f_i ^ reg_g_i : (reg_e_i & reg_f_i | ~reg_e_i & reg_g_i);
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`ifdef SM3_CMPRSS_DIRECT_ADD
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assign tmp_for_tt2_1 = reg_h_i + ss1 + wj_i;
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assign tt2 = tmp_for_tt2_0 + tmp_for_tt2_1;
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`else
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//tmp_for_tt2_1 = reg_h_i + tmp_for_tt2_0 + wj_i
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sm3_adder U_tmp_for_tt2_1(
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.A(reg_h_i),
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.B(tmp_for_tt2_0),
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.C(wj_i),
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.R(tmp_for_tt2_1)
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);
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//tt2 = ss1 + tmp_for_tt2_1
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adder_32b U_tt2(
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.A(ss1),
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.B(tmp_for_tt2_1),
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.R(tt2)
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);
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`endif
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assign tt2_after_p0 = tt2 ^ {tt2[31-9:0], tt2[31:31-9+1]} ^ {tt2[31-17:0], tt2[31:31-17+1]};
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assign reg_a_o = tt1;
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assign reg_b_o = reg_a_i;
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assign reg_c_o = {reg_b_i[31 - 9 : 0], reg_b_i[31 : 31 - 9 + 1]};
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assign reg_d_o = reg_c_i;
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assign reg_e_o = tt2_after_p0;
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assign reg_f_o = reg_e_i;
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assign reg_g_o = {reg_f_i[31 - 19 : 0], reg_f_i[31 : 31 - 19 + 1]};
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assign reg_h_o = reg_g_i;
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endmodule
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@ -1,3 +1,5 @@
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`timescale 1ns / 1ps
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`include "sm3_cfg.v"
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//////////////////////////////////////////////////////////////////////////////////
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// Author: ljgibbs / lf_gibbs@163.com
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// Create Date: 2020/07/27
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31
rtl/util/adder_32b.v
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31
rtl/util/adder_32b.v
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: SHU
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// Engineer: lf
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//
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// Create Date: 2020/04/26 16:24:02
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// Design Name:
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// Module Name: adder_32b
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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// 32 位 加法器 性能分析用
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module adder_32b(
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input [31:0] A,
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input [31:0] B,
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output [31:0] R
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);
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wire [32:0] R_tmp;
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assign R_tmp = A + B;
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assign R = R_tmp[31:0];
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endmodule
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43
rtl/util/csa_adder_3i_32b.v
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43
rtl/util/csa_adder_3i_32b.v
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: SHU
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// Engineer: lf
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//
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// Create Date: 2020/04/26 16:24:02
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// Design Name:
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// Module Name: csa_adder_3i_32b
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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// 32 位 3 输入 CSA 加法器，不考虑进位
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module csa_adder_3i_32b(
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input [31:0] A,
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input [31:0] B,
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input [31:0] C,
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output [31:0] R
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);
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wire [31:0] S;
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wire [31:0] Ca;
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wire [33:0] R_tmp;
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//3-2 CSA
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assign S = A ^ B ^ C;
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assign Ca = (A & B) | (A & C) | (B & C);
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//加法器
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assign R_tmp = {Ca,{1'b0}} + S;
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//输出端口,取低位，不考虑进位
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assign R = R_tmp[31:0];
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endmodule
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56
rtl/util/sm3_adder.v
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56
rtl/util/sm3_adder.v
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: SHU
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// Engineer: lf
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//
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// Create Date: 2020/04/26 16:24:02
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// Design Name:
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// Module Name: sm3_adder
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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// SM3 32 位 3 输入 加法器，
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module sm3_adder(
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input [31:0] A,
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input [31:0] B,
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input [31:0] C,
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output [31:0] R
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);
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`define USE_CSA
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`ifdef USE_CSA
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//使用CSA加法器
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csa_adder_3i_32b U_csa_adder_3i_32b(
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.A(A),
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.B(B),
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.C(C),
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.R(R)
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);
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`else
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//使用两级加法器
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wire [31:0] tmp;
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adder_32b U_adder_0(
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.A(A),
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.B(B),
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.R(tmp)
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);
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adder_32b U_adder_1(
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.A(tmp),
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.B(C),
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.R(R)
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);
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`endif
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endmodule
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