fix 填充中的bug，并通过迭代压缩的2个例子测试，修改完善仿真脚本

rtl/sm3_cmprss_core.v

@@ -109,12 +109,13 @@ wire                inpt_wrd_of_blk_cntr_clr;
 
 //管理tj寄存器
 always @(posedge clk or negedge rst_n) begin
-    if(~rst_n) begin
+    if(~rst_n |cmprss_blk_res_finish) begin
         reg_tj          <=  32'h79cc4519;
     end
     else if(sm3_wj_wjj_vld_r)begin
         if(reg_cmprss_round == 6'd16 - INPT_WORD_NUM)
             reg_tj          <=  32'h9d8a7a87;
+        
         else begin
             `ifdef SM3_INPT_DW_32
                 reg_tj          <=  {reg_tj[30:0],reg_tj[31]};
@@ -138,8 +139,8 @@ always @(posedge clk or negedge rst_n) begin
         sm3_wj_wjj_lst_r    <=   1'b0;        
     end
     else begin
-        sm3_wj_wjj_vld_r    <=   sm3_wj_wjj_valid_i;
+        sm3_wj_wjj_vld_r    <=   expnd_inpt_vld_i;
-        sm3_wj_wjj_lst_r    <=   sm3_wj_wjj_last_i;        
+        sm3_wj_wjj_lst_r    <=   expnd_inpt_lst_i;       
     end
 end
 
@@ -150,8 +151,8 @@ end
             wjj_rnd_r       <=   32'd0;       
         end
         else begin
-            wj_rnd_r        <=   sm3_exp_wj_i;
+            wj_rnd_r        <=   expnd_inpt_wj_i;
-            wjj_rnd_r       <=   sm3_exp_wjj_i;     
+            wjj_rnd_r       <=   expnd_inpt_wjj_i;     
         end
     end
     
@@ -381,4 +382,4 @@ assign                      cmprss_otpt_res_o     =   sm3_res;
     endgenerate
 `endif
 
-`endif
+endmodule

rtl/sm3_expnd_core.v

@@ -420,5 +420,4 @@ assign                  pad_inpt_rdy_o           =  pad_inpt_d_inpt_rdy; //反
         end
     endgenerate
 `endif
-
 endmodule

rtl/sm3_pad_core.v

@@ -208,7 +208,8 @@ always @(*) begin
         end
         INPT_PAD_LST_DATA: begin//根据最后一个输入数据的情况，确定填充策略
             if(inpt_vld_byte_cmplt) begin
-                if(inpt_wd_cntr[3:0] == 4'd0 && ~(inpt_wd_cntr == 16'd0))begin
+                // if(inpt_wd_cntr[3:0] == 4'd0 && ~(inpt_wd_cntr == 16'd0))begin
+                if(inpt_wd_cntr[3:0] == PAD_BLK_WD_NUM - INPT_WORD_NUM)begin
                     nxt_state   =   PAD_10_WAT_NEW_BLK;//填充以'1'为首的新块
                 end else begin//本块中填1
                     nxt_state   =   PAD_10_DATA;
@@ -300,5 +301,4 @@ assign                      pad_otpt_ena    =     state == PAD_10_DATA
 assign                      pad_otpt_vld_o      =   msg_inpt_vld_r1 || pad_otpt_ena;
 assign                      msg_inpt_rdy_o      =   pad_otpt_ena_i && (state == IDLE || state == INPT_DATA);
 
-
 endmodule

rtl/wrppr/sm3_cmprss_core_wrapper.sv

@@ -17,7 +17,7 @@ module sm3_cmprss_core_wrapper (
     sm3_if.CMPRSS sm3if
 );
 
-sm3_expnd_core sm3_cmprss_core(
+sm3_cmprss_core U_sm3_cmprss_core(
     .clk                        (sm3if.clk                    ),
     .rst_n                      (sm3if.rst_n                  ),
 

sim/run/run_sim.bat

@@ -14,7 +14,7 @@ REM
 REM ****************************************************************************
 set bin_path=C:\modeltech64_10.5\win64
 REM call %bin_path%/vsim -do "do ../script/{run_sm3_expnd_tb.do}" -l run_sim.log
-call %bin_path%/vsim -do "do ../script/{run_sm3_cmprss_tb.do}" -l run_sim.log
+call %bin_path%/vsim -do "do ../script/run_sm3_cmprss_tb.do" -l run_sim.log
 
 if "%errorlevel%"=="1" goto END
 if "%errorlevel%"=="0" goto SUCCESS

sim/script/run_sm3_cmprss_tb.do

@@ -1,10 +1,10 @@
 #////////////////////////////////////////////////////////////////////////////////
 # Author:        ljgibbs / lf_gibbs@163.com
-# Create Date: 2020/07/26 
+# Create Date: 2020/07/28 
 # Design Name: sm3
-# Module Name: run_sm3_expnd_tb
+# Module Name: run_sm3_cmprss_tb
 # Description:
-#      运行 sm3 扩展模块 tb 的 Modelsim 脚本
+#      运行 sm3 迭代压缩模块 tb 的 Modelsim 脚本
 #          - 使用相对路径
 #          - 使用库 sm3_core
 # Revision:
@@ -13,17 +13,17 @@
 
 vlib sm3_core
 
-vlog -64 -incr -work sm3_core  "+incdir+../rtl/inc" \
+vlog -64 -incr -work sm3_core  "+incdir+../../rtl/inc" \
-"../rtl/*.v" \
+"../../rtl/*.v" \
+"../../rtl/util/*.v" \
 
-vlog -64 -incr -sv -work sm3_core  "+incdir+../rtl/inc" \
+vlog -64 -incr -sv -work sm3_core  "+incdir+../../rtl/inc" \
-"../rtl/*.v"  \
+"../../rtl/if/*.sv" \
-"../rtl/if/*.sv" \
+"../../rtl/wrppr/*.sv" \
-"../rtl/wrppr/*.sv" \
-"../rtl/util/*.sv" \
 "../tb/*.sv" \
+"../sim_rtl/*.sv" \
 
-vsim -voptargs="+acc" -t 1ps   -L unisims_ver -L unimacro_ver -L secureip -lib sm3_core sm3_core.tb_sm3_expnd_top;
+vsim -voptargs="+acc" -t 1ps   -L unisims_ver -L unimacro_ver -L secureip -lib sm3_core sm3_core.tb_sm3_cmprss_top;
 
 add wave *
 

sim/script/run_sm3_expnd_tb.do

@@ -13,16 +13,17 @@
 
 vlib sm3_core
 
-vlog -64 -incr -work sm3_core  "+incdir+../rtl/inc" \
+vlog -64 -incr -work sm3_core  "+incdir+../../rtl/inc" \
-"../rtl/*.v" \
+"../../rtl/*.v" \
+"../../rtl/util/*.v" \
 
-vlog -64 -incr -sv -work sm3_core  "+incdir+../rtl/inc" \
+vlog -64 -incr -sv -work sm3_core  "+incdir+../../rtl/inc" \
-"../rtl/*.v"  \
+"../../rtl/if/*.sv" \
-"../rtl/if/*.sv" \
+"../../rtl/wrppr/*.sv" \
-"../rtl/wrppr/*.sv" \
 "../tb/*.sv" \
+"../sim_rtl/*.sv" \
 
-vsim -voptargs="+acc" -t 1ps   -L unisims_ver -L unimacro_ver -L secureip -lib sm3_core sm3_core.tb_sm3_cmprss_top;
+vsim -voptargs="+acc" -t 1ps   -L unisims_ver -L unimacro_ver -L secureip -lib sm3_core sm3_core.tb_sm3_expnd_top;
 
 add wave *
 

sim/tb/tb_sm3_cmprss_top.sv

@@ -73,7 +73,7 @@ initial begin
         // sm3_inpt_byte_num = $urandom % (64*100) + 1;
 
         @(posedge sm3if.clk);
-        task_pad_inpt_gntr_exmpl0();
+        task_pad_inpt_gntr_exmpl1();
         @(posedge sm3if.clk);
     end