修改运行脚本

This commit is contained in:
lf 2020-07-28 22:51:53 +08:00
parent 4a830d2d87
commit 62d0081ba1
3 changed files with 38 additions and 2 deletions

View File

@ -13,7 +13,8 @@ REM usage: run_sim.bat
REM
REM ****************************************************************************
set bin_path=C:\modeltech64_10.5\win64
call %bin_path%/vsim -do "do ../script/{run_sm3_expnd_tb.do}" -l run_sim.log
REM call %bin_path%/vsim -do "do ../script/{run_sm3_expnd_tb.do}" -l run_sim.log
call %bin_path%/vsim -do "do ../script/{run_sm3_cmprss_tb.do}" -l run_sim.log
if "%errorlevel%"=="1" goto END
if "%errorlevel%"=="0" goto SUCCESS

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@ -0,0 +1,35 @@
#////////////////////////////////////////////////////////////////////////////////
# Author: ljgibbs / lf_gibbs@163.com
# Create Date: 2020/07/26
# Design Name: sm3
# Module Name: run_sm3_expnd_tb
# Description:
# 运行 sm3 扩展模块 tb 的 Modelsim 脚本
# - 使用相对路径
# - 使用库 sm3_core
# Revision:
# Revision 0.01 - File Created
#////////////////////////////////////////////////////////////////////////////////
vlib sm3_core
vlog -64 -incr -work sm3_core "+incdir+../rtl/inc" \
"../rtl/*.v" \
vlog -64 -incr -sv -work sm3_core "+incdir+../rtl/inc" \
"../rtl/*.v" \
"../rtl/if/*.sv" \
"../rtl/wrppr/*.sv" \
"../rtl/util/*.sv" \
"../tb/*.sv" \
vsim -voptargs="+acc" -t 1ps -L unisims_ver -L unimacro_ver -L secureip -lib sm3_core sm3_core.tb_sm3_expnd_top;
add wave *
view wave
view structure
view signals
log -r /*
restart -f;run 2us

View File

@ -22,7 +22,7 @@ vlog -64 -incr -sv -work sm3_core "+incdir+../rtl/inc" \
"../rtl/wrppr/*.sv" \
"../tb/*.sv" \
vsim -voptargs="+acc" -t 1ps -L unisims_ver -L unimacro_ver -L secureip -lib sm3_core sm3_core.tb_sm3_expnd_top;
vsim -voptargs="+acc" -t 1ps -L unisims_ver -L unimacro_ver -L secureip -lib sm3_core sm3_core.tb_sm3_cmprss_top;
add wave *