添加用于仿真的脚本

.gitignore

@@ -1 +1,4 @@
 run/sm3_core/*
+run/run_sim.log
+run/run.log
+run/vsim.wlf

run/run_sim.bat

@@ -0,0 +1,23 @@
+@echo off
+REM ****************************************************************************
+REM Vivado (TM) v2018.3 (64-bit)
+REM adapt by ljgibbs / lf_gibbs@163.com for design:sm3_core
+REM 
+REM Filename    : run_sim.bat
+REM Simulator   : Mentor Graphics ModelSim Simulator
+REM Description : Script for compiling the simulation design source files
+REM
+REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+REM
+REM usage: run_sim.bat
+REM
+REM ****************************************************************************
+set bin_path=C:\modeltech64_10.5\win64
+call %bin_path%/vsim -do "do {run_sm3_expnd_tb.do}" -l run_sim.log
+
+if "%errorlevel%"=="1" goto END
+if "%errorlevel%"=="0" goto SUCCESS
+:END
+exit 1
+:SUCCESS
+exit 0

run/run_sm3_expnd_tb.do

@@ -0,0 +1,34 @@
+#////////////////////////////////////////////////////////////////////////////////
+# Author:        ljgibbs / lf_gibbs@163.com
+# Create Date: 2020/07/26 
+# Design Name: sm3
+# Module Name: run_sm3_expnd_tb
+# Description:
+#      运行 sm3 扩展模块 tb 的 Modelsim 脚本
+#          - 使用相对路径
+#          - 使用库 sm3_core
+# Revision:
+# Revision 0.01 - File Created
+#////////////////////////////////////////////////////////////////////////////////
+
+vlib sm3_core
+
+vlog -64 -incr -work sm3_core  "+incdir+../rtl/inc" \
+"../rtl/*.v" \
+
+vlog -64 -incr -sv -work sm3_core  "+incdir+../rtl/inc" \
+"../rtl/*.v"  \
+"../rtl/if/*.sv" \
+"../rtl/wrppr/*.sv" \
+"../tb/*.sv" \
+
+vsim -voptargs="+acc" -t 1ps   -L unisims_ver -L unimacro_ver -L secureip -lib sm3_core sm3_core.tb_sm3_pad_top;
+
+add wave *
+
+view wave
+view structure
+view signals
+log -r /*
+
+restart -f;run 2us