mirror of
https://github.com/ljgibbslf/SM3_core.git
synced 2024-08-18 19:54:12 +08:00
385 lines
12 KiB
Verilog
385 lines
12 KiB
Verilog
`timescale 1ns / 1ps
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`include "sm3_cfg.v"
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//////////////////////////////////////////////////////////////////////////////////
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// Author: ljgibbs / lf_gibbs@163.com
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// Create Date: 2020/07/27
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// Design Name: sm3
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// Module Name: sm3_cmprss_core
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// Description:
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// SM3 迭代压缩模块-SM3 迭代压缩核心单元
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// 输入位宽：INPT_DW1 定义，支持32/64bit
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// 输出位宽：与输入位宽对应
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// 特性：在 64bit 位宽下，采用二度展开结构（暂未）
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// Dependencies:
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// inc/sm3_cfg.v
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// Revision:
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// Revision 0.01 - File Created
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//////////////////////////////////////////////////////////////////////////////////
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module sm3_cmprss_core (
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input clk,
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input rst_n,
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input [`INPT_DW1:0] expnd_inpt_wj_i,
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input [`INPT_DW1:0] expnd_inpt_wjj_i,
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input expnd_inpt_lst_i,
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input expnd_inpt_vld_i,
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output [255:0] cmprss_otpt_res_o,
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output cmprss_otpt_vld_o
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);
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//每时钟输入的数据字数量 32bit位宽：1 64bit位宽：2
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`ifdef SM3_INPT_DW_32
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localparam [1:0] INPT_WORD_NUM = 2'd1;
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`elsif SM3_INPT_DW_64
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localparam [1:0] INPT_WORD_NUM = 2'd2;
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`endif
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localparam [6:0] CMPRSS_RND_NUM = 7'd64;
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//A-H 字寄存器
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reg [31 : 0] reg_a;
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reg [31 : 0] reg_b;
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reg [31 : 0] reg_c;
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reg [31 : 0] reg_d;
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reg [31 : 0] reg_e;
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reg [31 : 0] reg_f;
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reg [31 : 0] reg_g;
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reg [31 : 0] reg_h;
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reg [31 : 0] reg_tj;
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reg [5 : 0] reg_cmprss_round;
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reg cmprss_round_sm_16;
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//结果寄存器
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reg sm3_res_valid;
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reg sm3_res_valid_r1;
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reg [255:0] sm3_res;
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reg cmprss_blk_res_finish;
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//A-H 字运算中间值
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wire [31 : 0] reg_a_new;
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wire [31 : 0] reg_b_new;
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wire [31 : 0] reg_c_new;
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wire [31 : 0] reg_d_new;
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wire [31 : 0] reg_e_new;
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wire [31 : 0] reg_f_new;
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wire [31 : 0] reg_g_new;
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wire [31 : 0] reg_h_new;
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`ifdef SM3_INPT_DW_64
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wire [31 : 0] reg_a_mid;
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wire [31 : 0] reg_b_mid;
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wire [31 : 0] reg_c_mid;
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wire [31 : 0] reg_d_mid;
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wire [31 : 0] reg_e_mid;
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wire [31 : 0] reg_f_mid;
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wire [31 : 0] reg_g_mid;
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wire [31 : 0] reg_h_mid;
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//两轮运算的 tj 值
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wire [31 : 0] reg_tj_rnd_odd;
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wire [31 : 0] reg_tj_rnd_even;
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`endif
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//块迭代标志
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wire cmprss_new_round_valid;
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wire cmprss_blk_start;
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wire cmprss_blk_finish;
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//对输入的 wj 值打拍或者分离
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reg sm3_wj_wjj_vld_r;
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reg sm3_wj_wjj_lst_r;
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`ifdef SM3_INPT_DW_32
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reg [31:0] wj_rnd_r;
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reg [31:0] wjj_rnd_r;
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`elsif SM3_INPT_DW_64
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reg [31:0] wj_rnd_odd_r;
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reg [31:0] wjj_rnd_odd_r;
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reg [31:0] wj_rnd_even_r;
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reg [31:0] wjj_rnd_even_r;
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`endif
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//输入每数据块所属数据字计数
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reg [5:0] inpt_wrd_of_blk_cntr;
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wire inpt_wrd_of_blk_cntr_add;
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wire inpt_wrd_of_blk_cntr_clr;
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//管理tj寄存器
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n |cmprss_blk_res_finish) begin
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reg_tj <= 32'h79cc4519;
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end
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else if(sm3_wj_wjj_vld_r)begin
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if(reg_cmprss_round == 6'd16 - INPT_WORD_NUM)
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reg_tj <= 32'h9d8a7a87;
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else begin
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`ifdef SM3_INPT_DW_32
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reg_tj <= {reg_tj[30:0],reg_tj[31]};
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`elsif SM3_INPT_DW_64 //每次循环左移两位
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reg_tj <= {reg_tj[29:0],reg_tj[31:30]};
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`endif
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end
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end
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end
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`ifdef SM3_INPT_DW_64
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//两轮运算的 tj 值
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assign reg_tj_rnd_odd = {reg_tj[30:0],reg_tj[31]};
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assign reg_tj_rnd_even = reg_tj;
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`endif
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//对输入的 wj 值打拍或者分离
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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sm3_wj_wjj_vld_r <= 1'b0;
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sm3_wj_wjj_lst_r <= 1'b0;
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end
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else begin
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sm3_wj_wjj_vld_r <= expnd_inpt_vld_i;
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sm3_wj_wjj_lst_r <= expnd_inpt_lst_i;
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end
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end
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`ifdef SM3_INPT_DW_32
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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wj_rnd_r <= 32'd0;
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wjj_rnd_r <= 32'd0;
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end
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else begin
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wj_rnd_r <= expnd_inpt_wj_i;
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wjj_rnd_r <= expnd_inpt_wjj_i;
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end
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end
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`elsif SM3_INPT_DW_64
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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wj_rnd_odd_r <= 32'd0;
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wjj_rnd_odd_r <= 32'd0;
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wj_rnd_even_r <= 32'd0;
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wjj_rnd_even_r <= 32'd0;
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end
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else begin
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{wj_rnd_even_r,wj_rnd_odd_r} <= expnd_inpt_wj_i;
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{wjj_rnd_even_r,wjj_rnd_odd_r} <= expnd_inpt_wjj_i;
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end
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end
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`endif
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//标记最后一块
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assign cmprss_new_round_valid = sm3_wj_wjj_vld_r;
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assign cmprss_blk_finish = inpt_wrd_of_blk_cntr_clr;
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//块运算完成信号
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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cmprss_blk_res_finish <= 1'b0;
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end
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else begin
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cmprss_blk_res_finish <= inpt_wrd_of_blk_cntr_clr;
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end
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end
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//输入每数据块所属数据字计数
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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inpt_wrd_of_blk_cntr <= 6'b0;
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end else if(inpt_wrd_of_blk_cntr_add)begin
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inpt_wrd_of_blk_cntr <= inpt_wrd_of_blk_cntr + INPT_WORD_NUM;
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end else if(inpt_wrd_of_blk_cntr_clr)begin
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inpt_wrd_of_blk_cntr <= 6'b0;
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end
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end
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assign inpt_wrd_of_blk_cntr_add = sm3_wj_wjj_vld_r;
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assign inpt_wrd_of_blk_cntr_clr = sm3_wj_wjj_vld_r
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&& inpt_wrd_of_blk_cntr == (CMPRSS_RND_NUM - INPT_WORD_NUM);
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//压缩迭代轮计数
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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reg_cmprss_round <= 6'd0;
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end
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else if(cmprss_blk_finish)begin
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reg_cmprss_round <= 6'd0;
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end
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else if(cmprss_new_round_valid)begin
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reg_cmprss_round <= reg_cmprss_round + INPT_WORD_NUM;
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end
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end
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//产生16轮内标记
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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cmprss_round_sm_16 <= 1'b0;
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end else begin
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cmprss_round_sm_16 <= reg_cmprss_round < 6'd16 - INPT_WORD_NUM; //标识当前小于
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end
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end
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//寄存器组初值装填与迭代
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always @(posedge clk or negedge rst_n) begin
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if((~rst_n) || sm3_res_valid_r1) begin
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reg_a <= 32'h7380166f;//0;
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reg_b <= 32'h4914b2b9;//0;
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reg_c <= 32'h172442d7;//0;
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reg_d <= 32'hda8a0600;//0;
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reg_e <= 32'ha96f30bc;//0;
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reg_f <= 32'h163138aa;//0;
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reg_g <= 32'he38dee4d;//0;
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reg_h <= 32'hb0fb0e4e;//0;
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end
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else if(cmprss_new_round_valid)begin
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reg_a <= reg_a_new;
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reg_b <= reg_b_new;
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reg_c <= reg_c_new;
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reg_d <= reg_d_new;
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reg_e <= reg_e_new;
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reg_f <= reg_f_new;
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reg_g <= reg_g_new;
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reg_h <= reg_h_new;
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end
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else if(cmprss_blk_res_finish)begin
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reg_a <= reg_a ^ sm3_res[255-:32];
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reg_b <= reg_b ^ sm3_res[223-:32];
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reg_c <= reg_c ^ sm3_res[191-:32];
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reg_d <= reg_d ^ sm3_res[159-:32];
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reg_e <= reg_e ^ sm3_res[127-:32];
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reg_f <= reg_f ^ sm3_res[95 -:32];
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reg_g <= reg_g ^ sm3_res[63 -:32];
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reg_h <= reg_h ^ sm3_res[31 -:32];
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end
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end
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//消息所属块均计算完毕，输出计算结果
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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sm3_res_valid <= 1'b0;
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sm3_res_valid_r1 <= 1'b0;
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end
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else begin
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sm3_res_valid <= sm3_wj_wjj_lst_r;
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sm3_res_valid_r1 <= sm3_res_valid;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if((~rst_n) || sm3_res_valid_r1) begin
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sm3_res <= {32'h7380166f, 32'h4914b2b9, 32'h172442d7, 32'hda8a0600, 32'ha96f30bc, 32'h163138aa, 32'he38dee4d, 32'hb0fb0e4e};
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end
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else if(cmprss_blk_res_finish)begin
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sm3_res <= {reg_a,reg_b,reg_c,reg_d,reg_e,reg_f,reg_g,reg_h} ^ sm3_res;
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end
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end
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`ifdef SM3_INPT_DW_32
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sm3_cmprss_ceil_comb U_sm3_cmprss_ceil_comb
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(
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.cmprss_round_sm_16_i (cmprss_round_sm_16),
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.tj_i (reg_tj),
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.reg_a_i (reg_a),
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.reg_b_i (reg_b),
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.reg_c_i (reg_c),
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.reg_d_i (reg_d),
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.reg_e_i (reg_e),
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.reg_f_i (reg_f),
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.reg_g_i (reg_g),
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.reg_h_i (reg_h),
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.wj_i (wj_rnd_r),
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.wjj_i (wjj_rnd_r),
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.reg_a_o (reg_a_new),
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.reg_b_o (reg_b_new),
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.reg_c_o (reg_c_new),
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.reg_d_o (reg_d_new),
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.reg_e_o (reg_e_new),
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.reg_f_o (reg_f_new),
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.reg_g_o (reg_g_new),
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.reg_h_o (reg_h_new)
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);
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`elsif SM3_INPT_DW_64
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sm3_cmprss_ceil_comb U_sm3_cmprss_ceil_comb
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(
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.cmprss_round_sm_16_i (cmprss_round_sm_16),
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.tj_i (reg_tj_rnd_even),
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.reg_a_i (reg_a),
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.reg_b_i (reg_b),
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.reg_c_i (reg_c),
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.reg_d_i (reg_d),
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.reg_e_i (reg_e),
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.reg_f_i (reg_f),
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.reg_g_i (reg_g),
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.reg_h_i (reg_h),
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.wj_i (wj_rnd_even_r),
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.wjj_i (wjj_rnd_even_r),
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.reg_a_o (reg_a_mid),
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.reg_b_o (reg_b_mid),
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.reg_c_o (reg_c_mid),
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.reg_d_o (reg_d_mid),
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.reg_e_o (reg_e_mid),
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.reg_f_o (reg_f_mid),
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.reg_g_o (reg_g_mid),
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.reg_h_o (reg_h_mid)
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);
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sm3_cmprss_ceil_comb U_sm3_cmprss_ceil_comb_1
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(
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.cmprss_round_sm_16_i (cmprss_round_sm_16),
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.tj_i (reg_tj_rnd_odd),
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.reg_a_i (reg_a_mid),
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.reg_b_i (reg_b_mid),
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.reg_c_i (reg_c_mid),
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.reg_d_i (reg_d_mid),
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.reg_e_i (reg_e_mid),
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.reg_f_i (reg_f_mid),
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.reg_g_i (reg_g_mid),
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.reg_h_i (reg_h_mid),
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.wj_i (wj_rnd_odd_r),
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.wjj_i (wjj_rnd_odd_r),
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.reg_a_o (reg_a_new),
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.reg_b_o (reg_b_new),
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.reg_c_o (reg_c_new),
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.reg_d_o (reg_d_new),
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.reg_e_o (reg_e_new),
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.reg_f_o (reg_f_new),
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.reg_g_o (reg_g_new),
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.reg_h_o (reg_h_new)
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);
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`endif
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//输出控制
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assign cmprss_otpt_vld_o = sm3_res_valid_r1;
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assign cmprss_otpt_res_o = sm3_res;
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`ifdef SM3_CMPRS_SIM_DBG
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`ifdef SM3_CMPRS_SIM_FILE_LOG
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integer file;
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initial begin:inital_file
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file = $fopen("wj.txt","w");
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end
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`endif
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generate
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if(1) begin
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always@(*) begin
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if(cmprss_otpt_vld_o)
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begin
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`ifdef SM3_CMPRS_SIM_FILE_LOG
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$fdisplay(file,"LOG: res : %64h",cmprss_otpt_res_o);
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`else
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$display("LOG: res : %64h",cmprss_otpt_res_o);
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`endif
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end
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end
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end
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endgenerate
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`endif
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endmodule |