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https://github.com/ljgibbslf/SM3_core.git
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89 lines
2.6 KiB
Systemverilog
89 lines
2.6 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "sm3_cfg.v"
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//////////////////////////////////////////////////////////////////////////////////
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// Author: ljgibbs / lf_gibbs@163.com
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// Create Date: 2020/07/23
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// Design Name: sm3
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// Module Name: sm3_pad_mntr
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// Description:
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// SM3 填充结果监视器,将填充的最后一块结果与标准结果数组比较
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// 接口:sm3_if MONITOR
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// Dependencies:
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// inc/sm3_cfg.v
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// Revision:
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// Revision 0.01 - File Created
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//////////////////////////////////////////////////////////////////////////////////
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module sm3_pad_mntr (
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sm3_if.MONITOR sm3if,
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ref bit [31:0] gldn_pttrn[16]
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);
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int total_cnt = 0;
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int ok_cnt = 0;
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int fail_cnt = 0;
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logic [511:0] sm3_pad_lst_blk_reg;
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logic [511:0] sm3_gldn_pttrn_reg;
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logic sm3_pad_reg_shft;
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logic sm3_pad_reg_init;
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logic sm3_pad_reg_cmpr;
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always @(posedge sm3if.clk or negedge sm3if.rst_n) begin
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if(~sm3if.rst_n) begin
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sm3_pad_reg_cmpr <= 1'b0;
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sm3_pad_reg_init <= 1'b0;
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end else begin
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sm3_pad_reg_cmpr <= sm3if.pad_otpt_lst_o;
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sm3_pad_reg_init <= sm3_pad_reg_cmpr;
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end
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end
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assign sm3_pad_reg_shft = sm3if.pad_otpt_vld_o;
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//shift reg pad data
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always @(posedge sm3if.clk or negedge sm3if.rst_n) begin
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if(~sm3if.rst_n) begin
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sm3_pad_lst_blk_reg <= 512'b0;
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end else if(sm3_pad_reg_shft)begin
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`ifdef SM3_INPT_DW_32
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sm3_pad_lst_blk_reg <= {sm3_pad_lst_blk_reg[(511-32):0],sm3if.pad_otpt_d_o};
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`elsif SM3_INPT_DW_64
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sm3_pad_lst_blk_reg <= {sm3_pad_lst_blk_reg[(511-64):0],sm3if.pad_otpt_d_o};
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`endif
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end else if(sm3_pad_reg_init)begin
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sm3_pad_lst_blk_reg <= 512'b0;
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end
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end
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//compare with golden pattern
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always @(posedge sm3_pad_reg_cmpr) begin
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total_cnt++;
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$display("Mess:@%0t:result compare %d times",$time,total_cnt);
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foreach(gldn_pttrn[i])
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sm3_gldn_pttrn_reg[511 -32*i-:32] = gldn_pttrn[i];//do a copy to a ref array .hhh
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// if (sm3_gldn_pttrn_reg == sm3_pad_lst_blk_reg) begin
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// ok_cnt++;
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// $display("Mess:@%0t:check ok and ok %d times",$time,ok_cnt);
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// end else begin
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// fail_cnt++;
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// $display("Err:@%0t:check fail and fail %d times",$time,fail_cnt);
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// $stop;
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// end
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cmpr_a1:assert (sm3_gldn_pttrn_reg == sm3_pad_lst_blk_reg)
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begin
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ok_cnt++;
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$display("Mess:@%0t:check ok and ok %d times",$time,ok_cnt);
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end
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else begin
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fail_cnt++;
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$display("Err:@%0t:check fail and fail %d times",$time,fail_cnt);
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$stop;
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end
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end
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endmodule
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