FPGA/SM3_core
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lf 31a137a1eb add c model
2020-07-29 16:41:43 +08:00
c_model
add c model
2020-07-29 16:41:43 +08:00
doc
add waveform&drawio file and update some file
2020-07-26 16:11:47 +08:00
rtl
add sm3 top rtl&tb
2020-07-29 16:41:30 +08:00
sim
add sm3 top rtl&tb
2020-07-29 16:41:30 +08:00
.gitignore
直接移除参考代码文件夹
2020-07-28 22:22:34 +08:00
README.md
Create README.md
2020-07-29 09:56:09 +08:00

README.md

SM3_core

Description
No description provided
Readme 2.2 MiB
Languages
Verilog 42.7%
SystemVerilog 41.5%
C 12.4%
Stata 2.3%
Batchfile 0.9%
Other 0.2%