mirror of
https://github.com/ljgibbslf/SM3_core.git
synced 2024-08-18 19:54:12 +08:00
48 lines
1.2 KiB
Verilog
48 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Author: ljgibbs / lf_gibbs@163.com
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// Create Date: 2020/07/19
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// Design Name: sm3
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// Module Name: sm3_cfg
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// Description:
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// SM3 模块配置信息
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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//////////////////////////////////////////////////////////////////////////////////
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//定义设计阶段
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`define DESIGN_SIM
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// `define DESIGN_SYNT
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//定义 SM3 输入位宽
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// `define SM3_INPT_DW_32
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`define SM3_INPT_DW_64
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`ifdef SM3_INPT_DW_32
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`define INPT_DW 32
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`elsif SM3_INPT_DW_64
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`define INPT_DW 64
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`endif
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`define INPT_DW1 (INPT_DW - 1)
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`define INPT_BYTE_DW1 (INPT_DW/8 - 1)
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`define INPT_BYTE_DW (INPT_BYTE_DW1 + 1)
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//定义 SM3 输出位宽
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// `define SM3_OTPT_DW_32
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`define SM3_OTPT_DW_64
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// `define SM3_OTPT_DW_128
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// `define SM3_OTPT_DW_256
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`ifdef SM3_OTPT_DW_32
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`define OTPT_DW 32
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`elsif SM3_OTPT_DW_64
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`define OTPT_DW 64
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`elsif SM3_OTPT_DW_128
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`define OTPT_DW 128
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`elsif SM3_OTPT_DW_256
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`define OTPT_DW 256
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`endif
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`define OTPT_DW1 (OTPT_DW - 1) |