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https://github.com/ljgibbslf/SM3_core.git
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35 lines
873 B
Plaintext
35 lines
873 B
Plaintext
#////////////////////////////////////////////////////////////////////////////////
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# Author: ljgibbs / lf_gibbs@163.com
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# Create Date: 2020/07/26
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# Design Name: sm3
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# Module Name: run_sm3_expnd_tb
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# Description:
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# 运行 sm3 扩展模块 tb 的 Modelsim 脚本
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# - 使用相对路径
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# - 使用库 sm3_core
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# Revision:
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# Revision 0.01 - File Created
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#////////////////////////////////////////////////////////////////////////////////
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vlib sm3_core
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vlog -64 -incr -work sm3_core "+incdir+../rtl/inc" \
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"../rtl/*.v" \
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vlog -64 -incr -sv -work sm3_core "+incdir+../rtl/inc" \
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"../rtl/*.v" \
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"../rtl/if/*.sv" \
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"../rtl/wrppr/*.sv" \
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"../tb/*.sv" \
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vsim -voptargs="+acc" -t 1ps -L unisims_ver -L unimacro_ver -L secureip -lib sm3_core sm3_core.tb_sm3_pad_top;
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add wave *
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view wave
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view structure
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view signals
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log -r /*
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restart -f;run 2us
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