mirror of
https://github.com/ljgibbslf/SM3_core.git
synced 2024-08-18 19:54:12 +08:00
332 lines
15 KiB
Verilog
332 lines
15 KiB
Verilog
`timescale 1ns / 1ps
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`include "sm3_cfg.v"
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//////////////////////////////////////////////////////////////////////////////////
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// Author: ljgibbs / lf_gibbs@163.com
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// Create Date: 2020/07/26
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// Design Name: sm3
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// Module Name: sm3_expnd_core
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// Description:
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// SM3 扩展模块-SM3 扩展核心单元
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// 输入位宽：INPT_DW1 定义，支持32/64bit
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// 输出位宽：与输入位宽对应
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// 特性：预载寄存器（68->65clk(32b)/66->65clk(64b)）,目前仅支持32bit，默认开启
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// Dependencies:
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// inc/sm3_cfg.v
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// Revision:
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// Revision 0.01 - File Created
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//////////////////////////////////////////////////////////////////////////////////
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module sm3_expnd_core (
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input clk,
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input rst_n,
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input [`INPT_DW1:0] pad_inpt_d_i,
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input pad_inpt_vld_i,
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input pad_inpt_lst_i,
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input expnd_otpt_ena_i,
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output pad_inpt_rdy_o,
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output [`INPT_DW1:0] expnd_otpt_wj_o,
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output [`INPT_DW1:0] expnd_otpt_wjj_o,
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output expnd_otpt_lst_o,
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output expnd_otpt_vld_o
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);
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localparam WORDS_IN_BLOCK = 512 / 32;//16
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localparam WORD_EXPND_ROUND = 64;
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localparam WORD_OUTPUT_ROUND_END = WORD_EXPND_ROUND + WORDS_IN_BLOCK; //64+16
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localparam PRE_BUFF_N = 4;
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//字扩展电路
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wire [31:0] word_wj_expand;
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wire [31:0] word_wjj_expand;
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wire [31:0] word_wj_expand_tmp_1;
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wire [31:0] word_wj_expand_tmp_2;
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wire word_exp_push_reg_ena; //字拓展，并压入寄存器组使能
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//寄存器组 reg
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reg [31:0] word_buff [15:0]; //16字缓冲区 缓存16个32位字
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reg [31:0] word_buff_nb_pre [3:0];//4字 下一字预缓存区
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wire[31:0] word_buff_new_push; //寄存器组，新入组变量
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wire word_buff_shft_ena;
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wire word_buff_rpd_shft_ena;
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wire word_buff_nb_pre_shft_ena;
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//预缓冲区数据数量技术
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reg [1:0] word_buff_nb_pre_cntr;
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wire word_buff_nb_pre_cntr_add;
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wire word_buff_nb_pre_cntr_clr;
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//原始字输入计数
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reg [3:0] msg_blk_word_inpt_cntr;
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wire msg_blk_word_inpt_cntr_add;
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wire msg_blk_word_inpt_cntr_clr;
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//字扩展输出计数，指本数据块中扩展电路的扩展字输出数量
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reg [5:0] msg_blk_word_exp_cntr;
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wire msg_blk_word_exp_cntr_add;
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wire msg_blk_word_exp_cntr_clr;
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//消息扩展主状态机
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`define STT_W 8
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`define STT_W1 `STT_W - 1
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reg [`STT_W1:0] state;
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reg [`STT_W1:0] nxt_state;
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localparam IDLE = `STT_W'h1;
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localparam INPT_ORGN_5W = `STT_W'h2;//输入5个原始字w0-w4到寄存器组中
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localparam INPT_OTPT = `STT_W'h4;//输入剩下的11个原始字w5-w15，并输出11对扩展字
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localparam EXP_OTPT = `STT_W'h8;//扩展并输出扩展字,直至扩展得到第48个扩展字w63
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localparam EXP_OTPT_PRE_INPT = `STT_W'h10;//当w64生成后，开始预接收下一消息块前3个消息字 wn0-wn2，消息字写入预存储寄存器
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localparam EXP_OTPT_FIN = `STT_W'h20;//扩展以及输出结束（输出最后一对扩展字）,接收下一消息块的第4个消息字 wn3,判断预存储器中数据数量
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localparam WAT_PRE_INPT_FIN = `STT_W'h40;//若预存储器数据数量>0 但 <4,等待预寄存器存储完成 4 字
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localparam RPD_SHFT = `STT_W'h80;//快速移位原始数据,128b位宽的形式，包括预存储寄存器
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//SM3填充消息输入反压逻辑
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wire sm3_msg_inpt_rdy;
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//消息最后一块标记信号
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reg msg_lst_blk_flg;
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wire msg_lst_blk_flg_ena;
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wire msg_lst_blk_flg_clr;
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//SM3填充消息输入反压逻辑，仅在 EXP_OTPT 状态下仅进行扩展，不提供输入
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assign sm3_msg_inpt_rdy = ( state == IDLE
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|| state == INPT_ORGN_5W
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|| state == INPT_OTPT
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|| state == EXP_OTPT_PRE_INPT
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|| state == EXP_OTPT_FIN
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|| state == WAT_PRE_INPT_FIN
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|| state == RPD_SHFT
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) ;
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//原始字输入计数
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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msg_blk_word_inpt_cntr <= 4'b0;
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end else if(msg_blk_word_inpt_cntr_add)begin
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msg_blk_word_inpt_cntr <= msg_blk_word_inpt_cntr + 1'b1;
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end else if(msg_blk_word_inpt_cntr_clr)begin
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msg_blk_word_inpt_cntr <= 4'b0;
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end
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end
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assign msg_blk_word_inpt_cntr_add = sm3_msg_valid_i; //输入计数累加
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assign msg_blk_word_inpt_cntr_clr = 1'b0; //自清？
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//字扩展输出计数
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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msg_blk_word_exp_cntr <= 6'b0;
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end else if(msg_blk_word_exp_cntr_clr)begin
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msg_blk_word_exp_cntr <= 6'b0;
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end else if(msg_blk_word_exp_cntr_add)begin
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msg_blk_word_exp_cntr <= msg_blk_word_exp_cntr + 1'b1;
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end
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end
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assign msg_blk_word_exp_cntr_add = word_exp_push_reg_ena;//字扩展并移入寄存器使能
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assign msg_blk_word_exp_cntr_clr = msg_blk_word_exp_cntr == 6'd52;//完成 68-16 次扩展后清除计数器
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//预缓冲区数据数量计数
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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word_buff_nb_pre_cntr <= 2'b0;
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end else if(word_buff_nb_pre_cntr_add)begin
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word_buff_nb_pre_cntr <= word_buff_nb_pre_cntr + 1'b1;
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end else if(word_buff_nb_pre_cntr_clr)begin
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word_buff_nb_pre_cntr <= 2'b0;
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end
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end
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assign word_buff_nb_pre_cntr_add = ( state == EXP_OTPT_PRE_INPT
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|| state == EXP_OTPT_FIN
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|| state == WAT_PRE_INPT_FIN
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) && sm3_msg_valid_i;//预输入状态下的外部数据输入有效
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assign word_buff_nb_pre_cntr_clr = state == RPD_SHFT ;//预输入寄存器该状态下被移出
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//消息最后一块标记信号
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin
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msg_lst_blk_flg <= 1'b0;
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end else if(msg_lst_blk_flg_ena)begin
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msg_lst_blk_flg <= 1'b1;
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end else if(msg_lst_blk_flg_clr)begin
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msg_lst_blk_flg <= 1'b0;
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end
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end
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assign msg_lst_blk_flg_ena = sm3_msg_lst_i;
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assign msg_lst_blk_flg_clr = sm3_wj_wjj_lst_o;
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//消息扩展主状态机
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always @(*) begin
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case (state)
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IDLE: begin
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if(sm3_msg_valid_i)
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nxt_state = INPT_ORGN_5W;
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else
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nxt_state = IDLE;
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end
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INPT_ORGN_5W:begin
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if(msg_blk_word_inpt_cntr == 4'd4 && sm3_msg_valid_i)
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nxt_state = INPT_OTPT;//输入前 5 个原始字后，开始一边输入，一边输出
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else
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nxt_state = INPT_ORGN_5W;
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end
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INPT_OTPT:begin
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if(msg_blk_word_inpt_cntr == 4'd15 && sm3_msg_valid_i)
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nxt_state = EXP_OTPT;//输入所有 16 个原始字后，开始向寄存器组输入扩展字
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else
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nxt_state = INPT_OTPT;
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end
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EXP_OTPT:begin
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if(msg_blk_word_exp_cntr == 6'd48)
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nxt_state = EXP_OTPT_PRE_INPT; //在生成w63（第48个扩展字后）后，允许下一个块预输入
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else
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nxt_state = EXP_OTPT;
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end
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EXP_OTPT_PRE_INPT:begin
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if(msg_blk_word_exp_cntr == 6'd51)
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nxt_state = EXP_OTPT_FIN; //在生成51个扩展字后,转入最后一个扩展字
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else
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nxt_state = EXP_OTPT_PRE_INPT;
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end
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EXP_OTPT_FIN:begin
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if(word_buff_nb_pre_cntr == 2'd0 && ~sm3_msg_valid_i)
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nxt_state = IDLE; //扩展期间无预缓存字，转为idle，等待下次输入
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else if(word_buff_nb_pre_cntr == 2'd3 && sm3_msg_valid_i)
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nxt_state = RPD_SHFT;//4 个预缓存字，转入 RPD_SHFT
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else
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nxt_state = WAT_PRE_INPT_FIN;//存在预缓存字，转入 WAT_PRE_INPT_FIN，等待条件满足
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end
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WAT_PRE_INPT_FIN:begin
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if(word_buff_nb_pre_cntr == 2'd3 && sm3_msg_valid_i)
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nxt_state = RPD_SHFT; //4 个预缓存字，转入 RPD_SHFT
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else
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nxt_state = WAT_PRE_INPT_FIN;//存在预缓存字，转入WAT_PRE_INPT_FIN
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end
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RPD_SHFT:begin
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if(sm3_msg_valid_i)
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nxt_state = INPT_OTPT; //5个原始字输入完毕，开始一边输入，一边输出
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else
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nxt_state = RPD_SHFT;//等待第5个原始字
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end
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default:
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nxt_state = IDLE;
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endcase
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end
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n)
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state <= `STT_W'b1;
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else begin
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state <= nxt_state;
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end
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end
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//扩展电路
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assign word_wj_expand_tmp_1 = word_buff[0] ^ word_buff[7] ^ {word_buff[13][16:0],word_buff[13][31:17]};
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assign word_wj_expand_tmp_2 = {word_wj_expand_tmp_1 ^ {word_wj_expand_tmp_1[16:0],word_wj_expand_tmp_1[31:17]}
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^ {word_wj_expand_tmp_1[8:0],word_wj_expand_tmp_1[31:9]}};
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assign word_wj_expand = word_wj_expand_tmp_2 ^ word_buff[10] ^ {word_buff[3][24:0],word_buff[3][31:25]};
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assign word_wjj_expand = word_buff[11] ^ word_buff[15];//从寄存器后段输出
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//扩展电路输出使能
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assign word_exp_push_reg_ena = (state == EXP_OTPT
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|| state == EXP_OTPT_PRE_INPT
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|| state == EXP_OTPT_FIN
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);
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// 根据当前扩展轮数，确定补充进缓冲区的数据类型：原始数据(0-15) 扩展数据(16-67) 0( >67)
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assign word_buff_new_push = (state == IDLE
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|| state == INPT_ORGN_5W
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|| state == RPD_SHFT
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|| state == INPT_OTPT
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) ? sm3_msg_i :
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word_exp_push_reg_ena ? word_wj_expand :
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32'd0;
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//消息缓冲区 push
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin : buff_init
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integer i;
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for ( i = 0 ; i < WORDS_IN_BLOCK; i = i + 1) begin:buff_init
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word_buff[i] <= 32'd0;
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end
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end
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else if(word_buff_shft_ena)begin : buff_shift // w0 <- w1; w1 <- w2;....w15 <- w_new
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integer i;
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for ( i = WORDS_IN_BLOCK - 1 ; i > 0 ; i = i - 1) begin
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word_buff[i-1] <= word_buff[i];
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end
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word_buff[15] <= word_buff_new_push;
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end
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else if(word_buff_rpd_shft_ena)begin : buff_rpd_shift //快速移位阶段
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word_buff[15] <= sm3_msg_i;
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word_buff[14] <= word_buff_nb_pre[3];
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word_buff[13] <= word_buff_nb_pre[2];
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word_buff[12] <= word_buff_nb_pre[1];
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word_buff[11] <= word_buff_nb_pre[0];
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end
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end
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assign word_buff_shft_ena = (state == IDLE && sm3_msg_valid_i)
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|| (state == INPT_ORGN_5W && sm3_msg_valid_i)
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|| (state == INPT_OTPT && sm3_msg_valid_i)
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|| state == EXP_OTPT
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|| state == EXP_OTPT_PRE_INPT
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|| state == EXP_OTPT_FIN
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;//寄存器组左移使能 20.5.13 fix
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assign word_buff_rpd_shft_ena = state == RPD_SHFT && sm3_msg_valid_i; //缓存区快速移位使能
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//消息预缓冲区
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always @(posedge clk or negedge rst_n) begin
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if(~rst_n) begin : pre_buff_init
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integer i;
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for ( i = 0 ; i < PRE_BUFF_N; i = i + 1) begin : pre_buff_init
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word_buff_nb_pre[i] <= 32'd0;
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end
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end
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else if(word_buff_nb_pre_shft_ena)begin : pre_buff_shift // wnb0 <- wnb1....wnb3 <- input
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integer i;
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for ( i = PRE_BUFF_N - 1 ; i > 0 ; i = i - 1) begin
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word_buff_nb_pre[i-1] <= word_buff_nb_pre[i];
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end
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word_buff_nb_pre[PRE_BUFF_N - 1] <= sm3_msg_i;
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end
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end
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assign word_buff_nb_pre_shft_ena = ( state == EXP_OTPT_PRE_INPT
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|| state == EXP_OTPT_FIN
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|| state == WAT_PRE_INPT_FIN
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) && sm3_msg_valid_i;//预缓冲区移位使能
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//输出控制
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assign sm3_wj_o = word_buff[11];// 从倒数第5个寄存器输出
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assign sm3_wjj_o = word_wjj_expand;
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assign sm3_wj_wjj_valid_o = (state == INPT_OTPT && sm3_msg_valid_i) //20.5.13 fix
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|| state == EXP_OTPT
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|| state == EXP_OTPT_PRE_INPT
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|| state == EXP_OTPT_FIN
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;
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assign sm3_wj_wjj_lst_o = msg_lst_blk_flg && state == EXP_OTPT_FIN;
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assign sm3_msg_rdy_o = sm3_msg_inpt_rdy; //反压控制
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//调试用
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`ifdef SM3_TOP_SIM
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generate
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if(MODULE_SIM) begin
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always@(*) begin
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if(sm3_wj_wjj_valid_o)
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begin
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$display(" %32h|%32h", sm3_wj_o[31:0],sm3_wjj_o[31:0],);
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end
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end
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end
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endgenerate
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`endif
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endmodule
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