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32 lines
759 B
Verilog
32 lines
759 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: SHU
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// Engineer: lf
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//
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// Create Date: 2020/04/26 16:24:02
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// Design Name:
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// Module Name: adder_32b
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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// 32 位 加法器 性能分析用
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module adder_32b(
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input [31:0] A,
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input [31:0] B,
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output [31:0] R
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);
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wire [32:0] R_tmp;
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assign R_tmp = A + B;
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assign R = R_tmp[31:0];
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endmodule
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