mirror of
https://github.com/WangXuan95/USTC-RVSoC.git
synced 2025-01-30 23:02:55 +08:00
243 lines
8.8 KiB
Systemverilog
243 lines
8.8 KiB
Systemverilog
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// 一个能作为naive bus 主设备的调试模块
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// 它接收用户从UART发来的命令，操控复位等信号，或对总线进行读写。用户可以使用UART命令复位整个SoC，上传程序，或者查看运行时的RAM数据。
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// 命令列表(全部命令为ASCII，人类可读, 每个命令使用\r或\n或\r\n或\n\r结尾):
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// 1、复位命令
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// 发送: r\n
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// 效果: 将o_rst_n信号拉低若干个时钟周期
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// 返回: rst done\n
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// 2. w\n : o_run = 1 , return running \n
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// 3. s\n : o_run = 0 , return stoped \n
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// 4. addr=data\n : write [addr] = data , example: 00000100 928cd0f1\n , return : 00000100=928cd0f1 , note:automaticly align address to 4byte
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// 5. addr\n : read [addr] , example: 00000100\n return : 928cd0f1
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//
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module isp_uart #(
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parameter UART_RX_CLK_DIV = 108, // 50MHz/4/115200Hz=108
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parameter UART_TX_CLK_DIV = 434 // 50MHz/1/115200Hz=434
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)(
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input logic clk,
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input logic i_uart_rx,
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output logic o_uart_tx,
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output logic o_rst_n, o_stop,
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naive_bus.master bus
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);
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logic [ 5:0] rst_chain = 3'b0;
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logic rx_ready, rd_ok=1'b0, wr_ok=1'b0, tx_start=1'b0;
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logic [ 7:0] rx_data, rx_binary;
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logic [ 3:0] rx_binary_l;
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logic [31:0] addr=0, wr_data=0;
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logic [ 7:0][ 7:0] rd_data_ascii;
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logic [ 7:0][ 7:0] tx_data = 64'h0;
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enum {NONE, RST, RUN, STOP} cmd=NONE;
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enum {NEW, CMD, ADDR, EQUAL, DATA, FINAL, TRASH} fsm = NEW;
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`define C (rx_data=="r" || rx_data=="w" || rx_data=="s")
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`define S (rx_data==" " || rx_data=="\t" )
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`define E (rx_data=="\n" || rx_data=="\r" )
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`define N ( (rx_data>="0" && rx_data<="9" ) || (rx_data>="a" && rx_data<="f" ) )
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initial o_stop = 1'b0;
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assign o_rst_n = ~(|rst_chain);
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initial begin bus.rd_req = 1'b0; bus.wr_req = 1'b0; bus.rd_addr = 0; bus.wr_addr = 0; bus.wr_data = 0; end
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assign bus.rd_be = 4'hf;
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assign bus.wr_be = 4'hf;
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assign rx_binary_l = rx_binary[3:0];
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always_comb
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if(rx_data>="0" && rx_data<="9" ) begin
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rx_binary = rx_data - "0";
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end else if(rx_data>="a" && rx_data<="f" ) begin
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rx_binary = rx_data - "a" + 8'd10;
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end else begin
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rx_binary = 8'h0;
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end
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uart_rx #(
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.UART_RX_CLK_DIV (UART_RX_CLK_DIV)
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) uart_rx_inst (
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.clk ( clk ),
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.i_rx ( i_uart_rx ),
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.o_ready ( rx_ready ),
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.o_data ( rx_data )
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);
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uart_tx_line #(
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.UART_TX_CLK_DIV (UART_TX_CLK_DIV)
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) uart_tx_line_inst (
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.clk ( clk ),
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.o_tx ( o_uart_tx ),
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.i_start ( tx_start ),
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.i_data ( tx_data )
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);
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generate
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genvar i;
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for(i=0; i<8; i++) begin : convert_binary_to_ascii
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always_comb
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if(bus.rd_data[3+4*i:4*i]>4'h9)
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rd_data_ascii[i] = "a" - 8'd10 + bus.rd_data[3+4*i:4*i];
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else
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rd_data_ascii[i] = "0" + bus.rd_data[3+4*i:4*i];
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end
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endgenerate
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always @ (posedge clk)
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rd_ok <= (bus.rd_req & bus.rd_gnt);
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always @ (posedge clk)
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wr_ok <= (bus.wr_req & bus.wr_gnt);
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always @ (posedge clk)
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if (rd_ok) begin
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tx_start<= 1'b1;
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tx_data <= rd_data_ascii;
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end else if(wr_ok) begin
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tx_start<= 1'b1;
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tx_data <= "wr done ";
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end else if(rx_ready && fsm==CMD && `E) begin
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tx_start<= 1'b1;
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if(cmd==RST)
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tx_data <= "rst done";
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else if(cmd==RUN)
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tx_data <= "running ";
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else if(cmd==STOP)
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tx_data <= "stoped ";
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else
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tx_data <= 64'h0;
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end else begin
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tx_start<= 1'b0;
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tx_data <= 64'h0;
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end
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always @ (posedge clk)
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if(rx_ready && fsm==CMD && `E && cmd==RST)
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rst_chain <= 6'h0;
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else
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rst_chain <= {rst_chain[4:0],1'b0};
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always @ (posedge clk)
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if(rx_ready && fsm==CMD && `E) begin
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if(cmd==RUN)
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o_stop <= 1'b0;
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else
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o_stop <= 1'b1;
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end
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always @ (posedge clk)
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if (bus.rd_req) begin
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if(bus.rd_gnt)
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bus.rd_req <= 1'b0;
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end else if(bus.wr_req) begin
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if(bus.wr_gnt)
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bus.wr_req <= 1'b0;
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end else if( rx_ready ) begin
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case(fsm)
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NEW : if (`C) begin
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fsm <= CMD;
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if(rx_data=="r") begin // check rx_data to see which command it is
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cmd <= RST;
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end else if(rx_data=="w") begin
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cmd <= RUN;
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end else if(rx_data=="s") begin
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cmd <= STOP;
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end else begin
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cmd <= NONE;
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end
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end else if(`S || `E) begin
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fsm <= NEW;
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addr <= 0;
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wr_data <= 0;
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cmd <= NONE;
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end else if(`N) begin
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fsm <= ADDR;
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addr <= {addr[27:0], rx_binary_l}; // get a addr
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end else begin
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fsm <= TRASH;
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end
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CMD : if (`E) begin
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fsm <= NEW; // cmd ok!
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addr <= 0;
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wr_data <= 0;
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cmd <= NONE;
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end else if(`S) begin
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fsm <= CMD;
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end else begin
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fsm <= TRASH;
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end
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ADDR : if (`E) begin
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fsm <= NEW; // get a read command
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bus.rd_req <= 1'b1; // TODO : launch a bus read
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bus.rd_addr <= addr;
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addr <= 0;
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wr_data <= 0;
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cmd <= NONE;
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end else if(`N) begin
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fsm <= ADDR;
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addr <= {addr[27:0], rx_binary_l}; // get a addr
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end else if(`S) begin
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fsm <= EQUAL; // get addr down, waiting for data, maybe a write command
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end else begin
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fsm <= TRASH;
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end
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EQUAL : if (`E) begin
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fsm <= NEW; // get a read command
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bus.rd_req <= 1'b1; // TODO : launch a bus read
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bus.rd_addr <= addr;
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addr <= 0;
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wr_data <= 0;
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cmd <= NONE;
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end else if(`N) begin
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fsm <= DATA; // get a data
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wr_data <= {wr_data[27:0], rx_binary_l}; // get a data
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end else if(`S) begin
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fsm <= EQUAL;
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end else begin
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fsm <= TRASH;
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end
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DATA : if (`E) begin
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fsm <= NEW; // get a write command
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bus.wr_req <= 1'b1; // TODO : launch a bus write
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bus.wr_addr <= addr;
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bus.wr_data <= wr_data;
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addr <= 0;
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wr_data <= 0;
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cmd <= NONE;
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end else if(`N) begin
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fsm <= DATA; // get a data
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wr_data <= {wr_data[27:0], rx_binary_l}; // get a data
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end else if(`S) begin
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fsm <= FINAL; // get data down, waiting for \r or \n
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end else begin
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fsm <= TRASH;
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end
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FINAL : if (`E) begin
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fsm <= NEW; // get a write command
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bus.wr_req <= 1'b1; // TODO : launch a bus write
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bus.wr_addr <= addr;
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bus.wr_data <= wr_data;
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addr <= 0;
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wr_data <= 0;
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cmd <= NONE;
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end else if(`S) begin
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fsm <= FINAL; // get addr down, waiting for \r or \n
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end else begin
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fsm <= TRASH;
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end
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default : if (`E) begin
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// get a syntax error
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fsm <= NEW;
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addr <= 0;
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wr_data <= 0;
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cmd <= NONE;
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end else begin
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fsm <= TRASH;
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end
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endcase
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end
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endmodule
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