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9 lines
206 B
Systemverilog
9 lines
206 B
Systemverilog
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// asm file name: uart_print.S
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module instr_rom(
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input logic clk, rst_n,
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naive_bus.slave bus
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);
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localparam INSTR_CNT = 30'd20;
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wire [0:INSTR_CNT-1] [31:0] instr_rom_cell = {
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