mirror of
https://github.com/WangXuan95/USTC-RVSoC.git
synced 2024-12-24 22:58:56 +08:00
合并ISP-UART和USER-UART，添加Nexys4开发板工程
This commit is contained in:
WangXuan95
parent
b5c93cb6ce
commit
0840f54aa6
@ -10,7 +10,7 @@ version:1
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||||
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@ -29,7 +29,7 @@ version:1
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||||
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||||
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||||
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||||
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||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6c6963656e73655f6d616e616765:31:00:00
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||||
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||||
@ -40,7 +40,7 @@ version:1
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||||
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||||
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|
||||
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||||
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||||
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||||
@ -61,4 +61,4 @@ version:1
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||||
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@ -1,14 +1,14 @@
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||||
version:1
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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@ -18,4 +18,4 @@ version:1
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||||
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70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7570646174657265676964:31:00:00
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||||
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eof:1581560588
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eof:2851928415
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@ -1,4 +1,4 @@
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||||
version:1
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||||
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||||
eof:
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||||
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@ -3,7 +3,7 @@
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||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
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||||
The structure and the elements are likely to change over the next few releases.
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||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Tue Feb 26 19:19:01 2019">
|
||||
<application name="pa" timeStamp="Tue Feb 26 19:42:02 2019">
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<section name="Project Information" visible="false">
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<property name="ProjectID" value="802f49394334431ea9abba122e836e9e" type="ProjectID"/>
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||||
<property name="ProjectIteration" value="12" type="ProjectIteration"/>
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||||
@ -18,15 +18,15 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddSources" value="6" type="JavaHandler"/>
|
||||
<property name="AutoConnectTarget" value="2" type="JavaHandler"/>
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||||
<property name="AutoConnectTarget" value="3" type="JavaHandler"/>
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||||
<property name="CoreView" value="1" type="JavaHandler"/>
|
||||
<property name="CustomizeCore" value="1" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="4" type="JavaHandler"/>
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||||
<property name="LaunchProgramFpga" value="2" type="JavaHandler"/>
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<property name="LaunchProgramFpga" value="3" type="JavaHandler"/>
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<property name="NewProject" value="1" type="JavaHandler"/>
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<property name="OpenHardwareManager" value="6" type="JavaHandler"/>
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<property name="OpenRecentTarget" value="2" type="JavaHandler"/>
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<property name="ProgramDevice" value="2" type="JavaHandler"/>
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||||
<property name="OpenHardwareManager" value="9" type="JavaHandler"/>
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<property name="OpenRecentTarget" value="3" type="JavaHandler"/>
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||||
<property name="ProgramDevice" value="3" type="JavaHandler"/>
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||||
<property name="ReportUtilization" value="1" type="JavaHandler"/>
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||||
<property name="RunBitgen" value="8" type="JavaHandler"/>
|
||||
<property name="RunImplementation" value="3" type="JavaHandler"/>
|
||||
@ -49,7 +49,7 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="CreateSrcFileDialog_FILE_TYPE" value="1" type="GuiHandlerData"/>
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<property name="IPCoreView_TABBED_PANE" value="2" type="GuiHandlerData"/>
|
||||
@ -68,7 +68,7 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="MsgView_WARNING_MESSAGES" value="2" type="GuiHandlerData"/>
|
||||
<property name="NetlistTreeView_NETLIST_TREE" value="11" type="GuiHandlerData"/>
|
||||
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|
||||
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_UPDATE_HIER" value="13" type="GuiHandlerData"/>
|
||||
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|
||||
<property name="PACommandNames_REPORTS_WINDOW" value="1" type="GuiHandlerData"/>
|
||||
@ -79,7 +79,7 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="PAViews_DEVICE" value="2" type="GuiHandlerData"/>
|
||||
<property name="PartChooser_FAMILY_CHOOSER" value="1" type="GuiHandlerData"/>
|
||||
<property name="PartChooser_PARTS" value="2" type="GuiHandlerData"/>
|
||||
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|
||||
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|
||||
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|
||||
<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_PROJECT_NAME" value="2" type="GuiHandlerData"/>
|
||||
@ -101,6 +101,11 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="TaskBanner_CLOSE" value="1" type="GuiHandlerData"/>
|
||||
<property name="TouchpointSurveyDialog_NO" value="1" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
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|
||||
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|
||||
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|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
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||||
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||||
@ -1,5 +0,0 @@
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||||
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||||
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|
||||
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|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="wgg" Host="DESKTOP-C6I6OAQ" Pid="20504">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="wgg" Host="DESKTOP-C6I6OAQ" Pid="20504">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
@ -1,5 +0,0 @@
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||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="wgg" Host="DESKTOP-C6I6OAQ" Pid="20504">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="wgg" Host="DESKTOP-C6I6OAQ" Pid="21308">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
@ -1,5 +0,0 @@
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||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="wgg" Host="DESKTOP-C6I6OAQ" Pid="20504">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
@ -1,244 +0,0 @@
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||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
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||||
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
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|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
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ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
@ -1,63 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
@ -1,166 +0,0 @@
|
||||
#
|
||||
# Report generation script generated by Vivado
|
||||
#
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
proc start_step { step } {
|
||||
set stopFile ".stop.rst"
|
||||
if {[file isfile .stop.rst]} {
|
||||
puts ""
|
||||
puts "*** Halting run - EA reset detected ***"
|
||||
puts ""
|
||||
puts ""
|
||||
return -code error
|
||||
}
|
||||
set beginFile ".$step.begin.rst"
|
||||
set platform "$::tcl_platform(platform)"
|
||||
set user "$::tcl_platform(user)"
|
||||
set pid [pid]
|
||||
set host ""
|
||||
if { [string equal $platform unix] } {
|
||||
if { [info exist ::env(HOSTNAME)] } {
|
||||
set host $::env(HOSTNAME)
|
||||
}
|
||||
} else {
|
||||
if { [info exist ::env(COMPUTERNAME)] } {
|
||||
set host $::env(COMPUTERNAME)
|
||||
}
|
||||
}
|
||||
set ch [open $beginFile w]
|
||||
puts $ch "<?xml version=\"1.0\"?>"
|
||||
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
|
||||
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
|
||||
puts $ch " </Process>"
|
||||
puts $ch "</ProcessHandle>"
|
||||
close $ch
|
||||
}
|
||||
|
||||
proc end_step { step } {
|
||||
set endFile ".$step.end.rst"
|
||||
set ch [open $endFile w]
|
||||
close $ch
|
||||
}
|
||||
|
||||
proc step_failed { step } {
|
||||
set endFile ".$step.error.rst"
|
||||
set ch [open $endFile w]
|
||||
close $ch
|
||||
}
|
||||
|
||||
|
||||
start_step init_design
|
||||
set ACTIVE_STEP init_design
|
||||
set rc [catch {
|
||||
create_msg_db init_design.pb
|
||||
create_project -in_memory -part xc7a100tcsg324-1
|
||||
set_property design_mode GateLvl [current_fileset]
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_property webtalk.parent_dir E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt [current_project]
|
||||
set_property parent.project_path E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr [current_project]
|
||||
set_property ip_output_repo E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
add_files -quiet E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1/Nexys4_USTCRVSoC_top.dcp
|
||||
read_xdc E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc
|
||||
link_design -top Nexys4_USTCRVSoC_top -part xc7a100tcsg324-1
|
||||
close_msg_db -file init_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed init_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step init_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
start_step opt_design
|
||||
set ACTIVE_STEP opt_design
|
||||
set rc [catch {
|
||||
create_msg_db opt_design.pb
|
||||
opt_design
|
||||
write_checkpoint -force Nexys4_USTCRVSoC_top_opt.dcp
|
||||
create_report "impl_1_opt_report_drc_0" "report_drc -file Nexys4_USTCRVSoC_top_drc_opted.rpt -pb Nexys4_USTCRVSoC_top_drc_opted.pb -rpx Nexys4_USTCRVSoC_top_drc_opted.rpx"
|
||||
close_msg_db -file opt_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed opt_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step opt_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
start_step place_design
|
||||
set ACTIVE_STEP place_design
|
||||
set rc [catch {
|
||||
create_msg_db place_design.pb
|
||||
implement_debug_core
|
||||
place_design
|
||||
write_checkpoint -force Nexys4_USTCRVSoC_top_placed.dcp
|
||||
create_report "impl_1_place_report_io_0" "report_io -file Nexys4_USTCRVSoC_top_io_placed.rpt"
|
||||
create_report "impl_1_place_report_utilization_0" "report_utilization -file Nexys4_USTCRVSoC_top_utilization_placed.rpt -pb Nexys4_USTCRVSoC_top_utilization_placed.pb"
|
||||
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file Nexys4_USTCRVSoC_top_control_sets_placed.rpt"
|
||||
close_msg_db -file place_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed place_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step place_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
start_step route_design
|
||||
set ACTIVE_STEP route_design
|
||||
set rc [catch {
|
||||
create_msg_db route_design.pb
|
||||
route_design
|
||||
write_checkpoint -force Nexys4_USTCRVSoC_top_routed.dcp
|
||||
create_report "impl_1_route_report_drc_0" "report_drc -file Nexys4_USTCRVSoC_top_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_drc_routed.rpx"
|
||||
create_report "impl_1_route_report_methodology_0" "report_methodology -file Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_methodology_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_methodology_drc_routed.rpx"
|
||||
create_report "impl_1_route_report_power_0" "report_power -file Nexys4_USTCRVSoC_top_power_routed.rpt -pb Nexys4_USTCRVSoC_top_power_summary_routed.pb -rpx Nexys4_USTCRVSoC_top_power_routed.rpx"
|
||||
create_report "impl_1_route_report_route_status_0" "report_route_status -file Nexys4_USTCRVSoC_top_route_status.rpt -pb Nexys4_USTCRVSoC_top_route_status.pb"
|
||||
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file Nexys4_USTCRVSoC_top_timing_summary_routed.rpt -rpx Nexys4_USTCRVSoC_top_timing_summary_routed.rpx -warn_on_violation "
|
||||
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file Nexys4_USTCRVSoC_top_incremental_reuse_routed.rpt"
|
||||
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file Nexys4_USTCRVSoC_top_clock_utilization_routed.rpt"
|
||||
close_msg_db -file route_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
write_checkpoint -force Nexys4_USTCRVSoC_top_routed_error.dcp
|
||||
step_failed route_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step route_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
start_step write_bitstream
|
||||
set ACTIVE_STEP write_bitstream
|
||||
set rc [catch {
|
||||
create_msg_db write_bitstream.pb
|
||||
catch { write_mem_info -force Nexys4_USTCRVSoC_top.mmi }
|
||||
write_bitstream -force Nexys4_USTCRVSoC_top.bit
|
||||
catch {write_debug_probes -quiet -force Nexys4_USTCRVSoC_top}
|
||||
catch {file copy -force Nexys4_USTCRVSoC_top.ltx debug_nets.ltx}
|
||||
close_msg_db -file write_bitstream.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed write_bitstream
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step write_bitstream
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
@ -1,539 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Tue Feb 26 19:20:55 2019
|
||||
# Process ID: 20504
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1
|
||||
# Command line: vivado.exe -log Nexys4_USTCRVSoC_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Nexys4_USTCRVSoC_top.tcl -notrace
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.vdi
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source Nexys4_USTCRVSoC_top.tcl -notrace
|
||||
Command: link_design -top Nexys4_USTCRVSoC_top -part xc7a100tcsg324-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Netlist 29-17] Analyzing 319 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
|
||||
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc]
|
||||
Finished Parsing XDC File [E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 641.695 ; gain = 348.359
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.526 . Memory (MB): peak = 646.332 ; gain = 4.637
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: 13eadb8e1
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.372 . Memory (MB): peak = 1213.672 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 3 cells
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: 169946815
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.516 . Memory (MB): peak = 1213.672 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 10ac3042c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.618 . Memory (MB): peak = 1213.672 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 18 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
Phase 4 BUFG optimization | Checksum: 10ac3042c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.707 . Memory (MB): peak = 1213.672 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 10ac3042c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.783 . Memory (MB): peak = 1213.672 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1213.672 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 1105aca7b
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.865 . Memory (MB): peak = 1213.672 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Pwropt 34-9] Applying IDT optimizations ...
|
||||
INFO: [Pwropt 34-10] Applying ODC optimizations ...
|
||||
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.769 | TNS=0.000 |
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
|
||||
|
||||
Starting PowerOpt Patch Enables Task
|
||||
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 13 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
|
||||
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
|
||||
Number of BRAM Ports augmented: 0 newly gated: 5 Total Ports: 26
|
||||
Ending PowerOpt Patch Enables Task | Checksum: 15ce38535
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Ending Power Optimization Task | Checksum: 15ce38535
|
||||
|
||||
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1415.492 ; gain = 201.820
|
||||
|
||||
Starting Logic Optimization Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 1 Remap
|
||||
Phase 1 Remap | Checksum: 16c4c4a0f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.386 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Remap created 5 cells and removed 10 cells
|
||||
Ending Logic Optimization Task | Checksum: 16c4c4a0f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.397 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
opt_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 1415.492 ; gain = 773.797
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file Nexys4_USTCRVSoC_top_drc_opted.rpt -pb Nexys4_USTCRVSoC_top_drc_opted.pb -rpx Nexys4_USTCRVSoC_top_drc_opted.rpx
|
||||
Command: report_drc -file Nexys4_USTCRVSoC_top_drc_opted.rpt -pb Nexys4_USTCRVSoC_top_drc_opted.pb -rpx Nexys4_USTCRVSoC_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [Chipscope 16-241] No debug cores found in the current design.
|
||||
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
|
||||
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_memwrite_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[16]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[17]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[19]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[21]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[22]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[23]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[24]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[25]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[26]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[28]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[29]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[30]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[31]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 21 Warnings
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 40e63c3d
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 19c12ad57
|
||||
|
||||
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 2654ed21f
|
||||
|
||||
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 2654ed21f
|
||||
|
||||
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 2654ed21f
|
||||
|
||||
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
Phase 2 Global Placement | Checksum: 26f8edad2
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 26f8edad2
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 244c6aa9d
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 1e06eec96
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 20a4c2c3c
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 2da3e0599
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 1f5000c7e
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 1f5000c7e
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: 1f5000c7e
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: a6f92177
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
|
||||
INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: a6f92177
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.882. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 4dee693a
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 4dee693a
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 4dee693a
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 4dee693a
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: a535ead8
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: a535ead8
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: 9fd0d3a8
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
54 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
place_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:12 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.499 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file Nexys4_USTCRVSoC_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file Nexys4_USTCRVSoC_top_utilization_placed.rpt -pb Nexys4_USTCRVSoC_top_utilization_placed.pb
|
||||
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file Nexys4_USTCRVSoC_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: e685d48 ConstDB: 0 ShapeSum: 91687660 RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: 7fa797b6
|
||||
|
||||
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1422.488 ; gain = 6.996
|
||||
Post Restoration Checksum: NetGraph: 29d8a759 NumContArr: 55cef05d Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: 7fa797b6
|
||||
|
||||
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1422.488 ; gain = 6.996
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: 7fa797b6
|
||||
|
||||
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1422.488 ; gain = 6.996
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: 7fa797b6
|
||||
|
||||
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1422.488 ; gain = 6.996
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: 28a805e33
|
||||
|
||||
Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.796 | TNS=0.000 | WHS=0.007 | THS=0.000 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 292708314
|
||||
|
||||
Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 212fd4de5
|
||||
|
||||
Time (s): cpu = 00:00:33 ; elapsed = 00:00:28 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 1074
|
||||
Number of Nodes with overlaps = 9
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.421 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 1eeceb63b
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
Phase 4 Rip-up And Reroute | Checksum: 1eeceb63b
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 1eeceb63b
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 1eeceb63b
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 1eeceb63b
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 1cac9a9f3
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.517 | TNS=0.000 | WHS=0.401 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 1cac9a9f3
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
Phase 6 Post Hold Fix | Checksum: 1cac9a9f3
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 1.46077 %
|
||||
Global Horizontal Routing Utilization = 1.79511 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 1cac9a9f3
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 1cac9a9f3
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 1aca853e4
|
||||
|
||||
Time (s): cpu = 00:00:38 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.517 | TNS=0.000 | WHS=0.401 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 1aca853e4
|
||||
|
||||
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
70 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:40 ; elapsed = 00:00:31 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.667 . Memory (MB): peak = 1436.664 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file Nexys4_USTCRVSoC_top_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_drc_routed.rpx
|
||||
Command: report_drc -file Nexys4_USTCRVSoC_top_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_methodology_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_methodology_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file Nexys4_USTCRVSoC_top_power_routed.rpt -pb Nexys4_USTCRVSoC_top_power_summary_routed.pb -rpx Nexys4_USTCRVSoC_top_power_routed.rpx
|
||||
Command: report_power -file Nexys4_USTCRVSoC_top_power_routed.rpt -pb Nexys4_USTCRVSoC_top_power_summary_routed.pb -rpx Nexys4_USTCRVSoC_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
82 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file Nexys4_USTCRVSoC_top_route_status.rpt -pb Nexys4_USTCRVSoC_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Nexys4_USTCRVSoC_top_timing_summary_routed.rpt -rpx Nexys4_USTCRVSoC_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file Nexys4_USTCRVSoC_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file Nexys4_USTCRVSoC_top_clock_utilization_routed.rpt
|
||||
Command: write_bitstream -force Nexys4_USTCRVSoC_top.bit
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
Running DRC as a precondition to command write_bitstream
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
|
||||
|
||||
set_property CFGBVS value1 [current_design]
|
||||
#where value1 is either VCCO or GND
|
||||
|
||||
set_property CONFIG_VOLTAGE value2 [current_design]
|
||||
#where value2 is the voltage provided to configuration bank 0
|
||||
|
||||
Refer to the device configuration user guide for more information.
|
||||
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_memwrite_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[16]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[17]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[19]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[21]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[22]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[23]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[24]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[25]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[26]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[28]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[29]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[30]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[31]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 22 Warnings
|
||||
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
||||
INFO: [Project 1-821] Please set project.enableDesignId to be 'true'.
|
||||
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
|
||||
Loading data files...
|
||||
Loading site data...
|
||||
Loading route data...
|
||||
Processing options...
|
||||
Creating bitmap...
|
||||
Creating bitstream...
|
||||
Writing bitstream ./Nexys4_USTCRVSoC_top.bit...
|
||||
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
||||
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
|
||||
INFO: [Common 17-186] 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Feb 26 19:22:42 2019. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2017.4/doc/webtalk_introduction.html.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
100 Infos, 43 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
write_bitstream completed successfully
|
||||
write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1910.711 ; gain = 447.070
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Feb 26 19:22:42 2019...
|
||||
@ -1,506 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Tue Feb 26 17:56:46 2019
|
||||
# Process ID: 520
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1
|
||||
# Command line: vivado.exe -log Nexys4_USTCRVSoC_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Nexys4_USTCRVSoC_top.tcl -notrace
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.vdi
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source Nexys4_USTCRVSoC_top.tcl -notrace
|
||||
Command: link_design -top Nexys4_USTCRVSoC_top -part xc7a100tcsg324-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Netlist 29-17] Analyzing 319 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
|
||||
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc]
|
||||
Finished Parsing XDC File [E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 642.496 ; gain = 349.480
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.539 . Memory (MB): peak = 651.313 ; gain = 8.816
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: f6786b86
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.357 . Memory (MB): peak = 1213.191 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 3 cells
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: 197279e5e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.502 . Memory (MB): peak = 1213.191 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: bf162ee0
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.604 . Memory (MB): peak = 1213.191 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 18 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
Phase 4 BUFG optimization | Checksum: bf162ee0
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.694 . Memory (MB): peak = 1213.191 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: bf162ee0
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.771 . Memory (MB): peak = 1213.191 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1213.191 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 184e8243e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.856 . Memory (MB): peak = 1213.191 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Pwropt 34-9] Applying IDT optimizations ...
|
||||
INFO: [Pwropt 34-10] Applying ODC optimizations ...
|
||||
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.769 | TNS=0.000 |
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
|
||||
|
||||
Starting PowerOpt Patch Enables Task
|
||||
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 13 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
|
||||
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
|
||||
Number of BRAM Ports augmented: 0 newly gated: 5 Total Ports: 26
|
||||
Ending PowerOpt Patch Enables Task | Checksum: 53b43e8f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
Ending Power Optimization Task | Checksum: 53b43e8f
|
||||
|
||||
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1418.734 ; gain = 205.543
|
||||
|
||||
Starting Logic Optimization Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 1 Remap
|
||||
Phase 1 Remap | Checksum: fa17b0bc
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.381 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Remap created 5 cells and removed 10 cells
|
||||
Ending Logic Optimization Task | Checksum: fa17b0bc
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.392 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
opt_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 1418.734 ; gain = 776.238
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file Nexys4_USTCRVSoC_top_drc_opted.rpt -pb Nexys4_USTCRVSoC_top_drc_opted.pb -rpx Nexys4_USTCRVSoC_top_drc_opted.rpx
|
||||
Command: report_drc -file Nexys4_USTCRVSoC_top_drc_opted.rpt -pb Nexys4_USTCRVSoC_top_drc_opted.pb -rpx Nexys4_USTCRVSoC_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [Chipscope 16-241] No debug cores found in the current design.
|
||||
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
|
||||
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_memwrite_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[16]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[17]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[18]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[19]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[21]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[22]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[23]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[24]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[25]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[27]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[28]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[29]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[31]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 21 Warnings
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d5f6be65
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 19141b54c
|
||||
|
||||
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 26e6ee7f4
|
||||
|
||||
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 26e6ee7f4
|
||||
|
||||
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 26e6ee7f4
|
||||
|
||||
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
Phase 2 Global Placement | Checksum: 279477d6a
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 279477d6a
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 15cdba6a9
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 206e90d49
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 1805ce344
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 14ba068f7
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 1117e4fa0
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 1117e4fa0
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: 1117e4fa0
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: a197169c
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
|
||||
INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: a197169c
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.867. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 5dd8f8be
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 5dd8f8be
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 5dd8f8be
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 5dd8f8be
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 2f1f95ac
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2f1f95ac
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: 2d3cbfee
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
54 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.499 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file Nexys4_USTCRVSoC_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file Nexys4_USTCRVSoC_top_utilization_placed.rpt -pb Nexys4_USTCRVSoC_top_utilization_placed.pb
|
||||
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.076 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file Nexys4_USTCRVSoC_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1418.734 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: 1dafca7a ConstDB: 0 ShapeSum: f8cf574 RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: 107e60b4f
|
||||
|
||||
Time (s): cpu = 00:00:30 ; elapsed = 00:00:27 . Memory (MB): peak = 1427.777 ; gain = 9.043
|
||||
Post Restoration Checksum: NetGraph: 7d407409 NumContArr: 8aa59746 Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: 107e60b4f
|
||||
|
||||
Time (s): cpu = 00:00:30 ; elapsed = 00:00:27 . Memory (MB): peak = 1427.777 ; gain = 9.043
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: 107e60b4f
|
||||
|
||||
Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1427.777 ; gain = 9.043
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: 107e60b4f
|
||||
|
||||
Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1427.777 ; gain = 9.043
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: 1bb8b35b4
|
||||
|
||||
Time (s): cpu = 00:00:33 ; elapsed = 00:00:28 . Memory (MB): peak = 1431.434 ; gain = 12.699
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.781 | TNS=0.000 | WHS=0.001 | THS=0.000 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 1ecbd7787
|
||||
|
||||
Time (s): cpu = 00:00:33 ; elapsed = 00:00:28 . Memory (MB): peak = 1431.434 ; gain = 12.699
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 145a48684
|
||||
|
||||
Time (s): cpu = 00:00:35 ; elapsed = 00:00:29 . Memory (MB): peak = 1431.434 ; gain = 12.699
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 1072
|
||||
Number of Nodes with overlaps = 5
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.142 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 2356a8003
|
||||
|
||||
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
|
||||
Phase 4 Rip-up And Reroute | Checksum: 2356a8003
|
||||
|
||||
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 2356a8003
|
||||
|
||||
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 2356a8003
|
||||
|
||||
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 2356a8003
|
||||
|
||||
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 2220221b5
|
||||
|
||||
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.238 | TNS=0.000 | WHS=0.472 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 2220221b5
|
||||
|
||||
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
|
||||
Phase 6 Post Hold Fix | Checksum: 2220221b5
|
||||
|
||||
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 1.49872 %
|
||||
Global Horizontal Routing Utilization = 1.8604 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 2220221b5
|
||||
|
||||
Time (s): cpu = 00:00:39 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 2220221b5
|
||||
|
||||
Time (s): cpu = 00:00:39 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 25b5d5941
|
||||
|
||||
Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 1431.434 ; gain = 12.699
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.238 | TNS=0.000 | WHS=0.472 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 25b5d5941
|
||||
|
||||
Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 1431.434 ; gain = 12.699
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 1431.434 ; gain = 12.699
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
70 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 1431.434 ; gain = 12.699
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.673 . Memory (MB): peak = 1431.434 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file Nexys4_USTCRVSoC_top_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_drc_routed.rpx
|
||||
Command: report_drc -file Nexys4_USTCRVSoC_top_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_methodology_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_methodology_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file Nexys4_USTCRVSoC_top_power_routed.rpt -pb Nexys4_USTCRVSoC_top_power_summary_routed.pb -rpx Nexys4_USTCRVSoC_top_power_routed.rpx
|
||||
Command: report_power -file Nexys4_USTCRVSoC_top_power_routed.rpt -pb Nexys4_USTCRVSoC_top_power_summary_routed.pb -rpx Nexys4_USTCRVSoC_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
82 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file Nexys4_USTCRVSoC_top_route_status.rpt -pb Nexys4_USTCRVSoC_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Nexys4_USTCRVSoC_top_timing_summary_routed.rpt -rpx Nexys4_USTCRVSoC_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file Nexys4_USTCRVSoC_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file Nexys4_USTCRVSoC_top_clock_utilization_routed.rpt
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Feb 26 17:58:16 2019...
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Tue Feb 26 19:10:27 2019
|
||||
# Process ID: 17984
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1
|
||||
# Command line: vivado.exe -log Nexys4_USTCRVSoC_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Nexys4_USTCRVSoC_top.tcl -notrace
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.vdi
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source Nexys4_USTCRVSoC_top.tcl -notrace
|
||||
|
||||
*** Halting run - EA reset detected ***
|
||||
|
||||
|
||||
|
||||
while executing
|
||||
"start_step write_bitstream"
|
||||
(file "Nexys4_USTCRVSoC_top.tcl" line 64)
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Feb 26 19:10:35 2019...
|
||||
Binary file not shown.
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@ -1,223 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="impl_1" LaunchPart="xc7a100tcsg324-1" LaunchTime="1551179941">
|
||||
<File Type="PWROPT-DCP" Name="Nexys4_USTCRVSoC_top_pwropt.dcp"/>
|
||||
<File Type="ROUTE-PWR" Name="Nexys4_USTCRVSoC_top_power_routed.rpt"/>
|
||||
<File Type="PA-TCL" Name="Nexys4_USTCRVSoC_top.tcl"/>
|
||||
<File Type="ROUTE-PWR-SUM" Name="Nexys4_USTCRVSoC_top_power_summary_routed.pb"/>
|
||||
<File Type="REPORTS-TCL" Name="Nexys4_USTCRVSoC_top_reports.tcl"/>
|
||||
<File Type="BG-DRC" Name="Nexys4_USTCRVSoC_top.drc"/>
|
||||
<File Type="OPT-METHODOLOGY-DRC" Name="Nexys4_USTCRVSoC_top_methodology_drc_opted.rpt"/>
|
||||
<File Type="INIT-TIMING" Name="Nexys4_USTCRVSoC_top_timing_summary_init.rpt"/>
|
||||
<File Type="OPT-HWDEF" Name="Nexys4_USTCRVSoC_top.hwdef"/>
|
||||
<File Type="OPT-DCP" Name="Nexys4_USTCRVSoC_top_opt.dcp"/>
|
||||
<File Type="OPT-DRC" Name="Nexys4_USTCRVSoC_top_drc_opted.rpt"/>
|
||||
<File Type="OPT-TIMING" Name="Nexys4_USTCRVSoC_top_timing_summary_opted.rpt"/>
|
||||
<File Type="PWROPT-DRC" Name="Nexys4_USTCRVSoC_top_drc_pwropted.rpt"/>
|
||||
<File Type="PWROPT-TIMING" Name="Nexys4_USTCRVSoC_top_timing_summary_pwropted.rpt"/>
|
||||
<File Type="PLACE-DCP" Name="Nexys4_USTCRVSoC_top_placed.dcp"/>
|
||||
<File Type="PLACE-IO" Name="Nexys4_USTCRVSoC_top_io_placed.rpt"/>
|
||||
<File Type="PLACE-CLK" Name="Nexys4_USTCRVSoC_top_clock_utilization_placed.rpt"/>
|
||||
<File Type="PLACE-UTIL" Name="Nexys4_USTCRVSoC_top_utilization_placed.rpt"/>
|
||||
<File Type="PLACE-UTIL-PB" Name="Nexys4_USTCRVSoC_top_utilization_placed.pb"/>
|
||||
<File Type="PLACE-CTRL" Name="Nexys4_USTCRVSoC_top_control_sets_placed.rpt"/>
|
||||
<File Type="PLACE-SIMILARITY" Name="Nexys4_USTCRVSoC_top_incremental_reuse_placed.rpt"/>
|
||||
<File Type="PLACE-PRE-SIMILARITY" Name="Nexys4_USTCRVSoC_top_incremental_reuse_pre_placed.rpt"/>
|
||||
<File Type="PLACE-TIMING" Name="Nexys4_USTCRVSoC_top_timing_summary_placed.rpt"/>
|
||||
<File Type="POSTPLACE-PWROPT-DCP" Name="Nexys4_USTCRVSoC_top_postplace_pwropt.dcp"/>
|
||||
<File Type="POSTPLACE-PWROPT-TIMING" Name="Nexys4_USTCRVSoC_top_timing_summary_postplace_pwropted.rpt"/>
|
||||
<File Type="PHYSOPT-DCP" Name="Nexys4_USTCRVSoC_top_physopt.dcp"/>
|
||||
<File Type="PHYSOPT-DRC" Name="Nexys4_USTCRVSoC_top_drc_physopted.rpt"/>
|
||||
<File Type="BG-BIT" Name="Nexys4_USTCRVSoC_top.bit"/>
|
||||
<File Type="PHYSOPT-TIMING" Name="Nexys4_USTCRVSoC_top_timing_summary_physopted.rpt"/>
|
||||
<File Type="ROUTE-ERROR-DCP" Name="Nexys4_USTCRVSoC_top_routed_error.dcp"/>
|
||||
<File Type="ROUTE-DCP" Name="Nexys4_USTCRVSoC_top_routed.dcp"/>
|
||||
<File Type="ROUTE-BLACKBOX-DCP" Name="Nexys4_USTCRVSoC_top_routed_bb.dcp"/>
|
||||
<File Type="ROUTE-DRC" Name="Nexys4_USTCRVSoC_top_drc_routed.rpt"/>
|
||||
<File Type="ROUTE-DRC-PB" Name="Nexys4_USTCRVSoC_top_drc_routed.pb"/>
|
||||
<File Type="BITSTR-MSK" Name="Nexys4_USTCRVSoC_top.msk"/>
|
||||
<File Type="ROUTE-DRC-RPX" Name="Nexys4_USTCRVSoC_top_drc_routed.rpx"/>
|
||||
<File Type="BG-BGN" Name="Nexys4_USTCRVSoC_top.bgn"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC" Name="Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt"/>
|
||||
<File Type="BITSTR-RBT" Name="Nexys4_USTCRVSoC_top.rbt"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="Nexys4_USTCRVSoC_top_methodology_drc_routed.rpx"/>
|
||||
<File Type="BG-BIN" Name="Nexys4_USTCRVSoC_top.bin"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="Nexys4_USTCRVSoC_top_methodology_drc_routed.pb"/>
|
||||
<File Type="ROUTE-PWR-RPX" Name="Nexys4_USTCRVSoC_top_power_routed.rpx"/>
|
||||
<File Type="ROUTE-STATUS" Name="Nexys4_USTCRVSoC_top_route_status.rpt"/>
|
||||
<File Type="ROUTE-STATUS-PB" Name="Nexys4_USTCRVSoC_top_route_status.pb"/>
|
||||
<File Type="ROUTE-TIMINGSUMMARY" Name="Nexys4_USTCRVSoC_top_timing_summary_routed.rpt"/>
|
||||
<File Type="ROUTE-TIMING-PB" Name="Nexys4_USTCRVSoC_top_timing_summary_routed.pb"/>
|
||||
<File Type="ROUTE-TIMING-RPX" Name="Nexys4_USTCRVSoC_top_timing_summary_routed.rpx"/>
|
||||
<File Type="ROUTE-SIMILARITY" Name="Nexys4_USTCRVSoC_top_incremental_reuse_routed.rpt"/>
|
||||
<File Type="RDI-RDI" Name="Nexys4_USTCRVSoC_top.vdi"/>
|
||||
<File Type="ROUTE-CLK" Name="Nexys4_USTCRVSoC_top_clock_utilization_routed.rpt"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-DCP" Name="Nexys4_USTCRVSoC_top_postroute_physopt.dcp"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="Nexys4_USTCRVSoC_top_postroute_physopt_bb.dcp"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="Nexys4_USTCRVSoC_top_timing_summary_postroute_physopted.rpt"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="Nexys4_USTCRVSoC_top_timing_summary_postroute_physopted.pb"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="Nexys4_USTCRVSoC_top_timing_summary_postroute_physopted.rpx"/>
|
||||
<File Type="BITSTR-NKY" Name="Nexys4_USTCRVSoC_top.nky"/>
|
||||
<File Type="BITSTR-BMM" Name="Nexys4_USTCRVSoC_top_bd.bmm"/>
|
||||
<File Type="BITSTR-MMI" Name="Nexys4_USTCRVSoC_top.mmi"/>
|
||||
<File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
|
||||
<File Type="BITSTR-LTX" Name="Nexys4_USTCRVSoC_top.ltx"/>
|
||||
<File Type="BITSTR-SYSDEF" Name="Nexys4_USTCRVSoC_top.sysdef"/>
|
||||
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../../RTL/core_alu.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_bus_wrapper.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_ex_branch_judge.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_id_stage.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_regfile.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_top.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/instr_rom.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/isp_uart.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/naive_bus.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/naive_bus_router.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/ram.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/ram_bus_wrapper.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/soc_top.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/uart_rx.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/uart_tx_line.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/user_uart_tx.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/video_ram.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/Nexys4_USTCRVSoC_top.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="Nexys4_USTCRVSoC_top"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/Nexys-A7-100T-Master.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
@ -1,9 +0,0 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log Nexys4_USTCRVSoC_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Nexys4_USTCRVSoC_top.tcl -notrace
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1,31 +0,0 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6464633833343066316562613462386262623037366131316239623832303238:506172656e742050412070726f6a656374204944:00
|
||||
eof:566565886
|
||||
Binary file not shown.
@ -1,40 +0,0 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "C:/Xilinx/SDK/2017.4/bin;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2017.4/bin;";
|
||||
} else {
|
||||
PathVal = "C:/Xilinx/SDK/2017.4/bin;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2017.4/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
// pre-commands:
|
||||
ISETouchFile( "init_design", "begin" );
|
||||
ISEStep( "vivado",
|
||||
"-log Nexys4_USTCRVSoC_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Nexys4_USTCRVSoC_top.tcl -notrace" );
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
@ -1,10 +0,0 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
@ -1,538 +0,0 @@
|
||||
|
||||
*** Running vivado
|
||||
with args -log Nexys4_USTCRVSoC_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Nexys4_USTCRVSoC_top.tcl -notrace
|
||||
|
||||
|
||||
****** Vivado v2017.4 (64-bit)
|
||||
**** SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
**** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source Nexys4_USTCRVSoC_top.tcl -notrace
|
||||
Command: link_design -top Nexys4_USTCRVSoC_top -part xc7a100tcsg324-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Netlist 29-17] Analyzing 319 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
|
||||
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc]
|
||||
Finished Parsing XDC File [E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 641.695 ; gain = 348.359
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.526 . Memory (MB): peak = 646.332 ; gain = 4.637
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: 13eadb8e1
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.372 . Memory (MB): peak = 1213.672 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 3 cells
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: 169946815
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.516 . Memory (MB): peak = 1213.672 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 10ac3042c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.618 . Memory (MB): peak = 1213.672 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 18 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
Phase 4 BUFG optimization | Checksum: 10ac3042c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.707 . Memory (MB): peak = 1213.672 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 10ac3042c
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.783 . Memory (MB): peak = 1213.672 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1213.672 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 1105aca7b
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.865 . Memory (MB): peak = 1213.672 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Pwropt 34-9] Applying IDT optimizations ...
|
||||
INFO: [Pwropt 34-10] Applying ODC optimizations ...
|
||||
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.769 | TNS=0.000 |
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
|
||||
|
||||
Starting PowerOpt Patch Enables Task
|
||||
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 13 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
|
||||
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
|
||||
Number of BRAM Ports augmented: 0 newly gated: 5 Total Ports: 26
|
||||
Ending PowerOpt Patch Enables Task | Checksum: 15ce38535
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Ending Power Optimization Task | Checksum: 15ce38535
|
||||
|
||||
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1415.492 ; gain = 201.820
|
||||
|
||||
Starting Logic Optimization Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 1 Remap
|
||||
Phase 1 Remap | Checksum: 16c4c4a0f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.386 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Remap created 5 cells and removed 10 cells
|
||||
Ending Logic Optimization Task | Checksum: 16c4c4a0f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.397 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
opt_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 1415.492 ; gain = 773.797
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file Nexys4_USTCRVSoC_top_drc_opted.rpt -pb Nexys4_USTCRVSoC_top_drc_opted.pb -rpx Nexys4_USTCRVSoC_top_drc_opted.rpx
|
||||
Command: report_drc -file Nexys4_USTCRVSoC_top_drc_opted.rpt -pb Nexys4_USTCRVSoC_top_drc_opted.pb -rpx Nexys4_USTCRVSoC_top_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [Chipscope 16-241] No debug cores found in the current design.
|
||||
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
|
||||
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_memwrite_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[16]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[17]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[19]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[21]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[22]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[23]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[24]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[25]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[26]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[28]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[29]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[30]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[31]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 21 Warnings
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 40e63c3d
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 19c12ad57
|
||||
|
||||
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 2654ed21f
|
||||
|
||||
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 2654ed21f
|
||||
|
||||
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 2654ed21f
|
||||
|
||||
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
Phase 2 Global Placement | Checksum: 26f8edad2
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 26f8edad2
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 244c6aa9d
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 1e06eec96
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 20a4c2c3c
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 2da3e0599
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 1f5000c7e
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 1f5000c7e
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: 1f5000c7e
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: a6f92177
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
|
||||
INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: a6f92177
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.882. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1 Post Placement Optimization | Checksum: 4dee693a
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 4dee693a
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 4dee693a
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 4dee693a
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: a535ead8
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: a535ead8
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: 9fd0d3a8
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
54 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
place_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:12 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.499 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file Nexys4_USTCRVSoC_top_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file Nexys4_USTCRVSoC_top_utilization_placed.rpt -pb Nexys4_USTCRVSoC_top_utilization_placed.pb
|
||||
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file Nexys4_USTCRVSoC_top_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1415.492 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: e685d48 ConstDB: 0 ShapeSum: 91687660 RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: 7fa797b6
|
||||
|
||||
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1422.488 ; gain = 6.996
|
||||
Post Restoration Checksum: NetGraph: 29d8a759 NumContArr: 55cef05d Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Create Timer
|
||||
Phase 2.1 Create Timer | Checksum: 7fa797b6
|
||||
|
||||
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1422.488 ; gain = 6.996
|
||||
|
||||
Phase 2.2 Fix Topology Constraints
|
||||
Phase 2.2 Fix Topology Constraints | Checksum: 7fa797b6
|
||||
|
||||
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1422.488 ; gain = 6.996
|
||||
|
||||
Phase 2.3 Pre Route Cleanup
|
||||
Phase 2.3 Pre Route Cleanup | Checksum: 7fa797b6
|
||||
|
||||
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1422.488 ; gain = 6.996
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.4 Update Timing
|
||||
Phase 2.4 Update Timing | Checksum: 28a805e33
|
||||
|
||||
Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.796 | TNS=0.000 | WHS=0.007 | THS=0.000 |
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 292708314
|
||||
|
||||
Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 212fd4de5
|
||||
|
||||
Time (s): cpu = 00:00:33 ; elapsed = 00:00:28 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 1074
|
||||
Number of Nodes with overlaps = 9
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.421 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 1eeceb63b
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
Phase 4 Rip-up And Reroute | Checksum: 1eeceb63b
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 1eeceb63b
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 1eeceb63b
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 1eeceb63b
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 1cac9a9f3
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.517 | TNS=0.000 | WHS=0.401 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 1cac9a9f3
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
Phase 6 Post Hold Fix | Checksum: 1cac9a9f3
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 1.46077 %
|
||||
Global Horizontal Routing Utilization = 1.79511 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 1cac9a9f3
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 1cac9a9f3
|
||||
|
||||
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 1aca853e4
|
||||
|
||||
Time (s): cpu = 00:00:38 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.517 | TNS=0.000 | WHS=0.401 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 1aca853e4
|
||||
|
||||
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
70 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:40 ; elapsed = 00:00:31 . Memory (MB): peak = 1436.664 ; gain = 21.172
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.667 . Memory (MB): peak = 1436.664 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file Nexys4_USTCRVSoC_top_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_drc_routed.rpx
|
||||
Command: report_drc -file Nexys4_USTCRVSoC_top_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_methodology_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_methodology_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file Nexys4_USTCRVSoC_top_power_routed.rpt -pb Nexys4_USTCRVSoC_top_power_summary_routed.pb -rpx Nexys4_USTCRVSoC_top_power_routed.rpx
|
||||
Command: report_power -file Nexys4_USTCRVSoC_top_power_routed.rpt -pb Nexys4_USTCRVSoC_top_power_summary_routed.pb -rpx Nexys4_USTCRVSoC_top_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
82 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file Nexys4_USTCRVSoC_top_route_status.rpt -pb Nexys4_USTCRVSoC_top_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Nexys4_USTCRVSoC_top_timing_summary_routed.rpt -rpx Nexys4_USTCRVSoC_top_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file Nexys4_USTCRVSoC_top_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file Nexys4_USTCRVSoC_top_clock_utilization_routed.rpt
|
||||
Command: write_bitstream -force Nexys4_USTCRVSoC_top.bit
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
|
||||
Running DRC as a precondition to command write_bitstream
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
|
||||
|
||||
set_property CFGBVS value1 [current_design]
|
||||
#where value1 is either VCCO or GND
|
||||
|
||||
set_property CONFIG_VOLTAGE value2 [current_design]
|
||||
#where value2 is the voltage provided to configuration bank 0
|
||||
|
||||
Refer to the device configuration user guide for more information.
|
||||
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_memwrite_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[16]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[17]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[19]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[21]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[22]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[23]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[24]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[25]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[26]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[28]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[29]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[30]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[31]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 22 Warnings
|
||||
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
||||
INFO: [Project 1-821] Please set project.enableDesignId to be 'true'.
|
||||
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
|
||||
Loading data files...
|
||||
Loading site data...
|
||||
Loading route data...
|
||||
Processing options...
|
||||
Creating bitmap...
|
||||
Creating bitstream...
|
||||
Writing bitstream ./Nexys4_USTCRVSoC_top.bit...
|
||||
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
||||
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
|
||||
INFO: [Common 17-186] 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Feb 26 19:22:42 2019. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2017.4/doc/webtalk_introduction.html.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
100 Infos, 43 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
write_bitstream completed successfully
|
||||
write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1910.711 ; gain = 447.070
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Feb 26 19:22:42 2019...
|
||||
@ -1,47 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
|
||||
exit
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=C:/Xilinx/SDK/2017.4/bin;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2017.4/bin
|
||||
else
|
||||
PATH=C:/Xilinx/SDK/2017.4/bin;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2017.4/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
# pre-commands:
|
||||
/bin/touch .init_design.begin.rst
|
||||
EAStep vivado -log Nexys4_USTCRVSoC_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Nexys4_USTCRVSoC_top.tcl -notrace
|
||||
|
||||
|
||||
@ -1,776 +0,0 @@
|
||||
<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2086221</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Tue Feb 26 19:22:38 2019</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2017.4 (64-bit)</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>ddc8340f1eba4b8bbb076a11b9b82028</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>4</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>e0d099809a2653d599a90285146ff6f4</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>e0d099809a2653d599a90285146ff6f4</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7a100t</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>artix7</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>csg324</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
|
||||
</TR> </TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i7-8750H CPU @ 2.20GHz</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2208 MHz</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Microsoft Windows 8 or later , 64-bit</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release (build 9200)</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>25.000 GB</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
|
||||
</TR> </TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>addsrcwizard_specify_hdl_netlist_block_design=2</TD>
|
||||
<TD>basedialog_cancel=3</TD>
|
||||
<TD>basedialog_ok=16</TD>
|
||||
<TD>commandsinput_type_tcl_command_here=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>constraintschooserpanel_add_files=1</TD>
|
||||
<TD>constraintschooserpanel_create_file=1</TD>
|
||||
<TD>coretreetablepanel_core_tree_table=3</TD>
|
||||
<TD>createconstraintsfilepanel_file_name=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>createsrcfiledialog_file_name=1</TD>
|
||||
<TD>createsrcfiledialog_file_type=1</TD>
|
||||
<TD>filesetpanel_file_set_panel_tree=107</TD>
|
||||
<TD>flownavigatortreepanel_flow_navigator_tree=13</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>gettingstartedview_create_new_project=1</TD>
|
||||
<TD>hcodeeditor_search_text_combo_box=7</TD>
|
||||
<TD>ipcoreview_tabbed_pane=2</TD>
|
||||
<TD>logmonitor_monitor=3</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>mainmenumgr_file=2</TD>
|
||||
<TD>mainmenumgr_help=4</TD>
|
||||
<TD>mainmenumgr_tools=1</TD>
|
||||
<TD>mainmenumgr_view=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>mainmenumgr_window=2</TD>
|
||||
<TD>maintoolbarmgr_run=8</TD>
|
||||
<TD>mainwinmenumgr_layout=2</TD>
|
||||
<TD>messagewithoptiondialog_dont_show_this_dialog_again=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>msgtreepanel_message_severity=2</TD>
|
||||
<TD>msgtreepanel_message_view_tree=41</TD>
|
||||
<TD>msgview_critical_warnings=5</TD>
|
||||
<TD>msgview_warning_messages=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>netlisttreeview_netlist_tree=11</TD>
|
||||
<TD>pacommandnames_add_sources=6</TD>
|
||||
<TD>pacommandnames_auto_connect_target=2</TD>
|
||||
<TD>pacommandnames_auto_update_hier=13</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>pacommandnames_license_manage=1</TD>
|
||||
<TD>pacommandnames_reports_window=1</TD>
|
||||
<TD>pacommandnames_run_bitgen=8</TD>
|
||||
<TD>pacommandnames_run_synthesis=6</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>pacommandnames_set_as_top=2</TD>
|
||||
<TD>partchooser_family_chooser=1</TD>
|
||||
<TD>partchooser_parts=2</TD>
|
||||
<TD>paviews_code=8</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>paviews_device=2</TD>
|
||||
<TD>programfpgadialog_program=1</TD>
|
||||
<TD>progressdialog_background=1</TD>
|
||||
<TD>projectnamechooser_choose_project_location=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>projectnamechooser_project_name=2</TD>
|
||||
<TD>projectsummarytimingpanel_project_summary_timing_panel_tabbed=11</TD>
|
||||
<TD>projectsummaryutilizationgadget_project_summary_utilization_gadget_tabbed=1</TD>
|
||||
<TD>projectsummaryutilizationpanel_project_summary_utilization_panel_tabbed=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>rdicommands_delete=4</TD>
|
||||
<TD>rungadget_run_gadget_tabbed_pane=1</TD>
|
||||
<TD>rungadget_show_error=2</TD>
|
||||
<TD>saveprojectutils_cancel=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>saveprojectutils_save=2</TD>
|
||||
<TD>srcchooserpanel_add_hdl_and_netlist_files_to_your_project=3</TD>
|
||||
<TD>srcchooserpanel_create_file=1</TD>
|
||||
<TD>srcmenu_ip_hierarchy=11</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>srcmenu_refresh_hierarchy=1</TD>
|
||||
<TD>stalerundialog_yes=1</TD>
|
||||
<TD>syntheticagettingstartedview_recent_projects=2</TD>
|
||||
<TD>syntheticastatemonitor_cancel=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>taskbanner_close=1</TD>
|
||||
<TD>touchpointsurveydialog_no=1</TD>
|
||||
</TR> </TABLE>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>addsources=6</TD>
|
||||
<TD>autoconnecttarget=2</TD>
|
||||
<TD>coreview=1</TD>
|
||||
<TD>customizecore=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>editdelete=4</TD>
|
||||
<TD>launchprogramfpga=2</TD>
|
||||
<TD>newproject=1</TD>
|
||||
<TD>openhardwaremanager=6</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>openrecenttarget=2</TD>
|
||||
<TD>programdevice=2</TD>
|
||||
<TD>reportutilization=1</TD>
|
||||
<TD>runbitgen=8</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>runimplementation=3</TD>
|
||||
<TD>runsynthesis=6</TD>
|
||||
<TD>savefileproxyhandler=1</TD>
|
||||
<TD>settopnode=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>showview=7</TD>
|
||||
<TD>updateregid=1</TD>
|
||||
<TD>viewtasksynthesis=1</TD>
|
||||
</TR> </TABLE>
|
||||
</TR><TR ALIGN='LEFT'> <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>guimode=4</TD>
|
||||
</TR> </TABLE>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>constraintsetcount=1</TD>
|
||||
<TD>core_container=false</TD>
|
||||
<TD>currentimplrun=impl_1</TD>
|
||||
<TD>currentsynthesisrun=synth_1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>default_library=xil_defaultlib</TD>
|
||||
<TD>designmode=RTL</TD>
|
||||
<TD>export_simulation_activehdl=0</TD>
|
||||
<TD>export_simulation_ies=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>export_simulation_modelsim=0</TD>
|
||||
<TD>export_simulation_questa=0</TD>
|
||||
<TD>export_simulation_riviera=0</TD>
|
||||
<TD>export_simulation_vcs=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>export_simulation_xsim=0</TD>
|
||||
<TD>implstrategy=Vivado Implementation Defaults</TD>
|
||||
<TD>launch_simulation_activehdl=0</TD>
|
||||
<TD>launch_simulation_ies=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>launch_simulation_modelsim=0</TD>
|
||||
<TD>launch_simulation_questa=0</TD>
|
||||
<TD>launch_simulation_riviera=0</TD>
|
||||
<TD>launch_simulation_vcs=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>launch_simulation_xsim=0</TD>
|
||||
<TD>simulator_language=Mixed</TD>
|
||||
<TD>srcsetcount=18</TD>
|
||||
<TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>target_language=Verilog</TD>
|
||||
<TD>target_simulator=XSim</TD>
|
||||
<TD>totalimplruns=1</TD>
|
||||
<TD>totalsynthesisruns=1</TD>
|
||||
</TR> </TABLE>
|
||||
</TR> </TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>bufg=3</TD>
|
||||
<TD>carry4=128</TD>
|
||||
<TD>fdce=1563</TD>
|
||||
<TD>fdpe=7</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>fdre=581</TD>
|
||||
<TD>fdse=26</TD>
|
||||
<TD>gnd=23</TD>
|
||||
<TD>ibuf=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut1=45</TD>
|
||||
<TD>lut2=296</TD>
|
||||
<TD>lut3=211</TD>
|
||||
<TD>lut4=768</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut5=1121</TD>
|
||||
<TD>lut6=2937</TD>
|
||||
<TD>muxf7=170</TD>
|
||||
<TD>muxf8=6</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>obuf=25</TD>
|
||||
<TD>obuft=6</TD>
|
||||
<TD>ramb18e1=13</TD>
|
||||
<TD>srl16e=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vcc=28</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>bufg=3</TD>
|
||||
<TD>carry4=128</TD>
|
||||
<TD>fdce=1563</TD>
|
||||
<TD>fdpe=7</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>fdre=581</TD>
|
||||
<TD>fdse=26</TD>
|
||||
<TD>gnd=23</TD>
|
||||
<TD>ibuf=2</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut1=45</TD>
|
||||
<TD>lut2=296</TD>
|
||||
<TD>lut3=211</TD>
|
||||
<TD>lut4=768</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut5=1121</TD>
|
||||
<TD>lut6=2937</TD>
|
||||
<TD>muxf7=170</TD>
|
||||
<TD>muxf8=6</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>obuf=25</TD>
|
||||
<TD>obuft=6</TD>
|
||||
<TD>ramb18e1=13</TD>
|
||||
<TD>srl16e=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vcc=28</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
</TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>power_opt_design</B></TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options_spo</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>-cell_types=default::all</TD>
|
||||
<TD>-clocks=default::[not_specified]</TD>
|
||||
<TD>-exclude_cells=default::[not_specified]</TD>
|
||||
<TD>-include_cells=default::[not_specified]</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>bram_ports_augmented=0</TD>
|
||||
<TD>bram_ports_newly_gated=5</TD>
|
||||
<TD>bram_ports_total=26</TD>
|
||||
<TD>flow_state=default</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>slice_registers_augmented=0</TD>
|
||||
<TD>slice_registers_newly_gated=0</TD>
|
||||
<TD>slice_registers_total=2195</TD>
|
||||
<TD>srls_augmented=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>srls_newly_gated=0</TD>
|
||||
<TD>srls_total=1</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
</TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>-append=default::[not_specified]</TD>
|
||||
<TD>-checks=default::[not_specified]</TD>
|
||||
<TD>-fail_on=default::[not_specified]</TD>
|
||||
<TD>-force=default::[not_specified]</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-format=default::[not_specified]</TD>
|
||||
<TD>-messages=default::[not_specified]</TD>
|
||||
<TD>-name=default::[not_specified]</TD>
|
||||
<TD>-return_string=default::[not_specified]</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-ruledecks=default::[not_specified]</TD>
|
||||
<TD>-upgrade_cw=default::[not_specified]</TD>
|
||||
<TD>-waived=default::[not_specified]</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>cfgbvs-1=1</TD>
|
||||
<TD>check-3=1</TD>
|
||||
<TD>reqp-1840=20</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
</TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_methodology</B></TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>-append=default::[not_specified]</TD>
|
||||
<TD>-checks=default::[not_specified]</TD>
|
||||
<TD>-fail_on=default::[not_specified]</TD>
|
||||
<TD>-force=default::[not_specified]</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-format=default::[not_specified]</TD>
|
||||
<TD>-messages=default::[not_specified]</TD>
|
||||
<TD>-name=default::[not_specified]</TD>
|
||||
<TD>-return_string=default::[not_specified]</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-waived=default::[not_specified]</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>timing-17=1000</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
</TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_power</B></TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>-advisory=default::[not_specified]</TD>
|
||||
<TD>-append=default::[not_specified]</TD>
|
||||
<TD>-file=[specified]</TD>
|
||||
<TD>-format=default::text</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-hier=default::power</TD>
|
||||
<TD>-l=default::[not_specified]</TD>
|
||||
<TD>-name=default::[not_specified]</TD>
|
||||
<TD>-no_propagation=default::[not_specified]</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-return_string=default::[not_specified]</TD>
|
||||
<TD>-rpx=[specified]</TD>
|
||||
<TD>-verbose=default::[not_specified]</TD>
|
||||
<TD>-vid=default::[not_specified]</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-xpe=default::[not_specified]</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>airflow=250 (LFM)</TD>
|
||||
<TD>ambient_temp=25.0 (C)</TD>
|
||||
<TD>bi-dir_toggle=12.500000</TD>
|
||||
<TD>bidir_output_enable=1.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>board_layers=12to15 (12 to 15 Layers)</TD>
|
||||
<TD>board_selection=medium (10"x10")</TD>
|
||||
<TD>bram=0.005690</TD>
|
||||
<TD>clocks=0.000476</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>confidence_level_clock_activity=Low</TD>
|
||||
<TD>confidence_level_design_state=High</TD>
|
||||
<TD>confidence_level_device_models=High</TD>
|
||||
<TD>confidence_level_internal_activity=Medium</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>confidence_level_io_activity=Medium</TD>
|
||||
<TD>confidence_level_overall=Low</TD>
|
||||
<TD>customer=TBD</TD>
|
||||
<TD>customer_class=TBD</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>devstatic=0.097565</TD>
|
||||
<TD>die=xc7a100tcsg324-1</TD>
|
||||
<TD>dsp_output_toggle=12.500000</TD>
|
||||
<TD>dynamic=0.017636</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>effective_thetaja=4.6</TD>
|
||||
<TD>enable_probability=0.990000</TD>
|
||||
<TD>family=artix7</TD>
|
||||
<TD>ff_toggle=12.500000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>flow_state=routed</TD>
|
||||
<TD>heatsink=medium (Medium Profile)</TD>
|
||||
<TD>i/o=0.002276</TD>
|
||||
<TD>input_toggle=12.500000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>junction_temp=25.5 (C)</TD>
|
||||
<TD>logic=0.003857</TD>
|
||||
<TD>mgtavcc_dynamic_current=0.000000</TD>
|
||||
<TD>mgtavcc_static_current=0.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>mgtavcc_total_current=0.000000</TD>
|
||||
<TD>mgtavcc_voltage=1.000000</TD>
|
||||
<TD>mgtavtt_dynamic_current=0.000000</TD>
|
||||
<TD>mgtavtt_static_current=0.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>mgtavtt_total_current=0.000000</TD>
|
||||
<TD>mgtavtt_voltage=1.200000</TD>
|
||||
<TD>netlist_net_matched=NA</TD>
|
||||
<TD>off-chip_power=0.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>on-chip_power=0.115201</TD>
|
||||
<TD>output_enable=1.000000</TD>
|
||||
<TD>output_load=5.000000</TD>
|
||||
<TD>output_toggle=12.500000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>package=csg324</TD>
|
||||
<TD>pct_clock_constrained=4.000000</TD>
|
||||
<TD>pct_inputs_defined=50</TD>
|
||||
<TD>platform=nt64</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>process=typical</TD>
|
||||
<TD>ram_enable=50.000000</TD>
|
||||
<TD>ram_write=50.000000</TD>
|
||||
<TD>read_saif=False</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>set/reset_probability=0.000000</TD>
|
||||
<TD>signal_rate=False</TD>
|
||||
<TD>signals=0.005339</TD>
|
||||
<TD>simulation_file=None</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>speedgrade=-1</TD>
|
||||
<TD>static_prob=False</TD>
|
||||
<TD>temp_grade=commercial</TD>
|
||||
<TD>thetajb=5.7 (C/W)</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>thetasa=4.6 (C/W)</TD>
|
||||
<TD>toggle_rate=False</TD>
|
||||
<TD>user_board_temp=25.0 (C)</TD>
|
||||
<TD>user_effective_thetaja=4.6</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>user_junc_temp=25.5 (C)</TD>
|
||||
<TD>user_thetajb=5.7 (C/W)</TD>
|
||||
<TD>user_thetasa=4.6 (C/W)</TD>
|
||||
<TD>vccadc_dynamic_current=0.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vccadc_static_current=0.020000</TD>
|
||||
<TD>vccadc_total_current=0.020000</TD>
|
||||
<TD>vccadc_voltage=1.800000</TD>
|
||||
<TD>vccaux_dynamic_current=0.000081</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vccaux_io_dynamic_current=0.000000</TD>
|
||||
<TD>vccaux_io_static_current=0.000000</TD>
|
||||
<TD>vccaux_io_total_current=0.000000</TD>
|
||||
<TD>vccaux_io_voltage=1.800000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vccaux_static_current=0.018143</TD>
|
||||
<TD>vccaux_total_current=0.018224</TD>
|
||||
<TD>vccaux_voltage=1.800000</TD>
|
||||
<TD>vccbram_dynamic_current=0.000500</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vccbram_static_current=0.000398</TD>
|
||||
<TD>vccbram_total_current=0.000897</TD>
|
||||
<TD>vccbram_voltage=1.000000</TD>
|
||||
<TD>vccint_dynamic_current=0.014929</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vccint_static_current=0.015310</TD>
|
||||
<TD>vccint_total_current=0.030239</TD>
|
||||
<TD>vccint_voltage=1.000000</TD>
|
||||
<TD>vcco12_dynamic_current=0.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vcco12_static_current=0.000000</TD>
|
||||
<TD>vcco12_total_current=0.000000</TD>
|
||||
<TD>vcco12_voltage=1.200000</TD>
|
||||
<TD>vcco135_dynamic_current=0.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vcco135_static_current=0.000000</TD>
|
||||
<TD>vcco135_total_current=0.000000</TD>
|
||||
<TD>vcco135_voltage=1.350000</TD>
|
||||
<TD>vcco15_dynamic_current=0.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vcco15_static_current=0.000000</TD>
|
||||
<TD>vcco15_total_current=0.000000</TD>
|
||||
<TD>vcco15_voltage=1.500000</TD>
|
||||
<TD>vcco18_dynamic_current=0.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vcco18_static_current=0.000000</TD>
|
||||
<TD>vcco18_total_current=0.000000</TD>
|
||||
<TD>vcco18_voltage=1.800000</TD>
|
||||
<TD>vcco25_dynamic_current=0.000000</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vcco25_static_current=0.000000</TD>
|
||||
<TD>vcco25_total_current=0.000000</TD>
|
||||
<TD>vcco25_voltage=2.500000</TD>
|
||||
<TD>vcco33_dynamic_current=0.000625</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>vcco33_static_current=0.004000</TD>
|
||||
<TD>vcco33_total_current=0.004625</TD>
|
||||
<TD>vcco33_voltage=3.300000</TD>
|
||||
<TD>version=2017.4</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
</TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>bufgctrl_available=32</TD>
|
||||
<TD>bufgctrl_fixed=0</TD>
|
||||
<TD>bufgctrl_used=3</TD>
|
||||
<TD>bufgctrl_util_percentage=9.38</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>bufhce_available=96</TD>
|
||||
<TD>bufhce_fixed=0</TD>
|
||||
<TD>bufhce_used=0</TD>
|
||||
<TD>bufhce_util_percentage=0.00</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>bufio_available=24</TD>
|
||||
<TD>bufio_fixed=0</TD>
|
||||
<TD>bufio_used=0</TD>
|
||||
<TD>bufio_util_percentage=0.00</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>bufmrce_available=12</TD>
|
||||
<TD>bufmrce_fixed=0</TD>
|
||||
<TD>bufmrce_used=0</TD>
|
||||
<TD>bufmrce_util_percentage=0.00</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>bufr_available=24</TD>
|
||||
<TD>bufr_fixed=0</TD>
|
||||
<TD>bufr_used=0</TD>
|
||||
<TD>bufr_util_percentage=0.00</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>mmcme2_adv_available=6</TD>
|
||||
<TD>mmcme2_adv_fixed=0</TD>
|
||||
<TD>mmcme2_adv_used=0</TD>
|
||||
<TD>mmcme2_adv_util_percentage=0.00</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>plle2_adv_available=6</TD>
|
||||
<TD>plle2_adv_fixed=0</TD>
|
||||
<TD>plle2_adv_used=0</TD>
|
||||
<TD>plle2_adv_util_percentage=0.00</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>dsps_available=240</TD>
|
||||
<TD>dsps_fixed=0</TD>
|
||||
<TD>dsps_used=0</TD>
|
||||
<TD>dsps_util_percentage=0.00</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>blvds_25=0</TD>
|
||||
<TD>diff_hstl_i=0</TD>
|
||||
<TD>diff_hstl_i_18=0</TD>
|
||||
<TD>diff_hstl_ii=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>diff_hstl_ii_18=0</TD>
|
||||
<TD>diff_hsul_12=0</TD>
|
||||
<TD>diff_mobile_ddr=0</TD>
|
||||
<TD>diff_sstl135=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>diff_sstl135_r=0</TD>
|
||||
<TD>diff_sstl15=0</TD>
|
||||
<TD>diff_sstl15_r=0</TD>
|
||||
<TD>diff_sstl18_i=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>diff_sstl18_ii=0</TD>
|
||||
<TD>hstl_i=0</TD>
|
||||
<TD>hstl_i_18=0</TD>
|
||||
<TD>hstl_ii=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>hstl_ii_18=0</TD>
|
||||
<TD>hsul_12=0</TD>
|
||||
<TD>lvcmos12=0</TD>
|
||||
<TD>lvcmos15=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lvcmos18=1</TD>
|
||||
<TD>lvcmos25=0</TD>
|
||||
<TD>lvcmos33=1</TD>
|
||||
<TD>lvds_25=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lvttl=0</TD>
|
||||
<TD>mini_lvds_25=0</TD>
|
||||
<TD>mobile_ddr=0</TD>
|
||||
<TD>pci33_3=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>ppds_25=0</TD>
|
||||
<TD>rsds_25=0</TD>
|
||||
<TD>sstl135=0</TD>
|
||||
<TD>sstl135_r=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>sstl15=0</TD>
|
||||
<TD>sstl15_r=0</TD>
|
||||
<TD>sstl18_i=0</TD>
|
||||
<TD>sstl18_ii=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>tmds_33=0</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>block_ram_tile_available=135</TD>
|
||||
<TD>block_ram_tile_fixed=0</TD>
|
||||
<TD>block_ram_tile_used=6.5</TD>
|
||||
<TD>block_ram_tile_util_percentage=4.81</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>ramb18_available=270</TD>
|
||||
<TD>ramb18_fixed=0</TD>
|
||||
<TD>ramb18_used=13</TD>
|
||||
<TD>ramb18_util_percentage=4.81</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>ramb18e1_only_used=13</TD>
|
||||
<TD>ramb36_fifo_available=135</TD>
|
||||
<TD>ramb36_fifo_fixed=0</TD>
|
||||
<TD>ramb36_fifo_used=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>ramb36_fifo_util_percentage=0.00</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>bufg_functional_category=Clock</TD>
|
||||
<TD>bufg_used=3</TD>
|
||||
<TD>carry4_functional_category=CarryLogic</TD>
|
||||
<TD>carry4_used=128</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>fdce_functional_category=Flop & Latch</TD>
|
||||
<TD>fdce_used=1571</TD>
|
||||
<TD>fdpe_functional_category=Flop & Latch</TD>
|
||||
<TD>fdpe_used=7</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>fdre_functional_category=Flop & Latch</TD>
|
||||
<TD>fdre_used=591</TD>
|
||||
<TD>fdse_functional_category=Flop & Latch</TD>
|
||||
<TD>fdse_used=26</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>ibuf_functional_category=IO</TD>
|
||||
<TD>ibuf_used=2</TD>
|
||||
<TD>lut1_functional_category=LUT</TD>
|
||||
<TD>lut1_used=42</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut2_functional_category=LUT</TD>
|
||||
<TD>lut2_used=296</TD>
|
||||
<TD>lut3_functional_category=LUT</TD>
|
||||
<TD>lut3_used=216</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut4_functional_category=LUT</TD>
|
||||
<TD>lut4_used=768</TD>
|
||||
<TD>lut5_functional_category=LUT</TD>
|
||||
<TD>lut5_used=1121</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut6_functional_category=LUT</TD>
|
||||
<TD>lut6_used=2937</TD>
|
||||
<TD>muxf7_functional_category=MuxFx</TD>
|
||||
<TD>muxf7_used=170</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>muxf8_functional_category=MuxFx</TD>
|
||||
<TD>muxf8_used=6</TD>
|
||||
<TD>obuf_functional_category=IO</TD>
|
||||
<TD>obuf_used=25</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>obuft_functional_category=IO</TD>
|
||||
<TD>obuft_used=6</TD>
|
||||
<TD>ramb18e1_functional_category=Block Memory</TD>
|
||||
<TD>ramb18e1_used=13</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>srl16e_functional_category=Distributed Memory</TD>
|
||||
<TD>srl16e_used=1</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>f7_muxes_available=31700</TD>
|
||||
<TD>f7_muxes_fixed=0</TD>
|
||||
<TD>f7_muxes_used=170</TD>
|
||||
<TD>f7_muxes_util_percentage=0.54</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>f8_muxes_available=15850</TD>
|
||||
<TD>f8_muxes_fixed=0</TD>
|
||||
<TD>f8_muxes_used=6</TD>
|
||||
<TD>f8_muxes_util_percentage=0.04</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut_as_distributed_ram_fixed=0</TD>
|
||||
<TD>lut_as_distributed_ram_used=0</TD>
|
||||
<TD>lut_as_logic_available=63400</TD>
|
||||
<TD>lut_as_logic_fixed=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_used=4863</TD>
|
||||
<TD>lut_as_logic_util_percentage=7.67</TD>
|
||||
<TD>lut_as_memory_available=19000</TD>
|
||||
<TD>lut_as_memory_fixed=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_used=1</TD>
|
||||
<TD>lut_as_memory_util_percentage=<0.01</TD>
|
||||
<TD>lut_as_shift_register_fixed=0</TD>
|
||||
<TD>lut_as_shift_register_used=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>register_as_flip_flop_available=126800</TD>
|
||||
<TD>register_as_flip_flop_fixed=0</TD>
|
||||
<TD>register_as_flip_flop_used=2195</TD>
|
||||
<TD>register_as_flip_flop_util_percentage=1.73</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>register_as_latch_available=126800</TD>
|
||||
<TD>register_as_latch_fixed=0</TD>
|
||||
<TD>register_as_latch_used=0</TD>
|
||||
<TD>register_as_latch_util_percentage=0.00</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>slice_luts_available=63400</TD>
|
||||
<TD>slice_luts_fixed=0</TD>
|
||||
<TD>slice_luts_used=4864</TD>
|
||||
<TD>slice_luts_util_percentage=7.67</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>slice_registers_available=126800</TD>
|
||||
<TD>slice_registers_fixed=0</TD>
|
||||
<TD>slice_registers_used=2195</TD>
|
||||
<TD>slice_registers_util_percentage=1.73</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>fully_used_lut_ff_pairs_fixed=1.73</TD>
|
||||
<TD>fully_used_lut_ff_pairs_used=49</TD>
|
||||
<TD>lut_as_distributed_ram_fixed=0</TD>
|
||||
<TD>lut_as_distributed_ram_used=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_available=63400</TD>
|
||||
<TD>lut_as_logic_fixed=0</TD>
|
||||
<TD>lut_as_logic_used=4863</TD>
|
||||
<TD>lut_as_logic_util_percentage=7.67</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_available=19000</TD>
|
||||
<TD>lut_as_memory_fixed=0</TD>
|
||||
<TD>lut_as_memory_used=1</TD>
|
||||
<TD>lut_as_memory_util_percentage=<0.01</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut_as_shift_register_fixed=0</TD>
|
||||
<TD>lut_as_shift_register_used=1</TD>
|
||||
<TD>lut_ff_pairs_with_one_unused_flip_flop_fixed=1</TD>
|
||||
<TD>lut_ff_pairs_with_one_unused_flip_flop_used=1546</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut_ff_pairs_with_one_unused_lut_output_fixed=1546</TD>
|
||||
<TD>lut_ff_pairs_with_one_unused_lut_output_used=1531</TD>
|
||||
<TD>lut_flip_flop_pairs_available=63400</TD>
|
||||
<TD>lut_flip_flop_pairs_fixed=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>lut_flip_flop_pairs_used=1620</TD>
|
||||
<TD>lut_flip_flop_pairs_util_percentage=2.56</TD>
|
||||
<TD>slice_available=15850</TD>
|
||||
<TD>slice_fixed=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>slice_used=1626</TD>
|
||||
<TD>slice_util_percentage=10.26</TD>
|
||||
<TD>slicel_fixed=0</TD>
|
||||
<TD>slicel_used=1112</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>slicem_fixed=0</TD>
|
||||
<TD>slicem_used=514</TD>
|
||||
<TD>unique_control_sets_used=286</TD>
|
||||
<TD>using_o5_and_o6_fixed=286</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>using_o5_and_o6_used=0</TD>
|
||||
<TD>using_o5_output_only_fixed=0</TD>
|
||||
<TD>using_o5_output_only_used=1</TD>
|
||||
<TD>using_o6_output_only_fixed=1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>using_o6_output_only_used=0</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>bscane2_available=4</TD>
|
||||
<TD>bscane2_fixed=0</TD>
|
||||
<TD>bscane2_used=0</TD>
|
||||
<TD>bscane2_util_percentage=0.00</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>capturee2_available=1</TD>
|
||||
<TD>capturee2_fixed=0</TD>
|
||||
<TD>capturee2_used=0</TD>
|
||||
<TD>capturee2_util_percentage=0.00</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>dna_port_available=1</TD>
|
||||
<TD>dna_port_fixed=0</TD>
|
||||
<TD>dna_port_used=0</TD>
|
||||
<TD>dna_port_util_percentage=0.00</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>efuse_usr_available=1</TD>
|
||||
<TD>efuse_usr_fixed=0</TD>
|
||||
<TD>efuse_usr_used=0</TD>
|
||||
<TD>efuse_usr_util_percentage=0.00</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>frame_ecce2_available=1</TD>
|
||||
<TD>frame_ecce2_fixed=0</TD>
|
||||
<TD>frame_ecce2_used=0</TD>
|
||||
<TD>frame_ecce2_util_percentage=0.00</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>icape2_available=2</TD>
|
||||
<TD>icape2_fixed=0</TD>
|
||||
<TD>icape2_used=0</TD>
|
||||
<TD>icape2_util_percentage=0.00</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>pcie_2_1_available=1</TD>
|
||||
<TD>pcie_2_1_fixed=0</TD>
|
||||
<TD>pcie_2_1_used=0</TD>
|
||||
<TD>pcie_2_1_util_percentage=0.00</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>startupe2_available=1</TD>
|
||||
<TD>startupe2_fixed=0</TD>
|
||||
<TD>startupe2_used=0</TD>
|
||||
<TD>startupe2_util_percentage=0.00</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>xadc_available=1</TD>
|
||||
<TD>xadc_fixed=0</TD>
|
||||
<TD>xadc_used=0</TD>
|
||||
<TD>xadc_util_percentage=0.00</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
</TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>router</B></TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>actual_expansions=4982709</TD>
|
||||
<TD>bogomips=0</TD>
|
||||
<TD>bram18=13</TD>
|
||||
<TD>bram36=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>bufg=0</TD>
|
||||
<TD>bufr=0</TD>
|
||||
<TD>congestion_level=0</TD>
|
||||
<TD>ctrls=286</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>dsp=0</TD>
|
||||
<TD>effort=2</TD>
|
||||
<TD>estimated_expansions=6968538</TD>
|
||||
<TD>ff=2195</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>global_clocks=3</TD>
|
||||
<TD>high_fanout_nets=1</TD>
|
||||
<TD>iob=33</TD>
|
||||
<TD>lut=5187</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>movable_instances=7980</TD>
|
||||
<TD>nets=8403</TD>
|
||||
<TD>pins=48589</TD>
|
||||
<TD>pll=0</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>router_runtime=0.000000</TD>
|
||||
<TD>router_timing_driven=1</TD>
|
||||
<TD>threads=2</TD>
|
||||
<TD>timing_constraints_exist=1</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
</TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>-assert=default::[not_specified]</TD>
|
||||
<TD>-bufg=default::12</TD>
|
||||
<TD>-cascade_dsp=default::auto</TD>
|
||||
<TD>-constrset=default::[not_specified]</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-control_set_opt_threshold=default::auto</TD>
|
||||
<TD>-directive=default::default</TD>
|
||||
<TD>-fanout_limit=default::10000</TD>
|
||||
<TD>-flatten_hierarchy=default::rebuilt</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-fsm_extraction=default::auto</TD>
|
||||
<TD>-gated_clock_conversion=default::off</TD>
|
||||
<TD>-generic=default::[not_specified]</TD>
|
||||
<TD>-include_dirs=default::[not_specified]</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-keep_equivalent_registers=default::[not_specified]</TD>
|
||||
<TD>-max_bram=default::-1</TD>
|
||||
<TD>-max_bram_cascade_height=default::-1</TD>
|
||||
<TD>-max_dsp=default::-1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-max_uram=default::-1</TD>
|
||||
<TD>-max_uram_cascade_height=default::-1</TD>
|
||||
<TD>-mode=default::default</TD>
|
||||
<TD>-name=default::[not_specified]</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-no_lc=default::[not_specified]</TD>
|
||||
<TD>-no_srlextract=default::[not_specified]</TD>
|
||||
<TD>-no_timing_driven=default::[not_specified]</TD>
|
||||
<TD>-part=xc7a100tcsg324-1</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-resource_sharing=default::auto</TD>
|
||||
<TD>-retiming=default::[not_specified]</TD>
|
||||
<TD>-rtl=default::[not_specified]</TD>
|
||||
<TD>-rtl_skip_constraints=default::[not_specified]</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-rtl_skip_ip=default::[not_specified]</TD>
|
||||
<TD>-seu_protect=default::none</TD>
|
||||
<TD>-sfcu=default::[not_specified]</TD>
|
||||
<TD>-shreg_min_size=default::3</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>-top=Nexys4_USTCRVSoC_top</TD>
|
||||
<TD>-verilog_define=default::[not_specified]</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>elapsed=00:01:32s</TD>
|
||||
<TD>hls_ip=0</TD>
|
||||
<TD>memory_gain=876.070MB</TD>
|
||||
<TD>memory_peak=1165.590MB</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
</TABLE><BR>
|
||||
</BODY>
|
||||
</HTML>
|
||||
@ -1,702 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<webTalkData fileName='usage_statistics_webtalk.xml' majorVersion='1' minorVersion='0' timeStamp='Tue Feb 26 19:22:38 2019'>
|
||||
<section name="__ROOT__" level="0" order="1" description="">
|
||||
<section name="software_version_and_target_device" level="1" order="1" description="">
|
||||
<keyValuePair key="beta" value="FALSE" description="" />
|
||||
<keyValuePair key="build_version" value="2086221" description="" />
|
||||
<keyValuePair key="date_generated" value="Tue Feb 26 19:22:38 2019" description="" />
|
||||
<keyValuePair key="os_platform" value="WIN64" description="" />
|
||||
<keyValuePair key="product_version" value="Vivado v2017.4 (64-bit)" description="" />
|
||||
<keyValuePair key="project_id" value="ddc8340f1eba4b8bbb076a11b9b82028" description="" />
|
||||
<keyValuePair key="project_iteration" value="4" description="" />
|
||||
<keyValuePair key="random_id" value="e0d099809a2653d599a90285146ff6f4" description="" />
|
||||
<keyValuePair key="registration_id" value="e0d099809a2653d599a90285146ff6f4" description="" />
|
||||
<keyValuePair key="route_design" value="TRUE" description="" />
|
||||
<keyValuePair key="target_device" value="xc7a100t" description="" />
|
||||
<keyValuePair key="target_family" value="artix7" description="" />
|
||||
<keyValuePair key="target_package" value="csg324" description="" />
|
||||
<keyValuePair key="target_speed" value="-1" description="" />
|
||||
<keyValuePair key="tool_flow" value="Vivado" description="" />
|
||||
</section>
|
||||
<section name="user_environment" level="1" order="2" description="">
|
||||
<keyValuePair key="cpu_name" value="Intel(R) Core(TM) i7-8750H CPU @ 2.20GHz" description="" />
|
||||
<keyValuePair key="cpu_speed" value="2208 MHz" description="" />
|
||||
<keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
|
||||
<keyValuePair key="os_release" value="major release (build 9200)" description="" />
|
||||
<keyValuePair key="system_ram" value="25.000 GB" description="" />
|
||||
<keyValuePair key="total_processors" value="1" description="" />
|
||||
</section>
|
||||
<section name="power_opt_design" level="1" order="3" description="">
|
||||
<section name="command_line_options_spo" level="2" order="1" description="">
|
||||
<keyValuePair key="-cell_types" value="default::all" description="" />
|
||||
<keyValuePair key="-clocks" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-exclude_cells" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-include_cells" value="default::[not_specified]" description="" />
|
||||
</section>
|
||||
<section name="usage" level="2" order="2" description="">
|
||||
<keyValuePair key="bram_ports_augmented" value="0" description="" />
|
||||
<keyValuePair key="bram_ports_newly_gated" value="5" description="" />
|
||||
<keyValuePair key="bram_ports_total" value="26" description="" />
|
||||
<keyValuePair key="flow_state" value="default" description="" />
|
||||
<keyValuePair key="slice_registers_augmented" value="0" description="" />
|
||||
<keyValuePair key="slice_registers_newly_gated" value="0" description="" />
|
||||
<keyValuePair key="slice_registers_total" value="2195" description="" />
|
||||
<keyValuePair key="srls_augmented" value="0" description="" />
|
||||
<keyValuePair key="srls_newly_gated" value="0" description="" />
|
||||
<keyValuePair key="srls_total" value="1" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="report_drc" level="1" order="4" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="-append" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-checks" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-fail_on" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-force" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-format" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-messages" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-name" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-return_string" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-ruledecks" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-upgrade_cw" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-waived" value="default::[not_specified]" description="" />
|
||||
</section>
|
||||
<section name="results" level="2" order="2" description="">
|
||||
<keyValuePair key="cfgbvs-1" value="1" description="" />
|
||||
<keyValuePair key="check-3" value="1" description="" />
|
||||
<keyValuePair key="reqp-1840" value="20" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="report_methodology" level="1" order="5" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="-append" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-checks" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-fail_on" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-force" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-format" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-messages" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-name" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-return_string" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-waived" value="default::[not_specified]" description="" />
|
||||
</section>
|
||||
<section name="results" level="2" order="2" description="">
|
||||
<keyValuePair key="timing-17" value="1000" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="report_power" level="1" order="6" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="-advisory" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-append" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-file" value="[specified]" description="" />
|
||||
<keyValuePair key="-format" value="default::text" description="" />
|
||||
<keyValuePair key="-hier" value="default::power" description="" />
|
||||
<keyValuePair key="-l" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-name" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-no_propagation" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-return_string" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-rpx" value="[specified]" description="" />
|
||||
<keyValuePair key="-verbose" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-vid" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-xpe" value="default::[not_specified]" description="" />
|
||||
</section>
|
||||
<section name="usage" level="2" order="2" description="">
|
||||
<keyValuePair key="airflow" value="250 (LFM)" description="" />
|
||||
<keyValuePair key="ambient_temp" value="25.0 (C)" description="" />
|
||||
<keyValuePair key="bi-dir_toggle" value="12.500000" description="" />
|
||||
<keyValuePair key="bidir_output_enable" value="1.000000" description="" />
|
||||
<keyValuePair key="board_layers" value="12to15 (12 to 15 Layers)" description="" />
|
||||
<keyValuePair key="board_selection" value="medium (10"x10")" description="" />
|
||||
<keyValuePair key="bram" value="0.005690" description="" />
|
||||
<keyValuePair key="clocks" value="0.000476" description="" />
|
||||
<keyValuePair key="confidence_level_clock_activity" value="Low" description="" />
|
||||
<keyValuePair key="confidence_level_design_state" value="High" description="" />
|
||||
<keyValuePair key="confidence_level_device_models" value="High" description="" />
|
||||
<keyValuePair key="confidence_level_internal_activity" value="Medium" description="" />
|
||||
<keyValuePair key="confidence_level_io_activity" value="Medium" description="" />
|
||||
<keyValuePair key="confidence_level_overall" value="Low" description="" />
|
||||
<keyValuePair key="customer" value="TBD" description="" />
|
||||
<keyValuePair key="customer_class" value="TBD" description="" />
|
||||
<keyValuePair key="devstatic" value="0.097565" description="" />
|
||||
<keyValuePair key="die" value="xc7a100tcsg324-1" description="" />
|
||||
<keyValuePair key="dsp_output_toggle" value="12.500000" description="" />
|
||||
<keyValuePair key="dynamic" value="0.017636" description="" />
|
||||
<keyValuePair key="effective_thetaja" value="4.6" description="" />
|
||||
<keyValuePair key="enable_probability" value="0.990000" description="" />
|
||||
<keyValuePair key="family" value="artix7" description="" />
|
||||
<keyValuePair key="ff_toggle" value="12.500000" description="" />
|
||||
<keyValuePair key="flow_state" value="routed" description="" />
|
||||
<keyValuePair key="heatsink" value="medium (Medium Profile)" description="" />
|
||||
<keyValuePair key="i/o" value="0.002276" description="" />
|
||||
<keyValuePair key="input_toggle" value="12.500000" description="" />
|
||||
<keyValuePair key="junction_temp" value="25.5 (C)" description="" />
|
||||
<keyValuePair key="logic" value="0.003857" description="" />
|
||||
<keyValuePair key="mgtavcc_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="mgtavcc_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="mgtavcc_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="mgtavcc_voltage" value="1.000000" description="" />
|
||||
<keyValuePair key="mgtavtt_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="mgtavtt_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="mgtavtt_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="mgtavtt_voltage" value="1.200000" description="" />
|
||||
<keyValuePair key="netlist_net_matched" value="NA" description="" />
|
||||
<keyValuePair key="off-chip_power" value="0.000000" description="" />
|
||||
<keyValuePair key="on-chip_power" value="0.115201" description="" />
|
||||
<keyValuePair key="output_enable" value="1.000000" description="" />
|
||||
<keyValuePair key="output_load" value="5.000000" description="" />
|
||||
<keyValuePair key="output_toggle" value="12.500000" description="" />
|
||||
<keyValuePair key="package" value="csg324" description="" />
|
||||
<keyValuePair key="pct_clock_constrained" value="4.000000" description="" />
|
||||
<keyValuePair key="pct_inputs_defined" value="50" description="" />
|
||||
<keyValuePair key="platform" value="nt64" description="" />
|
||||
<keyValuePair key="process" value="typical" description="" />
|
||||
<keyValuePair key="ram_enable" value="50.000000" description="" />
|
||||
<keyValuePair key="ram_write" value="50.000000" description="" />
|
||||
<keyValuePair key="read_saif" value="False" description="" />
|
||||
<keyValuePair key="set/reset_probability" value="0.000000" description="" />
|
||||
<keyValuePair key="signal_rate" value="False" description="" />
|
||||
<keyValuePair key="signals" value="0.005339" description="" />
|
||||
<keyValuePair key="simulation_file" value="None" description="" />
|
||||
<keyValuePair key="speedgrade" value="-1" description="" />
|
||||
<keyValuePair key="static_prob" value="False" description="" />
|
||||
<keyValuePair key="temp_grade" value="commercial" description="" />
|
||||
<keyValuePair key="thetajb" value="5.7 (C/W)" description="" />
|
||||
<keyValuePair key="thetasa" value="4.6 (C/W)" description="" />
|
||||
<keyValuePair key="toggle_rate" value="False" description="" />
|
||||
<keyValuePair key="user_board_temp" value="25.0 (C)" description="" />
|
||||
<keyValuePair key="user_effective_thetaja" value="4.6" description="" />
|
||||
<keyValuePair key="user_junc_temp" value="25.5 (C)" description="" />
|
||||
<keyValuePair key="user_thetajb" value="5.7 (C/W)" description="" />
|
||||
<keyValuePair key="user_thetasa" value="4.6 (C/W)" description="" />
|
||||
<keyValuePair key="vccadc_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vccadc_static_current" value="0.020000" description="" />
|
||||
<keyValuePair key="vccadc_total_current" value="0.020000" description="" />
|
||||
<keyValuePair key="vccadc_voltage" value="1.800000" description="" />
|
||||
<keyValuePair key="vccaux_dynamic_current" value="0.000081" description="" />
|
||||
<keyValuePair key="vccaux_io_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vccaux_io_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vccaux_io_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vccaux_io_voltage" value="1.800000" description="" />
|
||||
<keyValuePair key="vccaux_static_current" value="0.018143" description="" />
|
||||
<keyValuePair key="vccaux_total_current" value="0.018224" description="" />
|
||||
<keyValuePair key="vccaux_voltage" value="1.800000" description="" />
|
||||
<keyValuePair key="vccbram_dynamic_current" value="0.000500" description="" />
|
||||
<keyValuePair key="vccbram_static_current" value="0.000398" description="" />
|
||||
<keyValuePair key="vccbram_total_current" value="0.000897" description="" />
|
||||
<keyValuePair key="vccbram_voltage" value="1.000000" description="" />
|
||||
<keyValuePair key="vccint_dynamic_current" value="0.014929" description="" />
|
||||
<keyValuePair key="vccint_static_current" value="0.015310" description="" />
|
||||
<keyValuePair key="vccint_total_current" value="0.030239" description="" />
|
||||
<keyValuePair key="vccint_voltage" value="1.000000" description="" />
|
||||
<keyValuePair key="vcco12_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco12_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco12_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco12_voltage" value="1.200000" description="" />
|
||||
<keyValuePair key="vcco135_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco135_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco135_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco135_voltage" value="1.350000" description="" />
|
||||
<keyValuePair key="vcco15_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco15_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco15_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco15_voltage" value="1.500000" description="" />
|
||||
<keyValuePair key="vcco18_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco18_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco18_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco18_voltage" value="1.800000" description="" />
|
||||
<keyValuePair key="vcco25_dynamic_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco25_static_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco25_total_current" value="0.000000" description="" />
|
||||
<keyValuePair key="vcco25_voltage" value="2.500000" description="" />
|
||||
<keyValuePair key="vcco33_dynamic_current" value="0.000625" description="" />
|
||||
<keyValuePair key="vcco33_static_current" value="0.004000" description="" />
|
||||
<keyValuePair key="vcco33_total_current" value="0.004625" description="" />
|
||||
<keyValuePair key="vcco33_voltage" value="3.300000" description="" />
|
||||
<keyValuePair key="version" value="2017.4" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="report_utilization" level="1" order="7" description="">
|
||||
<section name="clocking" level="2" order="1" description="">
|
||||
<keyValuePair key="bufgctrl_available" value="32" description="" />
|
||||
<keyValuePair key="bufgctrl_fixed" value="0" description="" />
|
||||
<keyValuePair key="bufgctrl_used" value="3" description="" />
|
||||
<keyValuePair key="bufgctrl_util_percentage" value="9.38" description="" />
|
||||
<keyValuePair key="bufhce_available" value="96" description="" />
|
||||
<keyValuePair key="bufhce_fixed" value="0" description="" />
|
||||
<keyValuePair key="bufhce_used" value="0" description="" />
|
||||
<keyValuePair key="bufhce_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="bufio_available" value="24" description="" />
|
||||
<keyValuePair key="bufio_fixed" value="0" description="" />
|
||||
<keyValuePair key="bufio_used" value="0" description="" />
|
||||
<keyValuePair key="bufio_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="bufmrce_available" value="12" description="" />
|
||||
<keyValuePair key="bufmrce_fixed" value="0" description="" />
|
||||
<keyValuePair key="bufmrce_used" value="0" description="" />
|
||||
<keyValuePair key="bufmrce_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="bufr_available" value="24" description="" />
|
||||
<keyValuePair key="bufr_fixed" value="0" description="" />
|
||||
<keyValuePair key="bufr_used" value="0" description="" />
|
||||
<keyValuePair key="bufr_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="mmcme2_adv_available" value="6" description="" />
|
||||
<keyValuePair key="mmcme2_adv_fixed" value="0" description="" />
|
||||
<keyValuePair key="mmcme2_adv_used" value="0" description="" />
|
||||
<keyValuePair key="mmcme2_adv_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="plle2_adv_available" value="6" description="" />
|
||||
<keyValuePair key="plle2_adv_fixed" value="0" description="" />
|
||||
<keyValuePair key="plle2_adv_used" value="0" description="" />
|
||||
<keyValuePair key="plle2_adv_util_percentage" value="0.00" description="" />
|
||||
</section>
|
||||
<section name="dsp" level="2" order="2" description="">
|
||||
<keyValuePair key="dsps_available" value="240" description="" />
|
||||
<keyValuePair key="dsps_fixed" value="0" description="" />
|
||||
<keyValuePair key="dsps_used" value="0" description="" />
|
||||
<keyValuePair key="dsps_util_percentage" value="0.00" description="" />
|
||||
</section>
|
||||
<section name="io_standard" level="2" order="3" description="">
|
||||
<keyValuePair key="blvds_25" value="0" description="" />
|
||||
<keyValuePair key="diff_hstl_i" value="0" description="" />
|
||||
<keyValuePair key="diff_hstl_i_18" value="0" description="" />
|
||||
<keyValuePair key="diff_hstl_ii" value="0" description="" />
|
||||
<keyValuePair key="diff_hstl_ii_18" value="0" description="" />
|
||||
<keyValuePair key="diff_hsul_12" value="0" description="" />
|
||||
<keyValuePair key="diff_mobile_ddr" value="0" description="" />
|
||||
<keyValuePair key="diff_sstl135" value="0" description="" />
|
||||
<keyValuePair key="diff_sstl135_r" value="0" description="" />
|
||||
<keyValuePair key="diff_sstl15" value="0" description="" />
|
||||
<keyValuePair key="diff_sstl15_r" value="0" description="" />
|
||||
<keyValuePair key="diff_sstl18_i" value="0" description="" />
|
||||
<keyValuePair key="diff_sstl18_ii" value="0" description="" />
|
||||
<keyValuePair key="hstl_i" value="0" description="" />
|
||||
<keyValuePair key="hstl_i_18" value="0" description="" />
|
||||
<keyValuePair key="hstl_ii" value="0" description="" />
|
||||
<keyValuePair key="hstl_ii_18" value="0" description="" />
|
||||
<keyValuePair key="hsul_12" value="0" description="" />
|
||||
<keyValuePair key="lvcmos12" value="0" description="" />
|
||||
<keyValuePair key="lvcmos15" value="0" description="" />
|
||||
<keyValuePair key="lvcmos18" value="1" description="" />
|
||||
<keyValuePair key="lvcmos25" value="0" description="" />
|
||||
<keyValuePair key="lvcmos33" value="1" description="" />
|
||||
<keyValuePair key="lvds_25" value="0" description="" />
|
||||
<keyValuePair key="lvttl" value="0" description="" />
|
||||
<keyValuePair key="mini_lvds_25" value="0" description="" />
|
||||
<keyValuePair key="mobile_ddr" value="0" description="" />
|
||||
<keyValuePair key="pci33_3" value="0" description="" />
|
||||
<keyValuePair key="ppds_25" value="0" description="" />
|
||||
<keyValuePair key="rsds_25" value="0" description="" />
|
||||
<keyValuePair key="sstl135" value="0" description="" />
|
||||
<keyValuePair key="sstl135_r" value="0" description="" />
|
||||
<keyValuePair key="sstl15" value="0" description="" />
|
||||
<keyValuePair key="sstl15_r" value="0" description="" />
|
||||
<keyValuePair key="sstl18_i" value="0" description="" />
|
||||
<keyValuePair key="sstl18_ii" value="0" description="" />
|
||||
<keyValuePair key="tmds_33" value="0" description="" />
|
||||
</section>
|
||||
<section name="memory" level="2" order="4" description="">
|
||||
<keyValuePair key="block_ram_tile_available" value="135" description="" />
|
||||
<keyValuePair key="block_ram_tile_fixed" value="0" description="" />
|
||||
<keyValuePair key="block_ram_tile_used" value="6.5" description="" />
|
||||
<keyValuePair key="block_ram_tile_util_percentage" value="4.81" description="" />
|
||||
<keyValuePair key="ramb18_available" value="270" description="" />
|
||||
<keyValuePair key="ramb18_fixed" value="0" description="" />
|
||||
<keyValuePair key="ramb18_used" value="13" description="" />
|
||||
<keyValuePair key="ramb18_util_percentage" value="4.81" description="" />
|
||||
<keyValuePair key="ramb18e1_only_used" value="13" description="" />
|
||||
<keyValuePair key="ramb36_fifo_available" value="135" description="" />
|
||||
<keyValuePair key="ramb36_fifo_fixed" value="0" description="" />
|
||||
<keyValuePair key="ramb36_fifo_used" value="0" description="" />
|
||||
<keyValuePair key="ramb36_fifo_util_percentage" value="0.00" description="" />
|
||||
</section>
|
||||
<section name="primitives" level="2" order="5" description="">
|
||||
<keyValuePair key="bufg_functional_category" value="Clock" description="" />
|
||||
<keyValuePair key="bufg_used" value="3" description="" />
|
||||
<keyValuePair key="carry4_functional_category" value="CarryLogic" description="" />
|
||||
<keyValuePair key="carry4_used" value="128" description="" />
|
||||
<keyValuePair key="fdce_functional_category" value="Flop & Latch" description="" />
|
||||
<keyValuePair key="fdce_used" value="1571" description="" />
|
||||
<keyValuePair key="fdpe_functional_category" value="Flop & Latch" description="" />
|
||||
<keyValuePair key="fdpe_used" value="7" description="" />
|
||||
<keyValuePair key="fdre_functional_category" value="Flop & Latch" description="" />
|
||||
<keyValuePair key="fdre_used" value="591" description="" />
|
||||
<keyValuePair key="fdse_functional_category" value="Flop & Latch" description="" />
|
||||
<keyValuePair key="fdse_used" value="26" description="" />
|
||||
<keyValuePair key="ibuf_functional_category" value="IO" description="" />
|
||||
<keyValuePair key="ibuf_used" value="2" description="" />
|
||||
<keyValuePair key="lut1_functional_category" value="LUT" description="" />
|
||||
<keyValuePair key="lut1_used" value="42" description="" />
|
||||
<keyValuePair key="lut2_functional_category" value="LUT" description="" />
|
||||
<keyValuePair key="lut2_used" value="296" description="" />
|
||||
<keyValuePair key="lut3_functional_category" value="LUT" description="" />
|
||||
<keyValuePair key="lut3_used" value="216" description="" />
|
||||
<keyValuePair key="lut4_functional_category" value="LUT" description="" />
|
||||
<keyValuePair key="lut4_used" value="768" description="" />
|
||||
<keyValuePair key="lut5_functional_category" value="LUT" description="" />
|
||||
<keyValuePair key="lut5_used" value="1121" description="" />
|
||||
<keyValuePair key="lut6_functional_category" value="LUT" description="" />
|
||||
<keyValuePair key="lut6_used" value="2937" description="" />
|
||||
<keyValuePair key="muxf7_functional_category" value="MuxFx" description="" />
|
||||
<keyValuePair key="muxf7_used" value="170" description="" />
|
||||
<keyValuePair key="muxf8_functional_category" value="MuxFx" description="" />
|
||||
<keyValuePair key="muxf8_used" value="6" description="" />
|
||||
<keyValuePair key="obuf_functional_category" value="IO" description="" />
|
||||
<keyValuePair key="obuf_used" value="25" description="" />
|
||||
<keyValuePair key="obuft_functional_category" value="IO" description="" />
|
||||
<keyValuePair key="obuft_used" value="6" description="" />
|
||||
<keyValuePair key="ramb18e1_functional_category" value="Block Memory" description="" />
|
||||
<keyValuePair key="ramb18e1_used" value="13" description="" />
|
||||
<keyValuePair key="srl16e_functional_category" value="Distributed Memory" description="" />
|
||||
<keyValuePair key="srl16e_used" value="1" description="" />
|
||||
</section>
|
||||
<section name="slice_logic" level="2" order="6" description="">
|
||||
<keyValuePair key="f7_muxes_available" value="31700" description="" />
|
||||
<keyValuePair key="f7_muxes_fixed" value="0" description="" />
|
||||
<keyValuePair key="f7_muxes_used" value="170" description="" />
|
||||
<keyValuePair key="f7_muxes_util_percentage" value="0.54" description="" />
|
||||
<keyValuePair key="f8_muxes_available" value="15850" description="" />
|
||||
<keyValuePair key="f8_muxes_fixed" value="0" description="" />
|
||||
<keyValuePair key="f8_muxes_used" value="6" description="" />
|
||||
<keyValuePair key="f8_muxes_util_percentage" value="0.04" description="" />
|
||||
<keyValuePair key="fully_used_lut_ff_pairs_fixed" value="1.73" description="" />
|
||||
<keyValuePair key="fully_used_lut_ff_pairs_used" value="49" description="" />
|
||||
<keyValuePair key="lut_as_distributed_ram_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_distributed_ram_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_distributed_ram_used" value="0" description="" />
|
||||
<keyValuePair key="lut_as_distributed_ram_used" value="0" description="" />
|
||||
<keyValuePair key="lut_as_logic_available" value="63400" description="" />
|
||||
<keyValuePair key="lut_as_logic_available" value="63400" description="" />
|
||||
<keyValuePair key="lut_as_logic_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_logic_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_logic_used" value="4863" description="" />
|
||||
<keyValuePair key="lut_as_logic_used" value="4863" description="" />
|
||||
<keyValuePair key="lut_as_logic_util_percentage" value="7.67" description="" />
|
||||
<keyValuePair key="lut_as_logic_util_percentage" value="7.67" description="" />
|
||||
<keyValuePair key="lut_as_memory_available" value="19000" description="" />
|
||||
<keyValuePair key="lut_as_memory_available" value="19000" description="" />
|
||||
<keyValuePair key="lut_as_memory_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_memory_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_memory_used" value="1" description="" />
|
||||
<keyValuePair key="lut_as_memory_used" value="1" description="" />
|
||||
<keyValuePair key="lut_as_memory_util_percentage" value="<0.01" description="" />
|
||||
<keyValuePair key="lut_as_memory_util_percentage" value="<0.01" description="" />
|
||||
<keyValuePair key="lut_as_shift_register_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_shift_register_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_as_shift_register_used" value="1" description="" />
|
||||
<keyValuePair key="lut_as_shift_register_used" value="1" description="" />
|
||||
<keyValuePair key="lut_ff_pairs_with_one_unused_flip_flop_fixed" value="1" description="" />
|
||||
<keyValuePair key="lut_ff_pairs_with_one_unused_flip_flop_used" value="1546" description="" />
|
||||
<keyValuePair key="lut_ff_pairs_with_one_unused_lut_output_fixed" value="1546" description="" />
|
||||
<keyValuePair key="lut_ff_pairs_with_one_unused_lut_output_used" value="1531" description="" />
|
||||
<keyValuePair key="lut_flip_flop_pairs_available" value="63400" description="" />
|
||||
<keyValuePair key="lut_flip_flop_pairs_fixed" value="0" description="" />
|
||||
<keyValuePair key="lut_flip_flop_pairs_used" value="1620" description="" />
|
||||
<keyValuePair key="lut_flip_flop_pairs_util_percentage" value="2.56" description="" />
|
||||
<keyValuePair key="register_as_flip_flop_available" value="126800" description="" />
|
||||
<keyValuePair key="register_as_flip_flop_fixed" value="0" description="" />
|
||||
<keyValuePair key="register_as_flip_flop_used" value="2195" description="" />
|
||||
<keyValuePair key="register_as_flip_flop_util_percentage" value="1.73" description="" />
|
||||
<keyValuePair key="register_as_latch_available" value="126800" description="" />
|
||||
<keyValuePair key="register_as_latch_fixed" value="0" description="" />
|
||||
<keyValuePair key="register_as_latch_used" value="0" description="" />
|
||||
<keyValuePair key="register_as_latch_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="slice_available" value="15850" description="" />
|
||||
<keyValuePair key="slice_fixed" value="0" description="" />
|
||||
<keyValuePair key="slice_luts_available" value="63400" description="" />
|
||||
<keyValuePair key="slice_luts_fixed" value="0" description="" />
|
||||
<keyValuePair key="slice_luts_used" value="4864" description="" />
|
||||
<keyValuePair key="slice_luts_util_percentage" value="7.67" description="" />
|
||||
<keyValuePair key="slice_registers_available" value="126800" description="" />
|
||||
<keyValuePair key="slice_registers_fixed" value="0" description="" />
|
||||
<keyValuePair key="slice_registers_used" value="2195" description="" />
|
||||
<keyValuePair key="slice_registers_util_percentage" value="1.73" description="" />
|
||||
<keyValuePair key="slice_used" value="1626" description="" />
|
||||
<keyValuePair key="slice_util_percentage" value="10.26" description="" />
|
||||
<keyValuePair key="slicel_fixed" value="0" description="" />
|
||||
<keyValuePair key="slicel_used" value="1112" description="" />
|
||||
<keyValuePair key="slicem_fixed" value="0" description="" />
|
||||
<keyValuePair key="slicem_used" value="514" description="" />
|
||||
<keyValuePair key="unique_control_sets_used" value="286" description="" />
|
||||
<keyValuePair key="using_o5_and_o6_fixed" value="286" description="" />
|
||||
<keyValuePair key="using_o5_and_o6_used" value="0" description="" />
|
||||
<keyValuePair key="using_o5_output_only_fixed" value="0" description="" />
|
||||
<keyValuePair key="using_o5_output_only_used" value="1" description="" />
|
||||
<keyValuePair key="using_o6_output_only_fixed" value="1" description="" />
|
||||
<keyValuePair key="using_o6_output_only_used" value="0" description="" />
|
||||
</section>
|
||||
<section name="specific_feature" level="2" order="7" description="">
|
||||
<keyValuePair key="bscane2_available" value="4" description="" />
|
||||
<keyValuePair key="bscane2_fixed" value="0" description="" />
|
||||
<keyValuePair key="bscane2_used" value="0" description="" />
|
||||
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|
||||
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|
||||
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|
||||
<keyValuePair key="capturee2_used" value="0" description="" />
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<keyValuePair key="efuse_usr_util_percentage" value="0.00" description="" />
|
||||
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|
||||
<keyValuePair key="frame_ecce2_fixed" value="0" description="" />
|
||||
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|
||||
<keyValuePair key="frame_ecce2_util_percentage" value="0.00" description="" />
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<keyValuePair key="pcie_2_1_fixed" value="0" description="" />
|
||||
<keyValuePair key="pcie_2_1_used" value="0" description="" />
|
||||
<keyValuePair key="pcie_2_1_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="startupe2_available" value="1" description="" />
|
||||
<keyValuePair key="startupe2_fixed" value="0" description="" />
|
||||
<keyValuePair key="startupe2_used" value="0" description="" />
|
||||
<keyValuePair key="startupe2_util_percentage" value="0.00" description="" />
|
||||
<keyValuePair key="xadc_available" value="1" description="" />
|
||||
<keyValuePair key="xadc_fixed" value="0" description="" />
|
||||
<keyValuePair key="xadc_used" value="0" description="" />
|
||||
<keyValuePair key="xadc_util_percentage" value="0.00" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="router" level="1" order="8" description="">
|
||||
<section name="usage" level="2" order="1" description="">
|
||||
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|
||||
<keyValuePair key="bogomips" value="0" description="" />
|
||||
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|
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|
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|
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|
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|
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|
||||
<keyValuePair key="dsp" value="0" description="" />
|
||||
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|
||||
<keyValuePair key="estimated_expansions" value="6968538" description="" />
|
||||
<keyValuePair key="ff" value="2195" description="" />
|
||||
<keyValuePair key="global_clocks" value="3" description="" />
|
||||
<keyValuePair key="high_fanout_nets" value="1" description="" />
|
||||
<keyValuePair key="iob" value="33" description="" />
|
||||
<keyValuePair key="lut" value="5187" description="" />
|
||||
<keyValuePair key="movable_instances" value="7980" description="" />
|
||||
<keyValuePair key="nets" value="8403" description="" />
|
||||
<keyValuePair key="pins" value="48589" description="" />
|
||||
<keyValuePair key="pll" value="0" description="" />
|
||||
<keyValuePair key="router_runtime" value="0.000000" description="" />
|
||||
<keyValuePair key="router_timing_driven" value="1" description="" />
|
||||
<keyValuePair key="threads" value="2" description="" />
|
||||
<keyValuePair key="timing_constraints_exist" value="1" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="synthesis" level="1" order="9" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="-assert" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-bufg" value="default::12" description="" />
|
||||
<keyValuePair key="-cascade_dsp" value="default::auto" description="" />
|
||||
<keyValuePair key="-constrset" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-control_set_opt_threshold" value="default::auto" description="" />
|
||||
<keyValuePair key="-directive" value="default::default" description="" />
|
||||
<keyValuePair key="-fanout_limit" value="default::10000" description="" />
|
||||
<keyValuePair key="-flatten_hierarchy" value="default::rebuilt" description="" />
|
||||
<keyValuePair key="-fsm_extraction" value="default::auto" description="" />
|
||||
<keyValuePair key="-gated_clock_conversion" value="default::off" description="" />
|
||||
<keyValuePair key="-generic" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-include_dirs" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-keep_equivalent_registers" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-max_bram" value="default::-1" description="" />
|
||||
<keyValuePair key="-max_bram_cascade_height" value="default::-1" description="" />
|
||||
<keyValuePair key="-max_dsp" value="default::-1" description="" />
|
||||
<keyValuePair key="-max_uram" value="default::-1" description="" />
|
||||
<keyValuePair key="-max_uram_cascade_height" value="default::-1" description="" />
|
||||
<keyValuePair key="-mode" value="default::default" description="" />
|
||||
<keyValuePair key="-name" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-no_lc" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-no_srlextract" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-no_timing_driven" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-part" value="xc7a100tcsg324-1" description="" />
|
||||
<keyValuePair key="-resource_sharing" value="default::auto" description="" />
|
||||
<keyValuePair key="-retiming" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-rtl" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-rtl_skip_constraints" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-rtl_skip_ip" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-seu_protect" value="default::none" description="" />
|
||||
<keyValuePair key="-sfcu" value="default::[not_specified]" description="" />
|
||||
<keyValuePair key="-shreg_min_size" value="default::3" description="" />
|
||||
<keyValuePair key="-top" value="Nexys4_USTCRVSoC_top" description="" />
|
||||
<keyValuePair key="-verilog_define" value="default::[not_specified]" description="" />
|
||||
</section>
|
||||
<section name="usage" level="2" order="2" description="">
|
||||
<keyValuePair key="elapsed" value="00:01:32s" description="" />
|
||||
<keyValuePair key="hls_ip" value="0" description="" />
|
||||
<keyValuePair key="memory_gain" value="876.070MB" description="" />
|
||||
<keyValuePair key="memory_peak" value="1165.590MB" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="unisim_transformation" level="1" order="10" description="">
|
||||
<section name="post_unisim_transformation" level="2" order="1" description="">
|
||||
<keyValuePair key="bufg" value="3" description="" />
|
||||
<keyValuePair key="carry4" value="128" description="" />
|
||||
<keyValuePair key="fdce" value="1563" description="" />
|
||||
<keyValuePair key="fdpe" value="7" description="" />
|
||||
<keyValuePair key="fdre" value="581" description="" />
|
||||
<keyValuePair key="fdse" value="26" description="" />
|
||||
<keyValuePair key="gnd" value="23" description="" />
|
||||
<keyValuePair key="ibuf" value="2" description="" />
|
||||
<keyValuePair key="lut1" value="45" description="" />
|
||||
<keyValuePair key="lut2" value="296" description="" />
|
||||
<keyValuePair key="lut3" value="211" description="" />
|
||||
<keyValuePair key="lut4" value="768" description="" />
|
||||
<keyValuePair key="lut5" value="1121" description="" />
|
||||
<keyValuePair key="lut6" value="2937" description="" />
|
||||
<keyValuePair key="muxf7" value="170" description="" />
|
||||
<keyValuePair key="muxf8" value="6" description="" />
|
||||
<keyValuePair key="obuf" value="25" description="" />
|
||||
<keyValuePair key="obuft" value="6" description="" />
|
||||
<keyValuePair key="ramb18e1" value="13" description="" />
|
||||
<keyValuePair key="srl16e" value="1" description="" />
|
||||
<keyValuePair key="vcc" value="28" description="" />
|
||||
</section>
|
||||
<section name="pre_unisim_transformation" level="2" order="2" description="">
|
||||
<keyValuePair key="bufg" value="3" description="" />
|
||||
<keyValuePair key="carry4" value="128" description="" />
|
||||
<keyValuePair key="fdce" value="1563" description="" />
|
||||
<keyValuePair key="fdpe" value="7" description="" />
|
||||
<keyValuePair key="fdre" value="581" description="" />
|
||||
<keyValuePair key="fdse" value="26" description="" />
|
||||
<keyValuePair key="gnd" value="23" description="" />
|
||||
<keyValuePair key="ibuf" value="2" description="" />
|
||||
<keyValuePair key="lut1" value="45" description="" />
|
||||
<keyValuePair key="lut2" value="296" description="" />
|
||||
<keyValuePair key="lut3" value="211" description="" />
|
||||
<keyValuePair key="lut4" value="768" description="" />
|
||||
<keyValuePair key="lut5" value="1121" description="" />
|
||||
<keyValuePair key="lut6" value="2937" description="" />
|
||||
<keyValuePair key="muxf7" value="170" description="" />
|
||||
<keyValuePair key="muxf8" value="6" description="" />
|
||||
<keyValuePair key="obuf" value="25" description="" />
|
||||
<keyValuePair key="obuft" value="6" description="" />
|
||||
<keyValuePair key="ramb18e1" value="13" description="" />
|
||||
<keyValuePair key="srl16e" value="1" description="" />
|
||||
<keyValuePair key="vcc" value="28" description="" />
|
||||
</section>
|
||||
</section>
|
||||
<section name="vivado_usage" level="1" order="11" description="">
|
||||
<section name="gui_handlers" level="2" order="1" description="">
|
||||
<keyValuePair key="addsrcwizard_specify_hdl_netlist_block_design" value="2" description="" />
|
||||
<keyValuePair key="basedialog_cancel" value="3" description="" />
|
||||
<keyValuePair key="basedialog_ok" value="16" description="" />
|
||||
<keyValuePair key="commandsinput_type_tcl_command_here" value="2" description="" />
|
||||
<keyValuePair key="constraintschooserpanel_add_files" value="1" description="" />
|
||||
<keyValuePair key="constraintschooserpanel_create_file" value="1" description="" />
|
||||
<keyValuePair key="coretreetablepanel_core_tree_table" value="3" description="" />
|
||||
<keyValuePair key="createconstraintsfilepanel_file_name" value="2" description="" />
|
||||
<keyValuePair key="createsrcfiledialog_file_name" value="1" description="" />
|
||||
<keyValuePair key="createsrcfiledialog_file_type" value="1" description="" />
|
||||
<keyValuePair key="filesetpanel_file_set_panel_tree" value="107" description="" />
|
||||
<keyValuePair key="flownavigatortreepanel_flow_navigator_tree" value="13" description="" />
|
||||
<keyValuePair key="gettingstartedview_create_new_project" value="1" description="" />
|
||||
<keyValuePair key="hcodeeditor_search_text_combo_box" value="7" description="" />
|
||||
<keyValuePair key="ipcoreview_tabbed_pane" value="2" description="" />
|
||||
<keyValuePair key="logmonitor_monitor" value="3" description="" />
|
||||
<keyValuePair key="mainmenumgr_file" value="2" description="" />
|
||||
<keyValuePair key="mainmenumgr_help" value="4" description="" />
|
||||
<keyValuePair key="mainmenumgr_tools" value="1" description="" />
|
||||
<keyValuePair key="mainmenumgr_view" value="2" description="" />
|
||||
<keyValuePair key="mainmenumgr_window" value="2" description="" />
|
||||
<keyValuePair key="maintoolbarmgr_run" value="8" description="" />
|
||||
<keyValuePair key="mainwinmenumgr_layout" value="2" description="" />
|
||||
<keyValuePair key="messagewithoptiondialog_dont_show_this_dialog_again" value="1" description="" />
|
||||
<keyValuePair key="msgtreepanel_message_severity" value="2" description="" />
|
||||
<keyValuePair key="msgtreepanel_message_view_tree" value="41" description="" />
|
||||
<keyValuePair key="msgview_critical_warnings" value="5" description="" />
|
||||
<keyValuePair key="msgview_warning_messages" value="2" description="" />
|
||||
<keyValuePair key="netlisttreeview_netlist_tree" value="11" description="" />
|
||||
<keyValuePair key="pacommandnames_add_sources" value="6" description="" />
|
||||
<keyValuePair key="pacommandnames_auto_connect_target" value="2" description="" />
|
||||
<keyValuePair key="pacommandnames_auto_update_hier" value="13" description="" />
|
||||
<keyValuePair key="pacommandnames_license_manage" value="1" description="" />
|
||||
<keyValuePair key="pacommandnames_reports_window" value="1" description="" />
|
||||
<keyValuePair key="pacommandnames_run_bitgen" value="8" description="" />
|
||||
<keyValuePair key="pacommandnames_run_synthesis" value="6" description="" />
|
||||
<keyValuePair key="pacommandnames_set_as_top" value="2" description="" />
|
||||
<keyValuePair key="partchooser_family_chooser" value="1" description="" />
|
||||
<keyValuePair key="partchooser_parts" value="2" description="" />
|
||||
<keyValuePair key="paviews_code" value="8" description="" />
|
||||
<keyValuePair key="paviews_device" value="2" description="" />
|
||||
<keyValuePair key="programfpgadialog_program" value="1" description="" />
|
||||
<keyValuePair key="progressdialog_background" value="1" description="" />
|
||||
<keyValuePair key="projectnamechooser_choose_project_location" value="1" description="" />
|
||||
<keyValuePair key="projectnamechooser_project_name" value="2" description="" />
|
||||
<keyValuePair key="projectsummarytimingpanel_project_summary_timing_panel_tabbed" value="11" description="" />
|
||||
<keyValuePair key="projectsummaryutilizationgadget_project_summary_utilization_gadget_tabbed" value="1" description="" />
|
||||
<keyValuePair key="projectsummaryutilizationpanel_project_summary_utilization_panel_tabbed" value="2" description="" />
|
||||
<keyValuePair key="rdicommands_delete" value="4" description="" />
|
||||
<keyValuePair key="rungadget_run_gadget_tabbed_pane" value="1" description="" />
|
||||
<keyValuePair key="rungadget_show_error" value="2" description="" />
|
||||
<keyValuePair key="saveprojectutils_cancel" value="1" description="" />
|
||||
<keyValuePair key="saveprojectutils_save" value="2" description="" />
|
||||
<keyValuePair key="srcchooserpanel_add_hdl_and_netlist_files_to_your_project" value="3" description="" />
|
||||
<keyValuePair key="srcchooserpanel_create_file" value="1" description="" />
|
||||
<keyValuePair key="srcmenu_ip_hierarchy" value="11" description="" />
|
||||
<keyValuePair key="srcmenu_refresh_hierarchy" value="1" description="" />
|
||||
<keyValuePair key="stalerundialog_yes" value="1" description="" />
|
||||
<keyValuePair key="syntheticagettingstartedview_recent_projects" value="2" description="" />
|
||||
<keyValuePair key="syntheticastatemonitor_cancel" value="1" description="" />
|
||||
<keyValuePair key="taskbanner_close" value="1" description="" />
|
||||
<keyValuePair key="touchpointsurveydialog_no" value="1" description="" />
|
||||
</section>
|
||||
<section name="java_command_handlers" level="2" order="2" description="">
|
||||
<keyValuePair key="addsources" value="6" description="" />
|
||||
<keyValuePair key="autoconnecttarget" value="2" description="" />
|
||||
<keyValuePair key="coreview" value="1" description="" />
|
||||
<keyValuePair key="customizecore" value="1" description="" />
|
||||
<keyValuePair key="editdelete" value="4" description="" />
|
||||
<keyValuePair key="launchprogramfpga" value="2" description="" />
|
||||
<keyValuePair key="newproject" value="1" description="" />
|
||||
<keyValuePair key="openhardwaremanager" value="6" description="" />
|
||||
<keyValuePair key="openrecenttarget" value="2" description="" />
|
||||
<keyValuePair key="programdevice" value="2" description="" />
|
||||
<keyValuePair key="reportutilization" value="1" description="" />
|
||||
<keyValuePair key="runbitgen" value="8" description="" />
|
||||
<keyValuePair key="runimplementation" value="3" description="" />
|
||||
<keyValuePair key="runsynthesis" value="6" description="" />
|
||||
<keyValuePair key="savefileproxyhandler" value="1" description="" />
|
||||
<keyValuePair key="settopnode" value="2" description="" />
|
||||
<keyValuePair key="showview" value="7" description="" />
|
||||
<keyValuePair key="updateregid" value="1" description="" />
|
||||
<keyValuePair key="viewtasksynthesis" value="1" description="" />
|
||||
</section>
|
||||
<section name="other_data" level="2" order="3" description="">
|
||||
<keyValuePair key="guimode" value="4" description="" />
|
||||
</section>
|
||||
<section name="project_data" level="2" order="4" description="">
|
||||
<keyValuePair key="constraintsetcount" value="1" description="" />
|
||||
<keyValuePair key="core_container" value="false" description="" />
|
||||
<keyValuePair key="currentimplrun" value="impl_1" description="" />
|
||||
<keyValuePair key="currentsynthesisrun" value="synth_1" description="" />
|
||||
<keyValuePair key="default_library" value="xil_defaultlib" description="" />
|
||||
<keyValuePair key="designmode" value="RTL" description="" />
|
||||
<keyValuePair key="export_simulation_activehdl" value="0" description="" />
|
||||
<keyValuePair key="export_simulation_ies" value="0" description="" />
|
||||
<keyValuePair key="export_simulation_modelsim" value="0" description="" />
|
||||
<keyValuePair key="export_simulation_questa" value="0" description="" />
|
||||
<keyValuePair key="export_simulation_riviera" value="0" description="" />
|
||||
<keyValuePair key="export_simulation_vcs" value="0" description="" />
|
||||
<keyValuePair key="export_simulation_xsim" value="0" description="" />
|
||||
<keyValuePair key="implstrategy" value="Vivado Implementation Defaults" description="" />
|
||||
<keyValuePair key="launch_simulation_activehdl" value="0" description="" />
|
||||
<keyValuePair key="launch_simulation_ies" value="0" description="" />
|
||||
<keyValuePair key="launch_simulation_modelsim" value="0" description="" />
|
||||
<keyValuePair key="launch_simulation_questa" value="0" description="" />
|
||||
<keyValuePair key="launch_simulation_riviera" value="0" description="" />
|
||||
<keyValuePair key="launch_simulation_vcs" value="0" description="" />
|
||||
<keyValuePair key="launch_simulation_xsim" value="0" description="" />
|
||||
<keyValuePair key="simulator_language" value="Mixed" description="" />
|
||||
<keyValuePair key="srcsetcount" value="18" description="" />
|
||||
<keyValuePair key="synthesisstrategy" value="Vivado Synthesis Defaults" description="" />
|
||||
<keyValuePair key="target_language" value="Verilog" description="" />
|
||||
<keyValuePair key="target_simulator" value="XSim" description="" />
|
||||
<keyValuePair key="totalimplruns" value="1" description="" />
|
||||
<keyValuePair key="totalsynthesisruns" value="1" description="" />
|
||||
</section>
|
||||
</section>
|
||||
</section>
|
||||
</webTalkData>
|
||||
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Tue Feb 26 19:20:55 2019
|
||||
# Process ID: 20504
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1
|
||||
# Command line: vivado.exe -log Nexys4_USTCRVSoC_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Nexys4_USTCRVSoC_top.tcl -notrace
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.vdi
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source Nexys4_USTCRVSoC_top.tcl -notrace
|
||||
Binary file not shown.
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Tue Feb 26 19:10:27 2019
|
||||
# Process ID: 17984
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1
|
||||
# Command line: vivado.exe -log Nexys4_USTCRVSoC_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Nexys4_USTCRVSoC_top.tcl -notrace
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.vdi
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source Nexys4_USTCRVSoC_top.tcl -notrace
|
||||
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Tue Feb 26 17:56:46 2019
|
||||
# Process ID: 520
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1
|
||||
# Command line: vivado.exe -log Nexys4_USTCRVSoC_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Nexys4_USTCRVSoC_top.tcl -notrace
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.vdi
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source Nexys4_USTCRVSoC_top.tcl -notrace
|
||||
Binary file not shown.
@ -1,99 +0,0 @@
|
||||
set_property SRC_FILE_INFO {cfile:E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc rfile:../../../USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc id:1} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
|
||||
set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
|
||||
set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
set_property src_info {type:XDC file:1 line:134 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
|
||||
set_property src_info {type:XDC file:1 line:135 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
|
||||
set_property src_info {type:XDC file:1 line:136 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
|
||||
set_property src_info {type:XDC file:1 line:137 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
|
||||
set_property src_info {type:XDC file:1 line:138 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
|
||||
set_property src_info {type:XDC file:1 line:139 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
|
||||
set_property src_info {type:XDC file:1 line:140 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
|
||||
set_property src_info {type:XDC file:1 line:141 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
|
||||
set_property src_info {type:XDC file:1 line:142 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
|
||||
set_property src_info {type:XDC file:1 line:143 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
|
||||
set_property src_info {type:XDC file:1 line:144 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
|
||||
set_property src_info {type:XDC file:1 line:145 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
|
||||
set_property src_info {type:XDC file:1 line:146 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs
|
||||
set_property src_info {type:XDC file:1 line:147 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
|
||||
set_property src_info {type:XDC file:1 line:183 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
set_property src_info {type:XDC file:1 line:184 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="wgg" Host="DESKTOP-C6I6OAQ" Pid="24220">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
@ -1,244 +0,0 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
@ -1,63 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
Binary file not shown.
@ -1,68 +0,0 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
create_project -in_memory -part xc7a100tcsg324-1
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_property webtalk.parent_dir E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt [current_project]
|
||||
set_property parent.project_path E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo e:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_verilog -library xil_defaultlib -sv {
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv
|
||||
E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/sources_1/Nexys4_USTCRVSoC_top.sv
|
||||
}
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc
|
||||
set_property used_in_implementation false [get_files E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc]
|
||||
|
||||
|
||||
synth_design -top Nexys4_USTCRVSoC_top -part xc7a100tcsg324-1
|
||||
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef Nexys4_USTCRVSoC_top.dcp
|
||||
create_report "synth_1_synth_report_utilization_0" "report_utilization -file Nexys4_USTCRVSoC_top_utilization_synth.rpt -pb Nexys4_USTCRVSoC_top_utilization_synth.pb"
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
@ -1,5 +0,0 @@
|
||||
|
||||
add_fsm_encoding \
|
||||
{isp_uart.fsm} \
|
||||
{ } \
|
||||
{{00000000000000000000000000000000 0000} {00000000000000000000000000000001 0001} {00000000000000000000000000000010 0010} {00000000000000000000000000000011 0011} {00000000000000000000000000000100 0100} {00000000000000000000000000000101 0101} {00000000000000000000000000000110 0110} {00000000000000000000000000000111 0111} {00000000000000000000000000001000 1000} }
|
||||
@ -1,161 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7a100tcsg324-1" LaunchTime="1551179941">
|
||||
<File Type="PA-TCL" Name="Nexys4_USTCRVSoC_top.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="Nexys4_USTCRVSoC_top_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="Nexys4_USTCRVSoC_top_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="Nexys4_USTCRVSoC_top.vds"/>
|
||||
<File Type="RDS-UTIL" Name="Nexys4_USTCRVSoC_top_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="Nexys4_USTCRVSoC_top_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="Nexys4_USTCRVSoC_top.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="Nexys4_USTCRVSoC_top_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="Nexys4_USTCRVSoC_top_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../../RTL/core_alu.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_bus_wrapper.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_ex_branch_judge.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_id_stage.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_regfile.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_top.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/instr_rom.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/isp_uart.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/naive_bus.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/naive_bus_router.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/ram.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/ram_bus_wrapper.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/soc_top.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/uart_rx.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/uart_tx_line.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/user_uart_tx.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/video_ram.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/Nexys4_USTCRVSoC_top.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="Nexys4_USTCRVSoC_top"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/Nexys-A7-100T-Master.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
@ -1,9 +0,0 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log Nexys4_USTCRVSoC_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Nexys4_USTCRVSoC_top.tcl
|
||||
@ -1,36 +0,0 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "C:/Xilinx/SDK/2017.4/bin;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2017.4/bin;";
|
||||
} else {
|
||||
PathVal = "C:/Xilinx/SDK/2017.4/bin;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2017.4/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log Nexys4_USTCRVSoC_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Nexys4_USTCRVSoC_top.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
@ -1,10 +0,0 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,43 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
|
||||
exit
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=C:/Xilinx/SDK/2017.4/bin;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2017.4/bin
|
||||
else
|
||||
PATH=C:/Xilinx/SDK/2017.4/bin;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2017.4/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log Nexys4_USTCRVSoC_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Nexys4_USTCRVSoC_top.tcl
|
||||
@ -1,12 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Tue Feb 26 19:19:03 2019
|
||||
# Process ID: 19248
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1
|
||||
# Command line: vivado.exe -log Nexys4_USTCRVSoC_top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Nexys4_USTCRVSoC_top.tcl
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1/Nexys4_USTCRVSoC_top.vds
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source Nexys4_USTCRVSoC_top.tcl -notrace
|
||||
Binary file not shown.
@ -2,37 +2,13 @@
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Tue Feb 26 17:52:17 2019
|
||||
# Process ID: 23044
|
||||
# Start of session at: Tue Feb 26 19:41:37 2019
|
||||
# Process ID: 9988
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent24448 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent15848 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
update_compile_order -fileset sources_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 8
|
||||
wait_on_run synth_1
|
||||
launch_runs impl_1 -jobs 8
|
||||
wait_on_run impl_1
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
wait_on_run impl_1
|
||||
reset_run impl_1 -prev_step
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
wait_on_run impl_1
|
||||
reset_run synth_1
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
wait_on_run impl_1
|
||||
open_hw
|
||||
connect_hw_server
|
||||
open_hw_target
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
current_hw_device [get_hw_devices xc7a100t_0]
|
||||
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
program_hw_devices [get_hw_devices xc7a100t_0]
|
||||
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
|
||||
@ -1,78 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Tue Feb 26 17:52:17 2019
|
||||
# Process ID: 23044
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent24448 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
INFO: [Project 1-313] Project file moved from 'E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4' since last save.
|
||||
Scanning sources...
|
||||
Finished scanning sources
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
|
||||
open_project: Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 844.801 ; gain = 82.859
|
||||
update_compile_order -fileset sources_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 8
|
||||
[Tue Feb 26 17:54:47 2019] Launched synth_1...
|
||||
Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1/runme.log
|
||||
launch_runs impl_1 -jobs 8
|
||||
[Tue Feb 26 17:56:39 2019] Launched impl_1...
|
||||
Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/runme.log
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
[Tue Feb 26 19:10:15 2019] Launched impl_1...
|
||||
Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/runme.log
|
||||
reset_run impl_1 -prev_step
|
||||
WARNING: [Vivado 12-1017] Problems encountered:
|
||||
1. PID not specified
|
||||
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
[Tue Feb 26 19:10:53 2019] Launched impl_1...
|
||||
Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/runme.log
|
||||
reset_run synth_1
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
[Tue Feb 26 19:19:01 2019] Launched synth_1...
|
||||
Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1/runme.log
|
||||
[Tue Feb 26 19:19:01 2019] Launched impl_1...
|
||||
Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/runme.log
|
||||
open_hw
|
||||
connect_hw_server
|
||||
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
|
||||
INFO: [Labtools 27-2222] Launching hw_server...
|
||||
INFO: [Labtools 27-2221] Launch Output:
|
||||
|
||||
****** Xilinx hw_server v2017.4
|
||||
**** Build date : Dec 15 2017-21:08:27
|
||||
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
open_hw_target
|
||||
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A8B5DFA
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
current_hw_device [get_hw_devices xc7a100t_0]
|
||||
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
||||
WARNING: [Labtools 27-3361] The debug hub core was not detected.
|
||||
Resolution:
|
||||
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
|
||||
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
|
||||
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
|
||||
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
program_hw_devices [get_hw_devices xc7a100t_0]
|
||||
INFO: [Labtools 27-3164] End of startup status: HIGH
|
||||
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
||||
WARNING: [Labtools 27-3361] The debug hub core was not detected.
|
||||
Resolution:
|
||||
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
|
||||
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
|
||||
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
|
||||
@ -1,303 +0,0 @@
|
||||
/*
|
||||
|
||||
Xilinx Vivado v2017.4 (64-bit) [Major: 2017, Minor: 4]
|
||||
SW Build: 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
IP Build: 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
|
||||
Process ID: 23044
|
||||
License: Customer
|
||||
|
||||
Current time: Tue Feb 26 17:52:33 CST 2019
|
||||
Time zone: China Standard Time (Asia/Shanghai)
|
||||
|
||||
OS: Windows 10
|
||||
OS Version: 10.0
|
||||
OS Architecture: amd64
|
||||
Available processors (cores): 12
|
||||
|
||||
Screen size: 1536x864
|
||||
Screen resolution (DPI): 96
|
||||
Available screens: 2
|
||||
Available disk space: 107 GB
|
||||
Default font: family=Dialog,name=Dialog,style=plain,size=12
|
||||
|
||||
Java version: 1.8.0_112 64-bit
|
||||
Java home: C:/Xilinx/Vivado/2017.4/tps/win64/jre
|
||||
JVM executable location: C:/Xilinx/Vivado/2017.4/tps/win64/jre/bin/java.exe
|
||||
|
||||
User name: wgg
|
||||
User home directory: C:/Users/wgg
|
||||
User working directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
User country: CN
|
||||
User language: zh
|
||||
User locale: zh_CN
|
||||
|
||||
RDI_BASEROOT: C:/Xilinx/Vivado
|
||||
HDI_APPROOT: C:/Xilinx/Vivado/2017.4
|
||||
RDI_DATADIR: C:/Xilinx/Vivado/2017.4/data
|
||||
RDI_BINDIR: C:/Xilinx/Vivado/2017.4/bin
|
||||
|
||||
Vivado preferences file location: C:/Users/wgg/AppData/Roaming/Xilinx/Vivado/2017.4/vivado.xml
|
||||
Vivado preferences directory: C:/Users/wgg/AppData/Roaming/Xilinx/Vivado/2017.4/
|
||||
Vivado layouts directory: C:/Users/wgg/AppData/Roaming/Xilinx/Vivado/2017.4/layouts
|
||||
PlanAhead jar file location: C:/Xilinx/Vivado/2017.4/lib/classes/planAhead.jar
|
||||
Vivado log file location: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
Vivado journal file location: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.jou
|
||||
Engine tmp dir: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/.Xil/Vivado-23044-DESKTOP-C6I6OAQ
|
||||
|
||||
GUI allocated memory: 197 MB
|
||||
GUI max memory: 3,052 MB
|
||||
Engine allocated memory: 572 MB
|
||||
|
||||
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
*/
|
||||
|
||||
// TclEventType: START_GUI
|
||||
// TclEventType: PROJECT_OPEN_DIALOG
|
||||
// Tcl Message: start_gui
|
||||
// TclEventType: PROJECT_OPEN_DIALOG
|
||||
// [GUI Memory]: 49 MB (+48710kb) [00:00:04]
|
||||
// [Engine Memory]: 516 MB (+389978kb) [00:00:04]
|
||||
// Opening Vivado Project: E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr. Version: Vivado v2017.4
|
||||
// bs (cj): Open Project : addNotify
|
||||
// TclEventType: DEBUG_PROBE_SET_CHANGE
|
||||
// Tcl Message: open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
// TclEventType: MSGMGR_MOVEMSG
|
||||
// TclEventType: FILE_SET_NEW
|
||||
// TclEventType: RUN_COMPLETED
|
||||
// TclEventType: RUN_CURRENT
|
||||
// TclEventType: PROJECT_NEW
|
||||
// [GUI Memory]: 58 MB (+7234kb) [00:00:07]
|
||||
// [Engine Memory]: 567 MB (+26394kb) [00:00:07]
|
||||
// Tcl Message: open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
// Tcl Message: INFO: [Project 1-313] Project file moved from 'E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4' since last save.
|
||||
// Tcl Message: Scanning sources... Finished scanning sources
|
||||
// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
// TclEventType: PROJECT_NEW
|
||||
// [GUI Memory]: 71 MB (+10160kb) [00:00:09]
|
||||
// [Engine Memory]: 623 MB (+28102kb) [00:00:09]
|
||||
// [GUI Memory]: 95 MB (+21289kb) [00:00:10]
|
||||
// [GUI Memory]: 126 MB (+27539kb) [00:00:11]
|
||||
// [Engine Memory]: 664 MB (+10365kb) [00:00:11]
|
||||
// Tcl Message: INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 701 MB. GUI used memory: 45 MB. Current time: 2/26/19 5:52:37 PM CST
|
||||
// Tcl Message: open_project: Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 844.801 ; gain = 82.859
|
||||
// Project name: USTCRVSoC-nexys4; location: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4; part: xc7a100tcsg324-1
|
||||
// [Engine Memory]: 707 MB (+11092kb) [00:00:12]
|
||||
dismissDialog("Open Project"); // bs (cj)
|
||||
// TclEventType: DG_ANALYSIS_MSG_RESET
|
||||
// TclEventType: DG_GRAPH_GENERATED
|
||||
// Tcl Message: update_compile_order -fileset sources_1
|
||||
// Elapsed time: 60 seconds
|
||||
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Nexys4_USTCRVSoC_top (Nexys4_USTCRVSoC_top.sv)]", 1); // B (D, cj)
|
||||
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Nexys4_USTCRVSoC_top (Nexys4_USTCRVSoC_top.sv)]", 1, true); // B (D, cj) - Node
|
||||
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Nexys4_USTCRVSoC_top (Nexys4_USTCRVSoC_top.sv)]", 1, true, false, false, false, false, true); // B (D, cj) - Double Click - Node
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 139, 277); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 127, 228); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 141, 52); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 58, 198); // cd (w, cj)
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 728 MB. GUI used memory: 47 MB. Current time: 2/26/19 5:53:55 PM CST
|
||||
// Elapsed time: 11 seconds
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 145, 235); // cd (w, cj)
|
||||
// Elapsed time: 11 seconds
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 148, 45); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 148, 45, false, false, false, false, true); // cd (w, cj) - Double Click
|
||||
typeControlKey((HResource) null, "Nexys4_USTCRVSoC_top.sv", 'c'); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 151, 274); // cd (w, cj)
|
||||
typeControlKey((HResource) null, "Nexys4_USTCRVSoC_top.sv", 'v'); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 54, 219); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 193, 275); // cd (w, cj)
|
||||
// Elapsed time: 13 seconds
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 39, 286); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 39, 286, false, false, false, false, true); // cd (w, cj) - Double Click
|
||||
typeControlKey((HResource) null, "Nexys4_USTCRVSoC_top.sv", 'c'); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 188, 407); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 188, 407, false, false, false, false, true); // cd (w, cj) - Double Click
|
||||
typeControlKey((HResource) null, "Nexys4_USTCRVSoC_top.sv", 'v'); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 139, 356); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 156, 349); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 156, 349, false, false, false, false, true); // cd (w, cj) - Double Click
|
||||
typeControlKey((HResource) null, "Nexys4_USTCRVSoC_top.sv", 'v'); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 304, 253); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 320, 151); // cd (w, cj)
|
||||
// TclEventType: DG_GRAPH_STALE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: DG_ANALYSIS_MSG_RESET
|
||||
// TclEventType: DG_ANALYSIS_MSG_RESET
|
||||
// TclEventType: DG_GRAPH_GENERATED
|
||||
selectButton(PAResourceItoN.MainToolbarMgr_RUN, (String) null); // aw (f, cj)
|
||||
selectMenuItem(PAResourceCommand.PACommandNames_RUN_SYNTHESIS, "Run Synthesis"); // ac (cj)
|
||||
// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
|
||||
// x (cj): Run Synthesis: addNotify
|
||||
selectCheckBox(RDIResource.MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN, "Don't show this dialog again", true); // g (N, x): TRUE
|
||||
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (x)
|
||||
// bs (cj): Resetting Runs : addNotify
|
||||
// TclEventType: RUN_MODIFY
|
||||
dismissDialog("Run Synthesis"); // x (cj)
|
||||
// TclEventType: RUN_RESET
|
||||
// TclEventType: RUN_MODIFY
|
||||
// Tcl Message: reset_run synth_1
|
||||
// bs (cj): Starting Design Runs : addNotify
|
||||
// TclEventType: RUN_LAUNCH
|
||||
// TclEventType: RUN_MODIFY
|
||||
// [Engine Memory]: 745 MB (+2022kb) [00:02:22]
|
||||
// Tcl Message: launch_runs synth_1 -jobs 8
|
||||
// Tcl Message: [Tue Feb 26 17:54:47 2019] Launched synth_1... Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1/runme.log
|
||||
// 'k' command handler elapsed time: 4 seconds
|
||||
dismissDialog("Starting Design Runs"); // bs (cj)
|
||||
// TclEventType: RUN_COMPLETED
|
||||
// ah (cj): Synthesis Completed: addNotify
|
||||
// WARNING: HTimer (ActiveMsgMonitor Process Messages Timer) is taking too long to process. Increasing delay to 2000 ms.
|
||||
// Elapsed time: 111 seconds
|
||||
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (ah)
|
||||
// Run Command: PAResourceCommand.PACommandNames_RUN_IMPLEMENTATION
|
||||
// bs (cj): Starting Design Runs : addNotify
|
||||
// TclEventType: RUN_LAUNCH
|
||||
// TclEventType: RUN_MODIFY
|
||||
// Tcl Message: launch_runs impl_1 -jobs 8
|
||||
// Tcl Message: [Tue Feb 26 17:56:39 2019] Launched impl_1... Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/runme.log
|
||||
dismissDialog("Starting Design Runs"); // bs (cj)
|
||||
// TclEventType: RUN_STEP_COMPLETED
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 751 MB. GUI used memory: 49 MB. Current time: 2/26/19 5:57:45 PM CST
|
||||
// TclEventType: RUN_COMPLETED
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 757 MB. GUI used memory: 48 MB. Current time: 2/26/19 6:27:45 PM CST
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 757 MB. GUI used memory: 46 MB. Current time: 2/26/19 6:57:46 PM CST
|
||||
// Elapsed time: 4415 seconds
|
||||
selectButton(PAResourceCommand.PACommandNames_RUN_BITGEN, "run_bitstream"); // B (f, cj)
|
||||
// Run Command: PAResourceCommand.PACommandNames_RUN_BITGEN
|
||||
// TclEventType: RUN_LAUNCH
|
||||
// TclEventType: RUN_MODIFY
|
||||
// Tcl Message: launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
// Tcl Message: [Tue Feb 26 19:10:15 2019] Launched impl_1... Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/runme.log
|
||||
// Elapsed time: 16 seconds
|
||||
selectButton(PAResourceQtoS.SyntheticaStateMonitor_CANCEL, "Cancel"); // h (N, cj)
|
||||
// bs (cj): Reset to Previous Step : addNotify
|
||||
// TclEventType: RUN_MODIFY
|
||||
// TclEventType: RUN_RESET
|
||||
// Tcl Message: reset_run impl_1 -prev_step
|
||||
selectButton(RDIResource.ProgressDialog_BACKGROUND, "Background"); // a (bs)
|
||||
// TclEventType: RUN_COMPLETED
|
||||
// TclEventType: RUN_RESET
|
||||
// TclEventType: RUN_MODIFY
|
||||
dismissDialog("Reset to Previous Step"); // bs (cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 483, 125); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 10, 276); // cd (w, cj)
|
||||
selectButton(PAResourceItoN.MainToolbarMgr_RUN, (String) null); // aw (f, cj)
|
||||
selectMenuItem(PAResourceCommand.PACommandNames_RUN_SYNTHESIS, "Run Synthesis"); // ac (cj)
|
||||
// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
|
||||
// am (cj): Save Project: addNotify
|
||||
selectButton(PAResourceQtoS.SaveProjectUtils_CANCEL, "Cancel"); // a (am)
|
||||
dismissDialog("Save Project"); // am (cj)
|
||||
selectButton(PAResourceCommand.PACommandNames_RUN_BITGEN, "run_bitstream"); // B (f, cj)
|
||||
// Run Command: PAResourceCommand.PACommandNames_RUN_BITGEN
|
||||
// am (cj): Save Project: addNotify
|
||||
selectButton(PAResourceQtoS.SaveProjectUtils_SAVE, "Save"); // a (am)
|
||||
// bs (cj): Save Constraints : addNotify
|
||||
// TclEventType: DG_GRAPH_STALE
|
||||
// 'cv' command handler elapsed time: 3 seconds
|
||||
dismissDialog("Save Project"); // am (cj)
|
||||
// TclEventType: DG_GRAPH_STALE
|
||||
dismissDialog("Save Constraints"); // bs (cj)
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: DG_ANALYSIS_MSG_RESET
|
||||
// Tcl Message: launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
// bs (cj): Generate Bitstream : addNotify
|
||||
// TclEventType: DG_GRAPH_GENERATED
|
||||
// TclEventType: RUN_LAUNCH
|
||||
// TclEventType: RUN_MODIFY
|
||||
// Tcl Message: [Tue Feb 26 19:10:53 2019] Launched impl_1... Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/runme.log
|
||||
dismissDialog("Generate Bitstream"); // bs (cj)
|
||||
// TclEventType: DG_ANALYSIS_MSG_RESET
|
||||
// TclEventType: DG_GRAPH_GENERATED
|
||||
// TclEventType: RUN_FAILED
|
||||
// TclEventType: RUN_COMPLETED
|
||||
// Elapsed time: 485 seconds
|
||||
selectButton(PAResourceItoN.MainToolbarMgr_RUN, (String) null); // aw (f, cj)
|
||||
selectButton(PAResourceCommand.PACommandNames_RUN_BITGEN, "run_bitstream"); // B (f, cj)
|
||||
// Run Command: PAResourceCommand.PACommandNames_RUN_BITGEN
|
||||
// bs (cj): Resetting Runs : addNotify
|
||||
// TclEventType: RUN_MODIFY
|
||||
// TclEventType: RUN_RESET
|
||||
// TclEventType: RUN_MODIFY
|
||||
// Tcl Message: reset_run synth_1
|
||||
dismissDialog("Resetting Runs"); // bs (cj)
|
||||
// TclEventType: RUN_LAUNCH
|
||||
// TclEventType: RUN_MODIFY
|
||||
// Tcl Message: launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
// Tcl Message: [Tue Feb 26 19:19:01 2019] Launched synth_1... Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1/runme.log [Tue Feb 26 19:19:01 2019] Launched impl_1... Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/runme.log
|
||||
// TclEventType: RUN_COMPLETED
|
||||
// WARNING: HTimer (ActiveMsgMonitor Process Messages Timer) is taking too long to process. Increasing delay to 2000 ms.
|
||||
// TclEventType: RUN_STEP_COMPLETED
|
||||
// TclEventType: RUN_COMPLETED
|
||||
// Elapsed time: 287 seconds
|
||||
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager]", 21, true); // u (O, cj) - Node
|
||||
// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER
|
||||
// Tcl Command: 'rdi::info_commands get_hw_probes'
|
||||
// Tcl Command: 'load_features labtools'
|
||||
// TclEventType: LOAD_FEATURE
|
||||
// bs (cj): Open Hardware Manager : addNotify
|
||||
// TclEventType: HW_SESSION_OPEN
|
||||
// Tcl Message: open_hw
|
||||
dismissDialog("Open Hardware Manager"); // bs (cj)
|
||||
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Open Target]", 22, false); // u (O, cj)
|
||||
// Run Command: PAResourceCommand.PACommandNames_OPEN_HW_TARGET
|
||||
selectMenuItem(PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET, "Auto Connect"); // ac (ai, cj)
|
||||
// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER
|
||||
// Tcl Command: 'rdi::info_commands get_hw_probes'
|
||||
// Run Command: PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET
|
||||
// Tcl Message: connect_hw_server
|
||||
// Tcl Message: INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
|
||||
// bs (cj): Auto Connect : addNotify
|
||||
// Tcl Message: INFO: [Labtools 27-2222] Launching hw_server...
|
||||
// Tcl Message: INFO: [Labtools 27-2221] Launch Output: ****** Xilinx hw_server v2017.4 **** Build date : Dec 15 2017-21:08:27 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
||||
// TclEventType: HW_SERVER_UPDATE
|
||||
// TclEventType: HW_TARGET_CHANGE
|
||||
// TclEventType: HW_TARGET_CLOSE
|
||||
// TclEventType: HW_DEVICE_CHANGE
|
||||
// TclEventType: HW_SYSMON_ADD
|
||||
// TclEventType: HW_TARGET_UPDATE
|
||||
// Tcl Message: open_hw_target
|
||||
// Tcl Message: INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A8B5DFA
|
||||
// [Engine Memory]: 1,321 MB (+565309kb) [01:31:32]
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 1,324 MB. GUI used memory: 51 MB. Current time: 2/26/19 7:23:58 PM CST
|
||||
// TclEventType: HW_DEVICE_CHANGE
|
||||
// Tcl Message: set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
// Tcl Message: current_hw_device [get_hw_devices xc7a100t_0]
|
||||
// TclEventType: HW_DEVICE_CHANGE
|
||||
// TclEventType: HW_SYSMON_CHANGE
|
||||
// TclEventType: HW_DEVICE_UPDATE
|
||||
// TclEventType: HW_DEVICE_CHANGE
|
||||
// Tcl Message: refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
// Tcl Message: INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
||||
dismissDialog("Auto Connect"); // bs (cj)
|
||||
// Elapsed time: 74 seconds
|
||||
selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 23, false); // u (O, cj)
|
||||
// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
|
||||
selectMenuItem((HResource) null, "xc7a100t_0"); // ac (ai, cj)
|
||||
// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER
|
||||
// Tcl Command: 'rdi::info_commands get_hw_probes'
|
||||
// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
|
||||
// bA (cj): Program Device: addNotify
|
||||
selectButton(PAResourceOtoP.ProgramFpgaDialog_PROGRAM, "Program"); // a (bA)
|
||||
// bs (cj): Program Device : addNotify
|
||||
dismissDialog("Program Device"); // bA (cj)
|
||||
// TclEventType: HW_DEVICE_CHANGE
|
||||
// Tcl Message: set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
// Tcl Message: set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
// TclEventType: HW_DEVICE_CHANGE
|
||||
// Tcl Message: set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
// Tcl Message: program_hw_devices [get_hw_devices xc7a100t_0]
|
||||
// TclEventType: HW_DEVICE_CHANGE
|
||||
// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH
|
||||
// TclEventType: HW_DEVICE_CHANGE
|
||||
// TclEventType: HW_SYSMON_CHANGE
|
||||
// TclEventType: HW_DEVICE_UPDATE
|
||||
// TclEventType: HW_DEVICE_CHANGE
|
||||
// TclEventType: HW_DEVICE_PROBES_CHANGE
|
||||
// TclEventType: DEBUG_PROBE_SET_CHANGE
|
||||
// TclEventType: HW_DEVICE_PROBES_CHANGE
|
||||
// Tcl Message: refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
// Tcl Message: INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
||||
// 'I' command handler elapsed time: 4 seconds
|
||||
dismissDialog("Program Device"); // bs (cj)
|
||||
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