diff --git a/hardware/ModelSim/USTCRVSoC.mpf b/hardware/ModelSim/USTCRVSoC.mpf index c1baacf..e1ddddc 100644 --- a/hardware/ModelSim/USTCRVSoC.mpf +++ b/hardware/ModelSim/USTCRVSoC.mpf @@ -449,49 +449,49 @@ Project_DefaultLib = work Project_SortMethod = unused Project_Files_Count = 22 Project_File_0 = ../RTL/dual_read_port_ram_32x32.sv -Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551597268 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551597268 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_1 = ../RTL/vga_char_86x32.sv -Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551536388 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1551536388 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_2 = ../RTL/ram128B.sv -Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1551597237 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1551597237 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_3 = ../RTL/uart_rx.sv -Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1549876350 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1549876350 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_4 = ../RTL/instr_rom.sv -Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1551094921 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551863110 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_5 = ../RTL/video_ram.sv -Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551536461 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551536461 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_6 = ../RTL/soc_top.sv -Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1551587626 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551587626 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_7 = ../RTL/core_ex_branch_judge.sv -Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1549876350 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1549876350 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_8 = ../RTL/ram.sv -Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551597245 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551597245 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_9 = ../RTL/ram_bus_wrapper.sv -Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1550846066 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1550846066 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_10 = ../RTL/core_bus_wrapper.sv -Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551591033 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551591033 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_11 = ../RTL/core_alu.sv -Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551588536 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551588536 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_12 = ../RTL/char8x16_rom.sv -Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551539060 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551539060 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_13 = ../RTL/core_top.sv -Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1551597558 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551597558 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_14 = ../RTL/soc_top_tb.sv -Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551596984 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551861246 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_15 = ../RTL/user_uart_tx.sv -Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551512538 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_16 = ../RTL/core_regfile.sv -Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551587650 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_17 = ../RTL/uart_tx_line.sv -Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1551092170 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551512538 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_16 = ../RTL/uart_tx_line.sv +Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1551092170 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_17 = ../RTL/core_regfile.sv +Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551587650 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_18 = ../RTL/isp_uart.sv -Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1551102643 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1551102643 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_19 = ../RTL/core_id_stage.sv -Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551588579 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_20 = ../RTL/naive_bus_router.sv -Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1549876350 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_21 = ../RTL/naive_bus.sv -Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1549876350 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551588579 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_20 = ../RTL/naive_bus.sv +Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1549876350 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_21 = ../RTL/naive_bus_router.sv +Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1549876350 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 diff --git a/hardware/ModelSim/vsim.wlf b/hardware/ModelSim/vsim.wlf new file mode 100644 index 0000000..56804ac Binary files /dev/null and b/hardware/ModelSim/vsim.wlf differ diff --git a/hardware/ModelSim/work/_info b/hardware/ModelSim/work/_info index a10f7c8..9cb7727 100644 --- a/hardware/ModelSim/work/_info +++ b/hardware/ModelSim/work/_info @@ -20,7 +20,7 @@ r1 31 Z11 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv| Z12 o-work work -sv -O0 -Z13 !s108 1551600111.448000 +Z13 !s108 1551863115.997000 Z14 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv| !i10b 1 !s85 0 @@ -42,7 +42,7 @@ r1 31 Z22 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv| R12 -Z23 !s108 1551600110.141000 +Z23 !s108 1551863114.690000 Z24 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv| !i10b 1 !s85 0 @@ -64,7 +64,7 @@ r1 31 Z32 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv| R12 -Z33 !s108 1551600110.207000 +Z33 !s108 1551863114.765000 Z34 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv| !i10b 1 !s85 0 @@ -86,7 +86,7 @@ r1 31 Z42 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv| R12 -Z43 !s108 1551600110.281000 +Z43 !s108 1551863114.833000 Z44 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv| !i10b 1 !s85 0 @@ -108,7 +108,7 @@ r1 31 Z52 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv| R12 -Z53 !s108 1551600110.351000 +Z53 !s108 1551863114.900000 Z54 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv| !i10b 1 !s85 0 @@ -130,7 +130,7 @@ r1 31 Z62 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv| R12 -Z63 !s108 1551600110.426000 +Z63 !s108 1551863114.978000 Z64 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv| !i10b 1 !s85 0 @@ -152,7 +152,7 @@ r1 31 Z72 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv| R12 -Z73 !s108 1551600110.497000 +Z73 !s108 1551863115.052000 Z74 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv| !i10b 1 !s85 0 @@ -174,29 +174,29 @@ R10 r1 !s85 0 31 -!s108 1551600111.665000 +!s108 1551863116.221000 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv| Z82 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv| !s101 -O0 R12 vinstr_rom R1 -Z83 !s100 Bd]Z1a^3]kD30E<26M`Lm1 -Z84 IOc1Uo_kS08]?1_CKOHHU?0 -Z85 Vg27TzclZ3S3@lBLMlA`?L1 -Z86 !s105 instr_rom_sv_unit +Z83 I0[kRSH:VXl_HDnGJiGS5]3 +Z84 Vg27TzclZ3S3@lBLMlA`?L1 +Z85 !s105 instr_rom_sv_unit S1 R6 -Z87 w1551094921 -Z88 8E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv -Z89 FE:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv +Z86 w1551863110 +Z87 8E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv +Z88 FE:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv L0 1 R10 r1 31 -Z90 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv| +Z89 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv| R12 -Z91 !s108 1551600110.571000 +Z90 !s100 m@TEV9E3O2B7:E0R:[VXF3 +Z91 !s108 1551863115.129000 Z92 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv| !i10b 1 !s85 0 @@ -218,7 +218,7 @@ r1 31 Z100 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv| R12 -Z101 !s108 1551600110.643000 +Z101 !s108 1551863115.210000 Z102 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv| !i10b 1 !s85 0 @@ -240,7 +240,7 @@ r1 31 Z109 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv| R12 -Z110 !s108 1551600110.715000 +Z110 !s108 1551863115.283000 Z111 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv| !i10b 1 !s85 0 @@ -262,7 +262,7 @@ r1 31 Z118 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv| R12 -Z119 !s108 1551600110.779000 +Z119 !s108 1551863115.349000 Z120 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv| !i10b 1 !s85 0 @@ -284,7 +284,7 @@ r1 31 Z128 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv| R12 -Z129 !s108 1551600110.858000 +Z129 !s108 1551863115.424000 Z130 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv| !i10b 1 !s85 0 @@ -307,7 +307,7 @@ r1 Z138 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv| R12 Z139 nram128@b -Z140 !s108 1551600111.520000 +Z140 !s108 1551863116.071000 Z141 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv| !i10b 1 !s85 0 @@ -329,7 +329,7 @@ r1 31 Z149 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv| R12 -Z150 !s108 1551600110.934000 +Z150 !s108 1551863115.494000 Z151 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv| !i10b 1 !s85 0 @@ -351,20 +351,20 @@ r1 31 Z159 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv| R12 -Z160 !s108 1551600111.003000 +Z160 !s108 1551863115.565000 Z161 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv| !i10b 1 !s85 0 !s101 -O0 vsoc_top_tb R1 -Z162 !s100 G9Pel5zad59i52f<6jYFNl[UE2 +Z163 I7hf=@mlD?E>:AKDSDL2O]1 Z164 VkLTgIQbfzI]@>Jm[T?T@F0 Z165 !s105 soc_top_tb_sv_unit S1 R6 -Z166 w1551596984 +Z166 w1551861246 Z167 8E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv Z168 FE:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv L0 1 @@ -373,7 +373,7 @@ r1 31 Z169 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv| R12 -Z170 !s108 1551600111.084000 +Z170 !s108 1551863115.642000 Z171 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv| !i10b 1 !s85 0 @@ -395,7 +395,7 @@ r1 31 Z178 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv| R12 -Z179 !s108 1551600111.160000 +Z179 !s108 1551863115.708000 Z180 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv| !i10b 1 !s85 0 @@ -417,7 +417,7 @@ r1 31 Z188 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv| R12 -Z189 !s108 1551600111.229000 +Z189 !s108 1551863115.776000 Z190 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv| !i10b 1 !s85 0 @@ -439,7 +439,7 @@ r1 31 Z198 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv| R12 -Z199 !s108 1551600111.301000 +Z199 !s108 1551863115.848000 Z200 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv| !i10b 1 !s85 0 @@ -485,7 +485,7 @@ Z219 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ R12 !i10b 1 !s85 0 -Z220 !s108 1551600111.587000 +Z220 !s108 1551863116.142000 Z221 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv| !s101 -O0 vvgaChar98x36 @@ -528,7 +528,7 @@ r1 31 R211 R12 -Z230 !s108 1551600111.371000 +Z230 !s108 1551863115.923000 R210 !i10b 1 !s85 0 diff --git a/hardware/Quartus/DE0Nano_USTCRVSoC/DE0Nano_USTCRVSoC.qsf b/hardware/Quartus/DE0Nano_USTCRVSoC/DE0Nano_USTCRVSoC.qsf index 9e98411..802cdc1 100644 --- a/hardware/Quartus/DE0Nano_USTCRVSoC/DE0Nano_USTCRVSoC.qsf +++ b/hardware/Quartus/DE0Nano_USTCRVSoC/DE0Nano_USTCRVSoC.qsf @@ -279,4 +279,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/dual_read_port_ram_32x3 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name FLOW_DISABLE_ASSEMBLER ON +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/hardware/Quartus/DE0Nano_USTCRVSoC/output_files/DE0Nano_USTCRVSoC.jdi b/hardware/Quartus/DE0Nano_USTCRVSoC/output_files/DE0Nano_USTCRVSoC.jdi index 95b8c73..ffc0d8c 100644 --- a/hardware/Quartus/DE0Nano_USTCRVSoC/output_files/DE0Nano_USTCRVSoC.jdi +++ b/hardware/Quartus/DE0Nano_USTCRVSoC/output_files/DE0Nano_USTCRVSoC.jdi @@ -1,6 +1,6 @@ - + diff --git a/hardware/Quartus/DE0Nano_USTCRVSoC/output_files/DE0Nano_USTCRVSoC.sof b/hardware/Quartus/DE0Nano_USTCRVSoC/output_files/DE0Nano_USTCRVSoC.sof index b2ac750..22bba42 100644 Binary files a/hardware/Quartus/DE0Nano_USTCRVSoC/output_files/DE0Nano_USTCRVSoC.sof and b/hardware/Quartus/DE0Nano_USTCRVSoC/output_files/DE0Nano_USTCRVSoC.sof differ diff --git a/hardware/RTL/instr_rom.sv b/hardware/RTL/instr_rom.sv index 747f000..4d9f6b5 100644 --- a/hardware/RTL/instr_rom.sv +++ b/hardware/RTL/instr_rom.sv @@ -2,26 +2,89 @@ module instr_rom( input logic clk, rst_n, naive_bus.slave bus ); -localparam INSTR_CNT = 30'd18; +localparam INSTR_CNT = 30'd81; wire [0:INSTR_CNT-1] [31:0] instr_rom_cell = { - 32'h000062b3, // 0x00000000 - 32'h000302b7, // 0x00000004 - 32'h06806313, // 0x00000008 - 32'h00628023, // 0x0000000c - 32'h06506313, // 0x00000010 - 32'h00628023, // 0x00000014 - 32'h06c06313, // 0x00000018 - 32'h00628023, // 0x0000001c - 32'h06c06313, // 0x00000020 - 32'h00628023, // 0x00000024 - 32'h06f06313, // 0x00000028 - 32'h00628023, // 0x0000002c - 32'h00a06313, // 0x00000030 - 32'h00628023, // 0x00000034 - 32'h00c003b7, // 0x00000038 - 32'hfff38393, // 0x0000003c - 32'hfe039ee3, // 0x00000040 - 32'hfc5ff06f // 0x00000044 + 32'h00010537, // 0x00000000 + 32'h40050113, // 0x00000004 + 32'h00050513, // 0x00000008 + 32'h00200293, // 0x0000000c + 32'h00552023, // 0x00000010 + 32'h00100293, // 0x00000014 + 32'h00552223, // 0x00000018 + 32'h00100293, // 0x0000001c + 32'h00552423, // 0x00000020 + 32'h00000593, // 0x00000024 + 32'h00800613, // 0x00000028 + 32'h00006f33, // 0x0000002c + 32'h020000ef, // 0x00000030 + 32'h00030fb7, // 0x00000034 + 32'h0fc06f13, // 0x00000038 + 32'h01ef8023, // 0x0000003c + 32'h00c003b7, // 0x00000040 + 32'hfff38393, // 0x00000044 + 32'hfe039ee3, // 0x00000048 + 32'hfb5ff06f, // 0x0000004c + 32'h0ec5d863, // 0x00000050 + 32'h0005e333, // 0x00000054 + 32'h000663b3, // 0x00000058 + 32'h006502b3, // 0x0000005c + 32'h0002a283, // 0x00000060 + 32'h04735463, // 0x00000064 + 32'h00750e33, // 0x00000068 + 32'h000e2e03, // 0x0000006c + 32'h00735863, // 0x00000070 + 32'h005e4663, // 0x00000074 + 32'hffc38393, // 0x00000078 + 32'hfedff06f, // 0x0000007c + 32'h00650eb3, // 0x00000080 + 32'h01cea023, // 0x00000084 + 32'h00650e33, // 0x00000088 + 32'h000e2e03, // 0x0000008c + 32'h00735863, // 0x00000090 + 32'h01c2c663, // 0x00000094 + 32'h00430313, // 0x00000098 + 32'hfedff06f, // 0x0000009c + 32'h00750eb3, // 0x000000a0 + 32'h01cea023, // 0x000000a4 + 32'hfbdff06f, // 0x000000a8 + 32'h00650eb3, // 0x000000ac + 32'h005ea023, // 0x000000b0 + 32'hffc10113, // 0x000000b4 + 32'h00112023, // 0x000000b8 + 32'hffc10113, // 0x000000bc + 32'h00b12023, // 0x000000c0 + 32'hffc10113, // 0x000000c4 + 32'h00c12023, // 0x000000c8 + 32'hffc10113, // 0x000000cc + 32'h00612023, // 0x000000d0 + 32'hffc30613, // 0x000000d4 + 32'hf79ff0ef, // 0x000000d8 + 32'h00012303, // 0x000000dc + 32'h00410113, // 0x000000e0 + 32'h00012603, // 0x000000e4 + 32'h00410113, // 0x000000e8 + 32'h00012583, // 0x000000ec + 32'h00410113, // 0x000000f0 + 32'h00012083, // 0x000000f4 + 32'h00410113, // 0x000000f8 + 32'hffc10113, // 0x000000fc + 32'h00112023, // 0x00000100 + 32'hffc10113, // 0x00000104 + 32'h00b12023, // 0x00000108 + 32'hffc10113, // 0x0000010c + 32'h00c12023, // 0x00000110 + 32'hffc10113, // 0x00000114 + 32'h00612023, // 0x00000118 + 32'h00430593, // 0x0000011c + 32'h00012303, // 0x00000120 + 32'h00410113, // 0x00000124 + 32'h00012603, // 0x00000128 + 32'h00410113, // 0x0000012c + 32'h00012583, // 0x00000130 + 32'h00410113, // 0x00000134 + 32'h00012083, // 0x00000138 + 32'h00410113, // 0x0000013c + 32'h00008067 // 0x00000140 }; logic [29:0] cell_rd_addr; diff --git a/hardware/RTL/soc_top_tb.sv b/hardware/RTL/soc_top_tb.sv index 8790e61..d66f579 100644 --- a/hardware/RTL/soc_top_tb.sv +++ b/hardware/RTL/soc_top_tb.sv @@ -18,6 +18,6 @@ soc_top soc_inst( .vga_blue ( vga_pixel[0] ) ); -initial #10000 $stop; +initial #1000 $stop; endmodule diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/gui_handlers.wdf b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/gui_handlers.wdf index 88f59aa..eb6b1ff 100644 --- a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/gui_handlers.wdf +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/gui_handlers.wdf @@ -2,6 +2,7 @@ version:1 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a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/java_command_handlers.wdf +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/java_command_handlers.wdf @@ -1,14 +1,14 @@ version:1 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:37:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:36:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:38:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f726576696577:31:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:31:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:35:00:00 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a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/webtalk_pa.xml +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -18,15 +18,15 @@ This means code written to parse this file will need to be revisited each subseq - + - + - - - + + + @@ -41,6 +41,7 @@ This means code written to parse this file will need to be revisited each subseq + @@ -48,8 +49,9 @@ This means code written to parse this file will need to be revisited each subseq + - + @@ -68,7 +70,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -81,14 +83,14 @@ This means code written to parse this file will need to be revisited each subseq - + - - + + @@ -101,15 +103,15 @@ This means code written to parse this file will need to be revisited each subseq - + - + - +
diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.jou b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.jou index a3e9a8d..27c4ccb 100644 --- a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.jou +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.jou @@ -2,28 +2,16 @@ # Vivado v2017.4 (64-bit) # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 -# Start of session at: Sun Mar 3 14:15:36 2019 -# Process ID: 16476 +# Start of session at: Tue Mar 5 19:07:42 2019 +# Process ID: 4532 # Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4 -# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent10728 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent12668 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr # Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log # Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou #----------------------------------------------------------- start_gui open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr update_compile_order -fileset sources_1 -add_files -norecurse {E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv} -update_compile_order -fileset sources_1 -export_ip_user_files -of_objects [get_files E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv] -no_script -reset -force -quiet -remove_files E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv -reset_run synth_1 -launch_runs synth_1 -jobs 8 -wait_on_run synth_1 -open_run synth_1 -name synth_1 -launch_runs impl_1 -jobs 8 -wait_on_run impl_1 -launch_runs impl_1 -to_step write_bitstream -jobs 8 -wait_on_run impl_1 open_hw connect_hw_server open_hw_target diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado_16476.backup.jou b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado_16476.backup.jou new file mode 100644 index 0000000..a3e9a8d --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado_16476.backup.jou @@ -0,0 +1,37 @@ +#----------------------------------------------------------- +# Vivado v2017.4 (64-bit) +# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 +# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 +# Start of session at: Sun Mar 3 14:15:36 2019 +# Process ID: 16476 +# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent10728 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr +# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log +# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou +#----------------------------------------------------------- +start_gui +open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr +update_compile_order -fileset sources_1 +add_files -norecurse {E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv} +update_compile_order -fileset sources_1 +export_ip_user_files -of_objects [get_files E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv] -no_script -reset -force -quiet +remove_files E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv +reset_run synth_1 +launch_runs synth_1 -jobs 8 +wait_on_run synth_1 +open_run synth_1 -name synth_1 +launch_runs impl_1 -jobs 8 +wait_on_run impl_1 +launch_runs impl_1 -to_step write_bitstream -jobs 8 +wait_on_run impl_1 +open_hw +connect_hw_server +open_hw_target +set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0] +current_hw_device [get_hw_devices xc7a100t_0] +refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0] +set_property PROBES.FILE {} [get_hw_devices xc7a100t_0] +set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0] +set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0] +program_hw_devices [get_hw_devices xc7a100t_0] +refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0] diff --git a/software/asm-code/load_store.S b/software/asm-code/basic-test/load_store.S similarity index 100% rename from software/asm-code/load_store.S rename to software/asm-code/basic-test/load_store.S diff --git a/software/asm-code/test_auipc.S b/software/asm-code/basic-test/test_auipc.S similarity index 100% rename from software/asm-code/test_auipc.S rename to software/asm-code/basic-test/test_auipc.S diff --git a/software/asm-code/calculation-test/Fibonacci.S b/software/asm-code/calculation-test/Fibonacci.S new file mode 100644 index 0000000..b897f3a --- /dev/null +++ b/software/asm-code/calculation-test/Fibonacci.S @@ -0,0 +1,62 @@ +# 概述：递归计算斐波那契数列的第n个数 +# Author: WangXuan +# +# 系统要求：1、具有一个大小至少为0x400 Byte的数据RAM （该程序中，其高地址用作栈） +# 2、请根据实际情况将a0设置为你的DataRam的地址，例如我的SoC DataRam起始地址为0x00010000，则我第一个指令是lui sp, 0x00010 +# + + + +.org 0x0 + .global _start +_start: + lui a0, 0x00010 # 设置DataRam的起始地址为0x00010000，也用作被排序数组的起始地址是，即DataRam的起始地址 + ori sp, a0, 0x400 # 为栈分配0x400Byte的空间 + + xori t0, zero, 8 # t0 = 8 + jal ra, Fibonacci # 计算 fib(8) = 34 = 0x22 + sw t1, (a0) # 计算结果放在DataRam的首地址 + +infinity_loop: + jal zero, infinity_loop # 排序结束，死循环 + + + +Fibonacci: # 递归计算斐波那契数列的第n项， + # n放在t0寄存器中 + # 结果放在t1寄存器中 + # 使用ra作为返回地址，并使用堆栈，堆栈指针为sp + + ori t4, zero, 3 # t4 = 3 + bgeu t0, t4, tag # if t0>=t4(3), jmp to tag + ori t1, t0, 0 # t1 = t0 + jalr zero, ra, 0 # pc = ra + +tag: + addi sp, sp, -4 # sp-=4 # push ra to stack + sw ra, (sp) # mem[sp] = ra + + addi t0, t0, -1 # t0-=1 + addi sp, sp, -4 # sp-=4 # push t0 to stack + sw t0, (sp) # mem[sp] = t0 + + jal ra, Fibonacci # 计算 Fib(n-1) + + lw t0, 0(sp) # t0=mem[sp] # pop t0 from stack + addi t0, t0, -1 # t0-=1 + addi sp, sp, 4 # sp+=4 + + + addi sp, sp, -4 # sp-=4 # push t1 to stack + sw t1, (sp) # mem[sp] = t1 + jal ra, Fibonacci # 计算 Fib(n-2) + lw t2, 0(sp) # ra=mem[sp] # pop t2 from stack + addi sp, sp, 4 # sp+=4 + add t1, t1, t2 # t1+=t2 + + lw ra, 0(sp) # ra=mem[sp] # pop ra from stack + addi sp, sp, 4 # sp+=4 + + jalr zero, ra,0 # pc = ra + + \ No newline at end of file diff --git a/software/asm-code/calculation-test/Number2Ascii.S b/software/asm-code/calculation-test/Number2Ascii.S new file mode 100644 index 0000000..a7dcec6 --- /dev/null +++ b/software/asm-code/calculation-test/Number2Ascii.S @@ -0,0 +1,71 @@ +# 概述：数字转十进制ASCII码 +# Author: WangXuan +# +# 系统要求：1、具有一个数据RAM +# 2、测试该代码时，不需要初始化DataRam，只需要将指令流烧入InstrRam。 +# 3、请根据实际情况将a0设置为你的DataRam的地址，例如我的SoC 显存起始地址为0x00020000，则我将计算结果写入了0x00020000，在VGA上会显示转化之后的ASCII字符 +# + + +.org 0x0 + .global _start +_start: + + ori a0, zero, 1395 # a0 = 1395 + add a0, a0 , a0 # a0 = 2790 + add a0, a0 , a0 # a0 = 5580 + jal ra, Number2DecimalAscii # 调用函数Number2DecimalAscii计算 a0 的十进制ASCII，结果应该是 0x30383535，存在 a0 里 + lui t0, 0x00020 # t0 = 0x00020000 + sw a0, 4(t0) # a0写入(t0) （计算结果写入显存RAM） +infinity_loop: + jal zero, infinity_loop # 死循环 + + +Number2DecimalAscii: + # 函数:Number2DecimalAscii：计算a0里低13位二进制数对应的十进制的ASCII码，存放在a0里 + # 例: a0=0x12345678，其低13位为0x1678，即5752 + # 则调用该函数后 a0=0x32353735，因为0x32, 0x35, 0x37, 0x35分别为2 5 7 5 的ASCII码 + # 之所以使用低13位，因为13位二进制数取值范围位0~8191，不会超过4位十进制数 + # 改变数据RAM： 无 + # 改变的寄存器：a0, t0, t1, t2 + # 调用方法：使用 jal ra, Number2DecimalAscii 指令调用，因为返回时需要用到 ra 寄存器作为返回地址 + lui t0, 0x01fff # t0 = 0x01fff000 + srl t0, t0 , 12 # t0 = 0x00001fff + and t0, a0 , t0 # t0 = t0 & a0 + lui a0, 0x30303 # a0 = 0x30303000 + ori a0, a0 , 0x030 # a0 = 0x30303030 + + ori t1, zero, 1000 # t1 = 1000 + thousand: + bltu t0, t1 , thousand_next # if t0<1000 jump to thousand_next + addi t0, t0 , -1000 # t0 -= 1000 + addi a0, a0 , 0x1 # a0 += 0x00000001 + jal zero, thousand # jump to thousand + thousand_next: + + ori t1, zero, 100 # t1 = 100 + hundred: + bltu t0, t1 , hundred_next # if t0<100 jump to hundred_next + addi t0, t0 , -100 # t0 -= 100 + addi a0, a0 , 0x100 # a0 += 0x00000100 + jal zero, hundred + hundred_next: + + lui t2, 0x00010 # t2 = 0x00010000 + ori t1, zero, 10 # t1 = 10 + ten: + bltu t0, t1 , ten_next # if t0<10 jump to ten_next + addi t0, t0 , -10 # t0 -= 10 + add a0, a0 , t2 # a0 += 0x00010000 + jal zero, ten + ten_next: + + lui t2, 0x01000 # t2 = 0x01000000 + ori t1, zero, 1 # t1 = 1 + one: + bltu t0, t1 , one_next # if t0<1 jump to one_next + addi t0, t0 , -1 # t0 -= 1 + add a0, a0 , t2 # a0 += 0x01000000 + jal zero, one + one_next: + jalr zero, ra, 0 diff --git a/software/asm-code/calculation-test/QuickSort.S b/software/asm-code/calculation-test/QuickSort.S new file mode 100644 index 0000000..b0c5709 --- /dev/null +++ b/software/asm-code/calculation-test/QuickSort.S @@ -0,0 +1,156 @@ +# 概述：对数组进行原地快速排序 +# Author: WangXuan +# +# 系统要求：1、具有一个大小至少为0x400 Byte的数据RAM （该程序中，其高地址用作栈，低地址用作被排序的数组） +# 2、测试该代码时，不需要初始化DataRam，只需要将指令流烧入InstrRam。因为有一系列指令去准备被排序的数组。 +# 3、请根据实际情况将a0设置为你的DataRam的地址，例如我的SoC DataRam起始地址为0x00010000，则第一条指令就是 lui a0, 0x00010 +# + + +.org 0x0 + .global _start +_start: + +main: # main函数开始，在DataRam里初始化一段数据，然后调用QuickSort进行排序，排序后进入死循环。请使用仿真或UART调试器查看排序后的数据 + + lui a0, 0x00010 # 设置DataRam的起始地址为0x00010000，也用作被排序数组的起始地址是，即DataRam的起始地址 + + addi sp, a0 , 0x400 # 设置栈顶指针 + + addi t0, zero, 0x03 # 用一系列指令向a0里写入被排序的数组，可以是负数 + sw t0, 0(a0) + addi t0, zero, 0x01 + sw t0, 4(a0) + addi t0, zero, 0x04 + sw t0, 8(a0) + addi t0, zero, -0x01 + sw t0, 12(a0) + addi t0, zero, 0x05 + sw t0, 16(a0) + addi t0, zero, -0x09 + sw t0, 20(a0) + addi t0, zero, 0x02 + sw t0, 24(a0) + addi t0, zero, 0x06 + sw t0, 28(a0) + addi t0, zero, -0x06 + sw t0, 32(a0) + addi t0, zero, 0x05 + sw t0, 36(a0) + addi t0, zero, 0x06 + sw t0, 40(a0) + addi t0, zero, -0x05 + sw t0, 44(a0) + addi t0, zero, 0x07 + sw t0, 48(a0) + + addi a1, zero, 0 # 准备参数 + addi a2, zero, 48 + jal ra , QuickSort # 开始排序 +infinity_loop: + jal zero, infinity_loop # 排序结束，死循环 + +QuickSort: + # 函数:QuickSort：以a0为基地址的原地升序快速排序，a1是start即开始下标，a2是end即结束下标 + # 例: a0=0x00000100，a1=0, a2=32，则计算从0x00000100开始的32个4Byte数的快速排序 + # 注: 以有符号数为比较标准。例如0xffffffff应该排在0x00000001前面，因为0xffffffff代表-1，比1要小 + # 之所以使用低13位，因为13位二进制数取值范围位0~8191，不会超过4位十进制数 + # 改变数据RAM： 除了被排序的数组外，还使用了以sp寄存器为栈顶指针的栈。使用栈的大小根据排序长度而不同，调用前合理设置sp的值以防爆栈 + # 改变的寄存器： t0, t1, t2, t3, t4 + + bge a1, a2, QuickSortReturn # if a1>=a2, end<=start, jump to return + or t1, a1, zero # t1=i=a1=start + or t2, a2, zero # t2=j=a2=end + add t0, a0, t1 # + lw t0, (t0) # t0=key=lst[start] + + PartationStart: + PartationFirstStart: # start of for loop + add t3, a0, t2 # + lw t3, (t3) # t3=lst[j] + bge t1, t2, PartationFirstEnd # if i>=j, branch to next step + blt t3, t0, PartationFirstEnd # if lst[j]=j, branch to next step + blt t0, t3, PartationSecondEnd # if keystart){ +# int i = start,j = end,key = lst[start]; +# while(i < j){ +# for (;i < j && key <= lst[j];j--); +# lst[i] = lst[j]; +# for (;i < j && key >= lst[i];i++); +# lst[j] = lst[i]; +# } +# lst[i] = key; +# QuickSort(lst, start, i - 1); +# QuickSort(lst, i + 1, end); +# } +# } +# +# + \ No newline at end of file diff --git a/software/asm-code/fibonacci_recursive.S b/software/asm-code/fibonacci_recursive.S deleted file mode 100644 index 1974777..0000000 --- a/software/asm-code/fibonacci_recursive.S +++ /dev/null @@ -1,59 +0,0 @@ -.org 0x0 - .global _start -_start: - - lui sp, 0x00020 - ori sp, sp, 0x400 # stack pointer=0x400, stack size = 256 dwords - - xori t0, zero, 8 # t0 = 8 - jal ra, fibonacci_recursive # fib(8) = 34 = 0x22 - - jal zero, print_result # 跳到死循环打印程序，循环打印斐波那契计算结果，应该打印的是0x15 - -fibonacci_recursive: # 递归计算斐波那契数列的第n项， - # n放在t0寄存器中 - # 结果放在t1寄存器中 - # 使用ra作为返回地址，并使用堆栈，堆栈指针为sp - - ori a0, zero, 3 # a0 = 3 - bgeu t0, a0, tag # if t0>=a0(3), jmp to tag - ori t1, t0, 0 # t1 = t0 - jalr zero, ra, 0 # pc = ra - -tag: - addi sp, sp, -4 # sp-=4 # push ra to stack - sw ra, (sp) # mem[sp] = ra - - addi t0, t0, -1 # t0-=1 - addi sp, sp, -4 # sp-=4 # push t0 to stack - sw t0, (sp) # mem[sp] = t0 - - jal ra, fibonacci_recursive # fibonacci_recursive n-1 - - lw t0, 0(sp) # t0=mem[sp] # pop t0 from stack - addi t0, t0, -1 # t0-=1 - addi sp, sp, 4 # sp+=4 - - - addi sp, sp, -4 # sp-=4 # push t1 to stack - sw t1, (sp) # mem[sp] = t1 - jal ra, fibonacci_recursive # fibonacci_recursive n-2 - lw t2, 0(sp) # ra=mem[sp] # pop t2 from stack - addi sp, sp, 4 # sp+=4 - add t1, t1, t2 # t1+=t2 - - lw ra, 0(sp) # ra=mem[sp] # pop ra from stack - addi sp, sp, 4 # sp+=4 - - jalr zero, ra,0 # pc = ra - -print_result: # 延时循环打印斐波那契计算结果 - or t0, zero,zero # t0 清零 - lui t0, 0x00030 # t0 寄存器的高20bit=0x00020 - sb t1, (t0) # 计算完成，结果在t1中，用USER-UART打印出来 - lui t2, 0x00c00 # t2 = 0x00800000 -big_loop: - addi t2, t2, -1 # t2 = t2-1 - bne t2, zero, big_loop # if t2!=0, jmp to big_loop - jal zero, _start # 大循环结束，跳到开头t，重复计算 - \ No newline at end of file diff --git a/software/asm-code/fibonacci_recursive.sv b/software/asm-code/fibonacci_recursive.sv deleted file mode 100644 index babef58..0000000 --- a/software/asm-code/fibonacci_recursive.sv +++ /dev/null @@ -1,61 +0,0 @@ -module instr_rom( - input logic clk, rst_n, - naive_bus.slave bus -); -localparam INSTR_CNT = 30'd36; -wire [0:INSTR_CNT-1] [31:0] instr_rom_cell = { - 32'h12300013, // 0x00000000 - 32'h45600013, // 0x00000004 - 32'h00010137, // 0x00000008 - 32'h40016113, // 0x0000000c - 32'h00804293, // 0x00000010 - 32'h008000ef, // 0x00000014 - 32'h05c0006f, // 0x00000018 - 32'h00306513, // 0x0000001c - 32'h00a2f663, // 0x00000020 - 32'h0002e313, // 0x00000024 - 32'h00008067, // 0x00000028 - 32'hffc10113, // 0x0000002c - 32'h00112023, // 0x00000030 - 32'hfff28293, // 0x00000034 - 32'hffc10113, // 0x00000038 - 32'h00512023, // 0x0000003c - 32'hfddff0ef, // 0x00000040 - 32'h00012283, // 0x00000044 - 32'h00410113, // 0x00000048 - 32'hfff28293, // 0x0000004c - 32'hffc10113, // 0x00000050 - 32'h00612023, // 0x00000054 - 32'hfc5ff0ef, // 0x00000058 - 32'h00012383, // 0x0000005c - 32'h00410113, // 0x00000060 - 32'h00730333, // 0x00000064 - 32'h00012083, // 0x00000068 - 32'h00410113, // 0x0000006c - 32'h00008067, // 0x00000070 - 32'h000062b3, // 0x00000074 - 32'h000302b7, // 0x00000078 - 32'h00628023, // 0x0000007c - 32'h00c003b7, // 0x00000080 - 32'hfff38393, // 0x00000084 - 32'hfe039ee3, // 0x00000088 - 32'hfe9ff06f // 0x0000008c -}; - -logic [29:0] cell_rd_addr; - -assign bus.rd_gnt = bus.rd_req; -assign bus.wr_gnt = bus.wr_req; -assign cell_rd_addr = bus.rd_addr[31:2]; -always @ (posedge clk or negedge rst_n) - if(~rst_n) - bus.rd_data <= 0; - else begin - if(bus.rd_req) - bus.rd_data <= (cell_rd_addr>=INSTR_CNT) ? 0 : instr_rom_cell[cell_rd_addr]; - else - bus.rd_data <= 0; - end - -endmodule - diff --git a/software/asm-code/uart_print.S b/software/asm-code/io-test/uart_print.S similarity index 100% rename from software/asm-code/uart_print.S rename to software/asm-code/io-test/uart_print.S diff --git a/software/asm-code/vga_hello.S b/software/asm-code/io-test/vga_hello.S similarity index 100% rename from software/asm-code/vga_hello.S rename to software/asm-code/io-test/vga_hello.S