diff --git a/Quartus/DE0_Nano/db/DE0_Nano.cbx.xml b/Quartus/DE0_Nano/db/DE0_Nano.cbx.xml
deleted file mode 100644
index 939b463..0000000
--- a/Quartus/DE0_Nano/db/DE0_Nano.cbx.xml
+++ /dev/null
@@ -1,32 +0,0 @@
-
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diff --git a/Quartus/DE0_Nano/db/DE0_Nano.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/Quartus/DE0_Nano/db/DE0_Nano.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
deleted file mode 100644
index 7c23578..0000000
Binary files a/Quartus/DE0_Nano/db/DE0_Nano.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd and /dev/null differ
diff --git a/Quartus/DE0_Nano/db/DE0_Nano.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd b/Quartus/DE0_Nano/db/DE0_Nano.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd
deleted file mode 100644
index 9561e51..0000000
Binary files a/Quartus/DE0_Nano/db/DE0_Nano.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd and /dev/null differ
diff --git a/Quartus/DE0_Nano/db/DE0_Nano.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd b/Quartus/DE0_Nano/db/DE0_Nano.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd
deleted file mode 100644
index 9d29892..0000000
Binary files a/Quartus/DE0_Nano/db/DE0_Nano.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd and /dev/null differ
diff --git a/Quartus/DE0_Nano/db/DE0_Nano.hier_info b/Quartus/DE0_Nano/db/DE0_Nano.hier_info
deleted file mode 100644
index cebcee1..0000000
--- a/Quartus/DE0_Nano/db/DE0_Nano.hier_info
+++ /dev/null
@@ -1,343384 +0,0 @@
-|DE0_Nano_USTCRVSoC_top
-CLOCK_50 => CLOCK_50.IN1
-LED[0] <= flow[0].DB_MAX_OUTPUT_PORT_TYPE
-LED[1] <= flow[1].DB_MAX_OUTPUT_PORT_TYPE
-LED[2] <= flow[2].DB_MAX_OUTPUT_PORT_TYPE
-LED[3] <= flow[3].DB_MAX_OUTPUT_PORT_TYPE
-LED[4] <= GPIO_1[1]~direct.DB_MAX_OUTPUT_PORT_TYPE
-LED[5] <= GPIO_1_IN[1].DB_MAX_OUTPUT_PORT_TYPE
-LED[6] <= GPIO_1[0]~direct.DB_MAX_OUTPUT_PORT_TYPE
-LED[7] <= GPIO_1_IN[0].DB_MAX_OUTPUT_PORT_TYPE
-KEY[0] => ~NO_FANOUT~
-KEY[1] => ~NO_FANOUT~
-SW[0] => ~NO_FANOUT~
-SW[1] => ~NO_FANOUT~
-SW[2] => ~NO_FANOUT~
-SW[3] => ~NO_FANOUT~
-GPIO_0_IN[0] => ~NO_FANOUT~
-GPIO_0_IN[1] => ~NO_FANOUT~
-GPIO_0[0] <>
-GPIO_0[1] <>
-GPIO_0[2] <>
-GPIO_0[3] <>
-GPIO_0[4] <>
-GPIO_0[5] <>
-GPIO_0[6] <>
-GPIO_0[7] <>
-GPIO_0[8] <>
-GPIO_0[9] <>
-GPIO_0[10] <>
-GPIO_0[11] <>
-GPIO_0[12] <>
-GPIO_0[13] <>
-GPIO_0[14] <>
-GPIO_0[15] <>
-GPIO_0[16] <> soc_top:soc_inst.vga_pixel
-GPIO_0[17] <> soc_top:soc_inst.vga_pixel
-GPIO_0[18] <> soc_top:soc_inst.vga_pixel
-GPIO_0[19] <> soc_top:soc_inst.vga_pixel
-GPIO_0[20] <> soc_top:soc_inst.vga_pixel
-GPIO_0[21] <> soc_top:soc_inst.vga_pixel
-GPIO_0[22] <> soc_top:soc_inst.vga_pixel
-GPIO_0[23] <> soc_top:soc_inst.vga_pixel
-GPIO_0[24] <> soc_top:soc_inst.vga_pixel
-GPIO_0[25] <> soc_top:soc_inst.vga_pixel
-GPIO_0[26] <> soc_top:soc_inst.vga_pixel
-GPIO_0[27] <> soc_top:soc_inst.vga_pixel
-GPIO_0[28] <> soc_top:soc_inst.vga_pixel
-GPIO_0[29] <> soc_top:soc_inst.vga_pixel
-GPIO_0[30] <> soc_top:soc_inst.vga_pixel
-GPIO_0[31] <> soc_top:soc_inst.vga_pixel
-GPIO_0[32] <> soc_top:soc_inst.vga_vsync
-GPIO_0[33] <> soc_top:soc_inst.vga_hsync
-GPIO_1_IN[0] => GPIO_1_IN[0].IN1
-GPIO_1_IN[1] => GPIO_1_IN[1].IN1
-GPIO_1[0] <> soc_top:soc_inst.isp_uart_tx
-GPIO_1[1] <> soc_top:soc_inst.user_uart_tx
-GPIO_1[2] <>
-GPIO_1[3] <>
-GPIO_1[4] <>
-GPIO_1[5] <>
-GPIO_1[6] <>
-GPIO_1[7] <>
-GPIO_1[8] <>
-GPIO_1[9] <>
-GPIO_1[10] <>
-GPIO_1[11] <>
-GPIO_1[12] <>
-GPIO_1[13] <>
-GPIO_1[14] <>
-GPIO_1[15] <>
-GPIO_1[16] <>
-GPIO_1[17] <>
-GPIO_1[18] <>
-GPIO_1[19] <>
-GPIO_1[20] <>
-GPIO_1[21] <>
-GPIO_1[22] <>
-GPIO_1[23] <>
-GPIO_1[24] <>
-GPIO_1[25] <>
-GPIO_1[26] <>
-GPIO_1[27] <>
-GPIO_1[28] <>
-GPIO_1[29] <>
-GPIO_1[30] <>
-GPIO_1[31] <>
-GPIO_1[32] <>
-GPIO_1[33] <>
-ADC_CS_N <=
-ADC_SADDR <=
-ADC_SCLK <=
-ADC_SDAT => ~NO_FANOUT~
-G_SENSOR_CS_N <=
-G_SENSOR_INT => ~NO_FANOUT~
-I2C_SCLK <=
-I2C_SDAT <>
-DRAM_ADDR[0] <=
-DRAM_ADDR[1] <=
-DRAM_ADDR[2] <=
-DRAM_ADDR[3] <=
-DRAM_ADDR[4] <=
-DRAM_ADDR[5] <=
-DRAM_ADDR[6] <=
-DRAM_ADDR[7] <=
-DRAM_ADDR[8] <=
-DRAM_ADDR[9] <=
-DRAM_ADDR[10] <=
-DRAM_ADDR[11] <=
-DRAM_ADDR[12] <=
-DRAM_BA[0] <=
-DRAM_BA[1] <=
-DRAM_CAS_N <=
-DRAM_CKE <=
-DRAM_CLK <=
-DRAM_CS_N <=
-DRAM_RAS_N <=
-DRAM_WE_N <=
-DRAM_DQ[0] <>
-DRAM_DQ[1] <>
-DRAM_DQ[2] <>
-DRAM_DQ[3] <>
-DRAM_DQ[4] <>
-DRAM_DQ[5] <>
-DRAM_DQ[6] <>
-DRAM_DQ[7] <>
-DRAM_DQ[8] <>
-DRAM_DQ[9] <>
-DRAM_DQ[10] <>
-DRAM_DQ[11] <>
-DRAM_DQ[12] <>
-DRAM_DQ[13] <>
-DRAM_DQ[14] <>
-DRAM_DQ[15] <>
-DRAM_DQM[0] <=
-DRAM_DQM[1] <=
-
-
-|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst
-clk => isp_uart:isp_uart_inst.clk
-clk => core_top:core_top_inst.clk
-clk => instr_rom:instr_rom_inst.clk
-clk => ram_bus_wrapper:instr_ram_inst.clk
-clk => ram_bus_wrapper:data_ram_inst.clk
-clk => video_ram:video_ram_inst.clk
-clk => user_uart_tx:user_uart_tx_inst.clk
-clk => naive_bus_router:soc_bus_router_inst.clk
-rst_n <= isp_uart:isp_uart_inst.o_rst_n
-isp_uart_rx => isp_uart:isp_uart_inst.i_uart_rx
-isp_uart_tx <= isp_uart:isp_uart_inst.o_uart_tx
-user_uart_rx => ~NO_FANOUT~
-user_uart_tx <= user_uart_tx:user_uart_tx_inst.o_uart_tx
-vga_hsync <= video_ram:video_ram_inst.o_hsync
-vga_vsync <= video_ram:video_ram_inst.o_vsync
-vga_pixel[0] <= video_ram:video_ram_inst.o_pixel[0]
-vga_pixel[1] <= video_ram:video_ram_inst.o_pixel[1]
-vga_pixel[2] <= video_ram:video_ram_inst.o_pixel[2]
-vga_pixel[3] <= video_ram:video_ram_inst.o_pixel[3]
-vga_pixel[4] <= video_ram:video_ram_inst.o_pixel[4]
-vga_pixel[5] <= video_ram:video_ram_inst.o_pixel[5]
-vga_pixel[6] <= video_ram:video_ram_inst.o_pixel[6]
-vga_pixel[7] <= video_ram:video_ram_inst.o_pixel[7]
-vga_pixel[8] <= video_ram:video_ram_inst.o_pixel[8]
-vga_pixel[9] <= video_ram:video_ram_inst.o_pixel[9]
-vga_pixel[10] <= video_ram:video_ram_inst.o_pixel[10]
-vga_pixel[11] <= video_ram:video_ram_inst.o_pixel[11]
-vga_pixel[12] <= video_ram:video_ram_inst.o_pixel[12]
-vga_pixel[13] <= video_ram:video_ram_inst.o_pixel[13]
-vga_pixel[14] <= video_ram:video_ram_inst.o_pixel[14]
-vga_pixel[15] <= video_ram:video_ram_inst.o_pixel[15]
-
-
-|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|naive_bus:bus_masters[2]
-naive_bus.wr_data[0] <>
-naive_bus.wr_data[1] <>
-naive_bus.wr_data[2] <>
-naive_bus.wr_data[3] <>
-naive_bus.wr_data[4] <>
-naive_bus.wr_data[5] <>
-naive_bus.wr_data[6] <>
-naive_bus.wr_data[7] <>
-naive_bus.wr_data[8] <>
-naive_bus.wr_data[9] <>
-naive_bus.wr_data[10] <>
-naive_bus.wr_data[11] <>
-naive_bus.wr_data[12] <>
-naive_bus.wr_data[13] <>
-naive_bus.wr_data[14] <>
-naive_bus.wr_data[15] <>
-naive_bus.wr_data[16] <>
-naive_bus.wr_data[17] <>
-naive_bus.wr_data[18] <>
-naive_bus.wr_data[19] <>
-naive_bus.wr_data[20] <>
-naive_bus.wr_data[21] <>
-naive_bus.wr_data[22] <>
-naive_bus.wr_data[23] <>
-naive_bus.wr_data[24] <>
-naive_bus.wr_data[25] <>
-naive_bus.wr_data[26] <>
-naive_bus.wr_data[27] <>
-naive_bus.wr_data[28] <>
-naive_bus.wr_data[29] <>
-naive_bus.wr_data[30] <>
-naive_bus.wr_data[31] <>
-naive_bus.wr_addr[0] <>
-naive_bus.wr_addr[1] <>
-naive_bus.wr_addr[2] <>
-naive_bus.wr_addr[3] <>
-naive_bus.wr_addr[4] <>
-naive_bus.wr_addr[5] <>
-naive_bus.wr_addr[6] <>
-naive_bus.wr_addr[7] <>
-naive_bus.wr_addr[8] <>
-naive_bus.wr_addr[9] <>
-naive_bus.wr_addr[10] <>
-naive_bus.wr_addr[11] <>
-naive_bus.wr_addr[12] <>
-naive_bus.wr_addr[13] <>
-naive_bus.wr_addr[14] <>
-naive_bus.wr_addr[15] <>
-naive_bus.wr_addr[16] <>
-naive_bus.wr_addr[17] <>
-naive_bus.wr_addr[18] <>
-naive_bus.wr_addr[19] <>
-naive_bus.wr_addr[20] <>
-naive_bus.wr_addr[21] <>
-naive_bus.wr_addr[22] <>
-naive_bus.wr_addr[23] <>
-naive_bus.wr_addr[24] <>
-naive_bus.wr_addr[25] <>
-naive_bus.wr_addr[26] <>
-naive_bus.wr_addr[27] <>
-naive_bus.wr_addr[28] <>
-naive_bus.wr_addr[29] <>
-naive_bus.wr_addr[30] <>
-naive_bus.wr_addr[31] <>
-naive_bus.wr_be[0] <>
-naive_bus.wr_be[1] <>
-naive_bus.wr_be[2] <>
-naive_bus.wr_be[3] <>
-naive_bus.wr_gnt <>
-naive_bus.wr_req <>
-naive_bus.rd_data[0] <>
-naive_bus.rd_data[1] <>
-naive_bus.rd_data[2] <>
-naive_bus.rd_data[3] <>
-naive_bus.rd_data[4] <>
-naive_bus.rd_data[5] <>
-naive_bus.rd_data[6] <>
-naive_bus.rd_data[7] <>
-naive_bus.rd_data[8] <>
-naive_bus.rd_data[9] <>
-naive_bus.rd_data[10] <>
-naive_bus.rd_data[11] <>
-naive_bus.rd_data[12] <>
-naive_bus.rd_data[13] <>
-naive_bus.rd_data[14] <>
-naive_bus.rd_data[15] <>
-naive_bus.rd_data[16] <>
-naive_bus.rd_data[17] <>
-naive_bus.rd_data[18] <>
-naive_bus.rd_data[19] <>
-naive_bus.rd_data[20] <>
-naive_bus.rd_data[21] <>
-naive_bus.rd_data[22] <>
-naive_bus.rd_data[23] <>
-naive_bus.rd_data[24] <>
-naive_bus.rd_data[25] <>
-naive_bus.rd_data[26] <>
-naive_bus.rd_data[27] <>
-naive_bus.rd_data[28] <>
-naive_bus.rd_data[29] <>
-naive_bus.rd_data[30] <>
-naive_bus.rd_data[31] <>
-naive_bus.rd_addr[0] <>
-naive_bus.rd_addr[1] <>
-naive_bus.rd_addr[2] <>
-naive_bus.rd_addr[3] <>
-naive_bus.rd_addr[4] <>
-naive_bus.rd_addr[5] <>
-naive_bus.rd_addr[6] <>
-naive_bus.rd_addr[7] <>
-naive_bus.rd_addr[8] <>
-naive_bus.rd_addr[9] <>
-naive_bus.rd_addr[10] <>
-naive_bus.rd_addr[11] <>
-naive_bus.rd_addr[12] <>
-naive_bus.rd_addr[13] <>
-naive_bus.rd_addr[14] <>
-naive_bus.rd_addr[15] <>
-naive_bus.rd_addr[16] <>
-naive_bus.rd_addr[17] <>
-naive_bus.rd_addr[18] <>
-naive_bus.rd_addr[19] <>
-naive_bus.rd_addr[20] <>
-naive_bus.rd_addr[21] <>
-naive_bus.rd_addr[22] <>
-naive_bus.rd_addr[23] <>
-naive_bus.rd_addr[24] <>
-naive_bus.rd_addr[25] <>
-naive_bus.rd_addr[26] <>
-naive_bus.rd_addr[27] <>
-naive_bus.rd_addr[28] <>
-naive_bus.rd_addr[29] <>
-naive_bus.rd_addr[30] <>
-naive_bus.rd_addr[31] <>
-naive_bus.rd_be[0] <>
-naive_bus.rd_be[1] <>
-naive_bus.rd_be[2] <>
-naive_bus.rd_be[3] <>
-naive_bus.rd_gnt <>
-naive_bus.rd_req <>
-
-
-|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|naive_bus:bus_masters[1]
-naive_bus.wr_data[0] <>
-naive_bus.wr_data[1] <>
-naive_bus.wr_data[2] <>
-naive_bus.wr_data[3] <>
-naive_bus.wr_data[4] <>
-naive_bus.wr_data[5] <>
-naive_bus.wr_data[6] <>
-naive_bus.wr_data[7] <>
-naive_bus.wr_data[8] <>
-naive_bus.wr_data[9] <>
-naive_bus.wr_data[10] <>
-naive_bus.wr_data[11] <>
-naive_bus.wr_data[12] <>
-naive_bus.wr_data[13] <>
-naive_bus.wr_data[14] <>
-naive_bus.wr_data[15] <>
-naive_bus.wr_data[16] <>
-naive_bus.wr_data[17] <>
-naive_bus.wr_data[18] <>
-naive_bus.wr_data[19] <>
-naive_bus.wr_data[20] <>
-naive_bus.wr_data[21] <>