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add USTCRVSoC-tool source files

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WangXuan95 2019-02-16 15:12:18 +08:00
parent ccb6d06344
commit 3c5624a703
27 changed files with 0 additions and 343517 deletions
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32
Quartus/DE0_Nano/db/DE0_Nano.cbx.xml
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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="DE0_Nano">
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|ram_bus_wrapper:data_ram_inst|ram:ram_block_inst_0|altsyncram:data_ram_cell[0][7]__2" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|ram_bus_wrapper:data_ram_inst|ram:ram_block_inst_1|altsyncram:data_ram_cell[0][7]__1" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|ram_bus_wrapper:instr_ram_inst|ram:ram_block_inst_2|altsyncram:data_ram_cell[0][7]__2" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|ram_bus_wrapper:instr_ram_inst|ram:ram_block_inst_3|altsyncram:data_ram_cell[0][7]__1" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|ram_bus_wrapper:data_ram_inst|ram:ram_block_inst_1|altsyncram:data_ram_cell[0][7]__2" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|ram_bus_wrapper:data_ram_inst|ram:ram_block_inst_2|altsyncram:data_ram_cell[0][7]__1" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|ram_bus_wrapper:instr_ram_inst|ram:ram_block_inst_3|altsyncram:data_ram_cell[0][7]__2" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|video_ram:video_ram_inst|ram:ram_block_inst_0|altsyncram:data_ram_cell[0][7]__1" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|ram_bus_wrapper:data_ram_inst|ram:ram_block_inst_2|altsyncram:data_ram_cell[0][7]__2" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|ram_bus_wrapper:data_ram_inst|ram:ram_block_inst_3|altsyncram:data_ram_cell[0][7]__1" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|video_ram:video_ram_inst|ram:ram_block_inst_0|altsyncram:data_ram_cell[0][7]__2" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|video_ram:video_ram_inst|ram:ram_block_inst_1|altsyncram:data_ram_cell[0][7]__1" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|video_ram:video_ram_inst|vgaChar98x36:vga_char_inst|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]" CBX_FILE_NAME="add_sub_kgh.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|ram_bus_wrapper:data_ram_inst|ram:ram_block_inst_0|altsyncram:data_ram_cell[0][7]__1" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|ram_bus_wrapper:data_ram_inst|ram:ram_block_inst_3|altsyncram:data_ram_cell[0][7]__2" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|ram_bus_wrapper:instr_ram_inst|ram:ram_block_inst_1|altsyncram:data_ram_cell[0][7]__2" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|ram_bus_wrapper:instr_ram_inst|ram:ram_block_inst_2|altsyncram:data_ram_cell[0][7]__1" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|video_ram:video_ram_inst|ram:ram_block_inst_1|altsyncram:data_ram_cell[0][7]__2" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|video_ram:video_ram_inst|ram:ram_block_inst_2|altsyncram:data_ram_cell[0][7]__1" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|video_ram:video_ram_inst|ram:ram_block_inst_2|altsyncram:data_ram_cell[0][7]__2" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|video_ram:video_ram_inst|ram:ram_block_inst_3|altsyncram:data_ram_cell[0][7]__1" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|ram_bus_wrapper:instr_ram_inst|ram:ram_block_inst_0|altsyncram:data_ram_cell[0][7]__1" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|user_uart_tx:user_uart_tx_inst|ram:ram_for_uart_tx_fifo_inst|altsyncram:data_ram_cell[0][7]__1" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|video_ram:video_ram_inst|ram:ram_block_inst_3|altsyncram:data_ram_cell[0][7]__2" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|ram_bus_wrapper:instr_ram_inst|ram:ram_block_inst_0|altsyncram:data_ram_cell[0][7]__2" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|ram_bus_wrapper:instr_ram_inst|ram:ram_block_inst_1|altsyncram:data_ram_cell[0][7]__1" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
<CBX_INST_ENTRY INSTANCE_NAME="|DE0_Nano_USTCRVSoC_top|soc_top:soc_inst|user_uart_tx:user_uart_tx_inst|ram:ram_for_uart_tx_fifo_inst|altsyncram:data_ram_cell[0][7]__2" CBX_FILE_NAME="altsyncram_g2h1.tdf"/>
</PROJECT>
</LOG_ROOT>

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Quartus/DE0_Nano/db/DE0_Nano.hier_info
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Quartus/DE0_Nano/db/DE0_Nano.lpc.txt
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+--------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+--------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; soc_inst|soc_bus_router_inst ; 490 ; 220 ; 0 ; 220 ; 632 ; 220 ; 220 ; 220 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|user_uart_tx_inst|ram_for_uart_tx_fifo_inst|data_ram_cell[0][7]__2|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|user_uart_tx_inst|ram_for_uart_tx_fifo_inst|data_ram_cell[0][7]__1|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|user_uart_tx_inst|ram_for_uart_tx_fifo_inst ; 31 ; 4 ; 0 ; 4 ; 8 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|user_uart_tx_inst ; 108 ; 0 ; 35 ; 0 ; 35 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|video_ram_inst|vga_char_inst|char_8x16_rom_inst ; 17 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|video_ram_inst|vga_char_inst|vga_inst ; 17 ; 0 ; 0 ; 0 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|video_ram_inst|vga_char_inst ; 10 ; 0 ; 0 ; 0 ; 30 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|video_ram_inst|ram_block_inst_3|data_ram_cell[0][7]__2|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|video_ram_inst|ram_block_inst_3|data_ram_cell[0][7]__1|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|video_ram_inst|ram_block_inst_3 ; 41 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|video_ram_inst|ram_block_inst_2|data_ram_cell[0][7]__2|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|video_ram_inst|ram_block_inst_2|data_ram_cell[0][7]__1|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|video_ram_inst|ram_block_inst_2 ; 41 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|video_ram_inst|ram_block_inst_1|data_ram_cell[0][7]__2|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|video_ram_inst|ram_block_inst_1|data_ram_cell[0][7]__1|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|video_ram_inst|ram_block_inst_1 ; 41 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|video_ram_inst|ram_block_inst_0|data_ram_cell[0][7]__2|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|video_ram_inst|ram_block_inst_0|data_ram_cell[0][7]__1|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|video_ram_inst|ram_block_inst_0 ; 41 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|video_ram_inst ; 108 ; 0 ; 48 ; 0 ; 52 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|data_ram_inst|ram_block_inst_3|data_ram_cell[0][7]__2|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|data_ram_inst|ram_block_inst_3|data_ram_cell[0][7]__1|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|data_ram_inst|ram_block_inst_3 ; 31 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|data_ram_inst|ram_block_inst_2|data_ram_cell[0][7]__2|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|data_ram_inst|ram_block_inst_2|data_ram_cell[0][7]__1|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|data_ram_inst|ram_block_inst_2 ; 31 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|data_ram_inst|ram_block_inst_1|data_ram_cell[0][7]__2|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|data_ram_inst|ram_block_inst_1|data_ram_cell[0][7]__1|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|data_ram_inst|ram_block_inst_1 ; 31 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|data_ram_inst|ram_block_inst_0|data_ram_cell[0][7]__2|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|data_ram_inst|ram_block_inst_0|data_ram_cell[0][7]__1|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|data_ram_inst|ram_block_inst_0 ; 31 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|data_ram_inst ; 108 ; 0 ; 48 ; 0 ; 34 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|instr_ram_inst|ram_block_inst_3|data_ram_cell[0][7]__2|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|instr_ram_inst|ram_block_inst_3|data_ram_cell[0][7]__1|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|instr_ram_inst|ram_block_inst_3 ; 31 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|instr_ram_inst|ram_block_inst_2|data_ram_cell[0][7]__2|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|instr_ram_inst|ram_block_inst_2|data_ram_cell[0][7]__1|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|instr_ram_inst|ram_block_inst_2 ; 31 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|instr_ram_inst|ram_block_inst_1|data_ram_cell[0][7]__2|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|instr_ram_inst|ram_block_inst_1|data_ram_cell[0][7]__1|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|instr_ram_inst|ram_block_inst_1 ; 31 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|instr_ram_inst|ram_block_inst_0|data_ram_cell[0][7]__2|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|instr_ram_inst|ram_block_inst_0|data_ram_cell[0][7]__1|auto_generated ; 30 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|instr_ram_inst|ram_block_inst_0 ; 31 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|instr_ram_inst ; 108 ; 0 ; 48 ; 0 ; 34 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|instr_rom_inst ; 108 ; 0 ; 74 ; 0 ; 34 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|core_top_inst|core_bus_wrapper_inst ; 105 ; 5 ; 0 ; 5 ; 140 ; 5 ; 5 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|core_top_inst|core_ex_branch_judge_inst ; 68 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|core_top_inst|core_alu_inst ; 113 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|core_top_inst|core_regfile_inst ; 129 ; 0 ; 0 ; 0 ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|core_top_inst|core_id_stage_inst ; 64 ; 0 ; 0 ; 0 ; 137 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|core_top_inst|inst_bus_wrap_inst ; 105 ; 41 ; 0 ; 41 ; 140 ; 41 ; 41 ; 41 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|core_top_inst ; 102 ; 0 ; 2 ; 0 ; 212 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|isp_uart_inst|uart_tx_line_inst ; 66 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|isp_uart_inst|uart_rx_inst ; 2 ; 0 ; 0 ; 0 ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|isp_uart_inst ; 36 ; 8 ; 0 ; 8 ; 140 ; 8 ; 8 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; soc_inst|bus_slaves[0] ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 140 ; 0 ; 140 ; 0 ; 140 ;
; soc_inst|bus_slaves[1] ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 140 ; 0 ; 140 ; 0 ; 140 ;
; soc_inst|bus_slaves[2] ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 140 ; 0 ; 140 ; 0 ; 140 ;
; soc_inst|bus_slaves[3] ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 140 ; 0 ; 140 ; 0 ; 140 ;
; soc_inst|bus_slaves[4] ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 140 ; 0 ; 140 ; 0 ; 140 ;
; soc_inst|bus_masters[0] ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 140 ; 0 ; 140 ; 0 ; 140 ;
; soc_inst|bus_masters[1] ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 140 ; 0 ; 140 ; 0 ; 140 ;
; soc_inst|bus_masters[2] ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 140 ; 0 ; 140 ; 0 ; 140 ;
; soc_inst ; 3 ; 0 ; 1 ; 0 ; 21 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+--------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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DONE

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start_full_compilation:s
start_analysis_synthesis:s-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s-start_full_compilation
start_assembler:s-start_full_compilation
start_timing_analyzer:s-start_full_compilation
start_eda_netlist_writer:s-start_full_compilation

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Quartus/DE0_Nano/incremental_db/README
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This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

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c5eb7f6cdd530884c3b884e0a3668ea4

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<sld_project_info>
<project>
<hash md5_digest_80b="4ed33baeec61574974c8"/>
</project>
<file_info>
<file device="EP4CE22F17C6" path="DE0_Nano.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>

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