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简化流水线
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WangXuan95
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commit
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@ -280,7 +280,6 @@ set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_regfile.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_id_segreg.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_id_stage.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_alu.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_ex_branch_judge.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_bus_wrapper.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/dual_read_port_ram_32x32.sv
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -1,4 +1,4 @@
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/* Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version */
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/* Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version */
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JedecChain;
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FileRevision(JESD32A);
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DefaultMfr(6E);
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@ -1,6 +1,6 @@
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<sld_project_info>
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<project>
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<hash md5_digest_80b="c0f22711e2ea592227c1"/>
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<hash md5_digest_80b="cefaa24b22dc0d7c5813"/>
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</project>
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<file_info>
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<file device="EP4CE22F17C6" path="DE0Nano_USTCRVSoC.sof" usercode="0xFFFFFFFF"/>
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Binary file not shown.
@ -1,29 +1,57 @@
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module core_alu(
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input logic [ 6:0] i_opcode, i_funct7,
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input logic [ 2:0] i_funct3,
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input logic [31:0] i_num1u, i_num2u, i_immu, i_pc_immu,
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output logic [31:0] o_res
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input logic [31:0] i_num1u, i_num2u, i_pc, i_immu,
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output logic o_branch_jalr,
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output logic [31:0] o_res, o_branch_jalr_target
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);
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logic [4:0] shamt_rs, shamt_imm;
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logic [31:0] shifted;
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logic [ 4:0] shamt_rs, shamt_imm;
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logic [31:0] num1_plus_imm, pc_plus_imm;
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logic signed [31:0] i_num1s, i_num2s, i_imms;
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assign shamt_imm = i_immu[4:0];
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assign shamt_rs = i_num2u[4:0];
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assign i_num1s = i_num1u;
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assign i_num2s = i_num2u;
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assign i_imms = i_immu;
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assign shamt_imm = i_immu[4:0];
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assign shamt_rs = i_num2u[4:0];
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assign num1_plus_imm = i_num1u + i_immu;
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assign pc_plus_imm = i_pc + i_immu;
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assign i_num1s = i_num1u;
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assign i_num2s = i_num2u;
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assign i_imms = i_immu;
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always_comb
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case(i_opcode)
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7'b1100111 : begin // JALR
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o_branch_jalr <= 1'b1;
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o_branch_jalr_target <= num1_plus_imm;
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end
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7'b1100011 : begin // BRANCH类
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case(i_funct3)
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3'b000 : o_branch_jalr <= (i_num1u == i_num2u); // BEQ
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3'b001 : o_branch_jalr <= (i_num1u != i_num2u); // BNE
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3'b100 : o_branch_jalr <= (i_num1s < i_num2s); // BLT
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3'b101 : o_branch_jalr <= (i_num1s >= i_num2s); // BGE
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3'b110 : o_branch_jalr <= (i_num1u < i_num2u); // BLTU
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3'b111 : o_branch_jalr <= (i_num1u >= i_num2u); // BGEU
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default: o_branch_jalr <= 1'b0;
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endcase
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o_branch_jalr_target <= pc_plus_imm;
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end
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default : begin // 不跳转
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o_branch_jalr <= 1'b0;
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o_branch_jalr_target <= 0;
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end
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endcase
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always_comb
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casex({i_funct7,i_funct3,i_opcode})
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// JAL类与JALR类
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17'bxxxxxxx_xxx_110x111 : o_res <= i_pc + 4; // JAL, JALR
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// LUI类
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17'bxxxxxxx_xxx_0110111 : o_res <= i_immu; // LUI
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// AUIPC类
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17'bxxxxxxx_xxx_0010111 : o_res <= i_pc_immu; // AUIPC
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17'bxxxxxxx_xxx_0010111 : o_res <= pc_plus_imm ; // AUIPC
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// 算术类
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17'b0000000_000_0110011 : o_res <= i_num1u + i_num2u; // ADD
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17'bxxxxxxx_000_0010011 : o_res <= i_num1u + i_immu ; // ADDI
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17'bxxxxxxx_000_0010011 : o_res <= num1_plus_imm ; // ADDI
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17'b0100000_000_0110011 : o_res <= i_num1u - i_num2u; // SUB
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// 逻辑类
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17'b0000000_100_0110011 : o_res <= i_num1u ^ i_num2u; // XOR
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@ -1,26 +0,0 @@
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module core_ex_branch_judge(
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input logic i_branch,
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input logic [31:0] i_num1u, i_num2u,
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input logic [ 2:0] i_funct3,
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output logic o_branch
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);
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logic branch_judge_res;
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assign o_branch = i_branch & branch_judge_res;
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logic signed [31:0] i_num1s, i_num2s;
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assign i_num1s = i_num1u;
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assign i_num2s = i_num2u;
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always_comb
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case(i_funct3)
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3'b000 : branch_judge_res <= (i_num1u == i_num2u); // BEQ
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3'b001 : branch_judge_res <= (i_num1u != i_num2u); // BNE
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3'b100 : branch_judge_res <= (i_num1s < i_num2s); // BLT
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3'b101 : branch_judge_res <= (i_num1s >= i_num2s); // BGE
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3'b110 : branch_judge_res <= (i_num1u < i_num2u); // BLTU
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3'b111 : branch_judge_res <= (i_num1u >= i_num2u); // BGEU
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default: branch_judge_res <= 1'b0;
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endcase
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endmodule
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@ -4,7 +4,7 @@ module core_id_segreg(
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input logic [31:0] i_boot_addr,
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input logic i_en, i_re, i_ex_jmp, i_id_jmp,
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input logic [31:0] i_ex_jmp_target, i_id_jmp_target,
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output logic [31:0] o_pc, o_next_pc, o_instr,
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output logic [31:0] o_pc, o_instr,
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naive_bus.master bus_master
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);
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@ -22,8 +22,6 @@ assign bus_master.rd_be = {4{i_re}};
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assign bus_master.rd_addr = i_re ? target_pc : 0;
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assign conflict = (bus_master.rd_req & ~bus_master.rd_gnt);
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assign o_next_pc = o_pc + 4;
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always_comb
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if(i_ex_jmp)
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target_pc <= i_ex_jmp_target;
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@ -32,7 +30,7 @@ always_comb
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else if( ~(i_re) | conflict_latch)
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target_pc <= o_pc;
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else
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target_pc <= o_next_pc;
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target_pc <= o_pc + 4;
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always @ (posedge clk or negedge rst_n)
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if(~rst_n) begin
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@ -1,79 +1,68 @@
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module core_id_stage(
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input logic [31:0] i_instr,
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input logic [31:0] i_pc,
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output logic [ 4:0] o_rs1_addr, o_rs2_addr,
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output logic o_rs1_en, o_rs2_en,
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output logic o_jal, o_jalr, o_branch_may,
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output logic o_nextpc2reg, o_alures2reg, o_memory2reg,
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output logic o_mem_write,
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output logic [31:0] o_pc_plus_imm, o_imm,
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output logic [4:0] o_dst_reg_addr,
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output logic [6:0] o_opcode, o_funct7,
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output logic [2:0] o_funct3
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output logic o_src1_reg_en, o_src2_reg_en,
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output logic o_jal, o_alures2reg, o_memory2reg, o_mem_write,
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output logic [ 4:0] o_src1_reg_addr, o_src2_reg_addr, o_dst_reg_addr,
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output logic [ 6:0] o_opcode, o_funct7,
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output logic [ 2:0] o_funct3,
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output logic [31:0] o_imm
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);
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logic [31:0] instr;
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assign {o_funct7, o_src2_reg_addr, o_src1_reg_addr, o_funct3, o_dst_reg_addr, o_opcode} = i_instr;
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enum {UKNOWN_TYPE, R_TYPE, I_TYPE, IZ_TYPE, S_TYPE, B_TYPE, U_TYPE, J_TYPE} instr_type;
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localparam OPCODE_AUIPC = 7'b0010111, // rd=pc+imm
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OPCODE_LUI = 7'b0110111, // rd=imm;
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OPCODE_JAL = 7'b1101111, // rd=pc+4, pc= pc+imm*2,
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OPCODE_JALR = 7'b1100111, // rd=pc+4, pc= rs1+imm
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OPCODE_BXXX = 7'b1100011, // conditional branch, pc= pc+imm*2,
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OPCODE_LUI = 7'b0110111, // rd = imm;
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OPCODE_BRANCH = 7'b1100011, // conditional branch, pc= pc+imm*2,
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OPCODE_ALI = 7'b0010011, // arithmetic and logical I-TYPE, rd=alu_res
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OPCODE_ALR = 7'b0110011, // arithmetic and logical R-TYPE, rd=alu_res
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OPCODE_LOAD = 7'b0000011, // load
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OPCODE_STORE = 7'b0100011; // store
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assign instr = i_instr;
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assign o_pc_plus_imm = i_pc + o_imm;
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assign {o_funct7, o_rs2_addr, o_rs1_addr, o_funct3, o_dst_reg_addr, o_opcode} = instr;
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// generate control signals
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assign o_jal = (o_opcode == OPCODE_JAL );
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assign o_jalr = (o_opcode == OPCODE_JALR );
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assign o_branch_may = (o_opcode == OPCODE_BXXX );
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assign o_nextpc2reg = (o_opcode == OPCODE_JAL || o_opcode == OPCODE_JALR );
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assign o_alures2reg = (o_opcode == OPCODE_LUI || o_opcode == OPCODE_AUIPC || o_opcode == OPCODE_ALI || o_opcode == OPCODE_ALR);
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assign o_memory2reg = (o_opcode == OPCODE_LOAD );
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assign o_mem_write = (o_opcode == OPCODE_STORE);
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assign o_alures2reg = (o_opcode == OPCODE_JAL || o_opcode == OPCODE_JALR ||
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o_opcode == OPCODE_LUI || o_opcode == OPCODE_AUIPC ||
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o_opcode == OPCODE_ALI || o_opcode == OPCODE_ALR );
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// calculate instruction type
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always_comb
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always_comb // calculate instruction type
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case(o_opcode)
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OPCODE_AUIPC: instr_type <= U_TYPE;
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OPCODE_JAL : instr_type <= J_TYPE;
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OPCODE_JALR : instr_type <= I_TYPE;
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OPCODE_BXXX : instr_type <= B_TYPE;
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OPCODE_LUI : instr_type <= U_TYPE;
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OPCODE_ALI : instr_type <= (o_funct3==3'b011) ? IZ_TYPE : I_TYPE;
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OPCODE_ALR : instr_type <= R_TYPE;
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OPCODE_LOAD : instr_type <= I_TYPE;
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OPCODE_STORE: instr_type <= S_TYPE;
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default : instr_type <= UKNOWN_TYPE;
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OPCODE_AUIPC : instr_type <= U_TYPE;
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OPCODE_JAL : instr_type <= J_TYPE;
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OPCODE_JALR : instr_type <= I_TYPE;
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OPCODE_BRANCH : instr_type <= B_TYPE;
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OPCODE_LUI : instr_type <= U_TYPE;
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OPCODE_ALI : instr_type <= (o_funct3==3'b011) ? IZ_TYPE : I_TYPE;
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OPCODE_ALR : instr_type <= R_TYPE;
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OPCODE_LOAD : instr_type <= I_TYPE;
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OPCODE_STORE : instr_type <= S_TYPE;
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default : instr_type <= UKNOWN_TYPE;
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endcase
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always_comb
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always_comb // calculate imm
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case(instr_type)
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I_TYPE : o_imm <= {{20{instr[31]}} , instr[31:20]};
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IZ_TYPE: o_imm <= { 20'h0 , instr[31:20]};
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S_TYPE : o_imm <= {{20{instr[31]}} , instr[31:25], instr[11:7]};
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B_TYPE : o_imm <= {{20{instr[31]}} , instr[7], instr[30:25], instr[11:8], 1'b0};
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U_TYPE : o_imm <= { instr[31:12] , 12'h0 };
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J_TYPE : o_imm <= {{12{instr[31]}} , instr[19:12], instr[20], instr[30:21], 1'b0};
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I_TYPE : o_imm <= {{20{i_instr[31]}} , i_instr[31:20]};
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IZ_TYPE: o_imm <= { 20'h0 , i_instr[31:20]};
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S_TYPE : o_imm <= {{20{i_instr[31]}} , i_instr[31:25], i_instr[11:7]};
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B_TYPE : o_imm <= {{20{i_instr[31]}} , i_instr[7], i_instr[30:25], i_instr[11:8], 1'b0};
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U_TYPE : o_imm <= { i_instr[31:12] , 12'h0 };
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J_TYPE : o_imm <= {{12{i_instr[31]}} , i_instr[19:12], i_instr[20], i_instr[30:21], 1'b0};
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default: o_imm <= 0;
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endcase
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always_comb
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always_comb // calculate read register enable
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case(instr_type)
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R_TYPE : {o_rs2_en, o_rs1_en} <= 2'b11;
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I_TYPE : {o_rs2_en, o_rs1_en} <= 2'b01;
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IZ_TYPE: {o_rs2_en, o_rs1_en} <= 2'b01;
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S_TYPE : {o_rs2_en, o_rs1_en} <= 2'b11;
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B_TYPE : {o_rs2_en, o_rs1_en} <= 2'b11;
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U_TYPE : {o_rs2_en, o_rs1_en} <= 2'b00;
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J_TYPE : {o_rs2_en, o_rs1_en} <= 2'b00;
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default: {o_rs2_en, o_rs1_en} <= 2'b00;
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R_TYPE : {o_src2_reg_en, o_src1_reg_en} <= 2'b11;
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I_TYPE : {o_src2_reg_en, o_src1_reg_en} <= 2'b01;
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IZ_TYPE: {o_src2_reg_en, o_src1_reg_en} <= 2'b01;
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S_TYPE : {o_src2_reg_en, o_src1_reg_en} <= 2'b11;
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B_TYPE : {o_src2_reg_en, o_src1_reg_en} <= 2'b11;
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default: {o_src2_reg_en, o_src1_reg_en} <= 2'b00;
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endcase
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endmodule
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@ -4,35 +4,30 @@ module core_top(
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naive_bus.master instr_master, data_master
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);
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// ID stage
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logic [31:0] id_instr, id_pc, id_next_pc;
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logic id_rs1_en, id_rs2_en;
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logic [4:0] id_rs1_addr, id_rs2_addr, id_dst_reg_addr;
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logic id_jal, id_jalr, id_branch_may;
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logic id_nextpc2reg, id_alures2reg, id_memory2reg;
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logic id_memwrite;
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logic [6:0] id_opcode, id_funct7;
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logic [2:0] id_funct3;
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logic [31:0] id_pc_plus_imm, id_imm;
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logic [31:0] id_instr, id_pc;
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logic id_src1_reg_en, id_src2_reg_en;
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logic [ 4:0] id_src1_reg_addr, id_src2_reg_addr, id_dst_reg_addr;
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logic id_jal, id_alures2reg, id_memory2reg, id_memwrite;
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logic [ 6:0] id_opcode, id_funct7;
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logic [ 2:0] id_funct3;
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logic [31:0] id_imm;
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// EX stage
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logic ex_jalr=1'b0, ex_branch_may=1'b0, ex_branch;
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logic ex_nextpc2reg=1'b0, ex_alures2reg=1'b0, ex_memory2reg=1'b0, ex_memwrite=1'b0;
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logic [31:0] ex_s1, ex_s2;
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logic ex_branch_jalr, ex_alures2reg=1'b0, ex_memory2reg=1'b0, ex_memwrite=1'b0;
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logic [6:0] ex_opcode=7'h0, ex_funct7=7'h0;
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logic [2:0] ex_funct3=3'h0;
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logic [31:0] ex_alu_res;
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logic [4:0] ex_dst_reg_addr=5'h0;
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logic [31:0] ex_s1_plus_imm, ex_imm=0, ex_next_pc=0, ex_pc_plus_imm=0;
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logic [31:0] ex_alu_res, ex_src1_reg_data, ex_src2_reg_data, ex_pc=0, ex_imm=0, ex_branch_jalr_target;
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// MEM stage
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logic [2:0] mem_funct3=3'b0;
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logic mem_2reg=1'b0, mem_memory2reg=1'b0, mem_memwrite=1'b0;
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logic [31:0] mem_2regdata=0, mem_mem_wdata=0, mem_s1_plus_imm=0;
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logic mem_alures2reg=1'b0, mem_memory2reg=1'b0, mem_memwrite=1'b0;
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logic [31:0] mem_alu_res=0, mem_mem_wdata=0, mem_mem_addr=0;
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logic [4:0] mem_dst_reg_addr=5'h0;
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// WB stage
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logic wb_memory2reg=1'b0, wb_2reg=1'b0;
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logic [31:0] wb_mem_2regdata=0, wb_reg_wdata, wb_memout;
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logic wb_memory2reg=1'b0, wb_regwrite=1'b0;
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logic [31:0] wb_alu_res=0, wb_reg_wdata, wb_memout;
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logic [4:0] wb_dst_reg_addr=5'h0;
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// hazard signal
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@ -51,89 +46,75 @@ assign mem_stall = mem_data_bus_conflict;
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assign wb_nop = mem_data_bus_conflict;
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assign loaduse =
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(id_rs1_en & ex_alures2reg & (id_rs1_addr== ex_dst_reg_addr) ) |
|
||||
(id_rs2_en & ex_alures2reg & (id_rs2_addr== ex_dst_reg_addr) ) |
|
||||
(id_rs1_en & ex_memory2reg & (id_rs1_addr== ex_dst_reg_addr) ) |
|
||||
(id_rs2_en & ex_memory2reg & (id_rs2_addr== ex_dst_reg_addr) ) |
|
||||
(id_rs1_en &mem_memory2reg & (id_rs1_addr==mem_dst_reg_addr) ) |
|
||||
(id_rs2_en &mem_memory2reg & (id_rs2_addr==mem_dst_reg_addr) ) ;
|
||||
|
||||
|
||||
(id_src1_reg_en & ex_memory2reg & (id_src1_reg_addr== ex_dst_reg_addr) ) |
|
||||
(id_src2_reg_en & ex_memory2reg & (id_src2_reg_addr== ex_dst_reg_addr) ) |
|
||||
(id_src1_reg_en & mem_memory2reg & (id_src1_reg_addr==mem_dst_reg_addr) ) |
|
||||
(id_src2_reg_en & mem_memory2reg & (id_src2_reg_addr==mem_dst_reg_addr) ) ;
|
||||
|
||||
// -------------------------------------------------------------------------------
|
||||
// PC controller - timing logic
|
||||
// -------------------------------------------------------------------------------
|
||||
core_id_segreg inst_bus_wrap_inst(
|
||||
core_id_segreg core_id_segreg_inst(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
.i_boot_addr ( i_boot_addr ),
|
||||
.i_en ( ~id_stall ),
|
||||
.i_re ( ~id_read_disable ),
|
||||
.i_ex_jmp ( ex_branch | ex_jalr ),
|
||||
.i_ex_jmp_target ( ex_branch ? ex_pc_plus_imm:ex_s1_plus_imm ),
|
||||
.i_ex_jmp ( ex_branch_jalr ),
|
||||
.i_ex_jmp_target ( ex_branch_jalr_target ),
|
||||
.i_id_jmp ( id_jal ),
|
||||
.i_id_jmp_target ( id_pc_plus_imm ),
|
||||
.i_id_jmp_target ( id_pc + id_imm ),
|
||||
.o_pc ( id_pc ),
|
||||
.o_next_pc ( id_next_pc ),
|
||||
.o_instr ( id_instr ),
|
||||
.bus_master ( instr_master )
|
||||
);
|
||||
|
||||
|
||||
// -------------------------------------------------------------------------------
|
||||
// ID stage - comb logic
|
||||
// -------------------------------------------------------------------------------
|
||||
core_id_stage core_id_stage_inst(
|
||||
.i_instr ( id_instr ),
|
||||
.i_pc ( id_pc ),
|
||||
.o_rs1_addr ( id_rs1_addr ),
|
||||
.o_rs2_addr ( id_rs2_addr ),
|
||||
.o_rs1_en ( id_rs1_en ),
|
||||
.o_rs2_en ( id_rs2_en ),
|
||||
.o_src1_reg_en ( id_src1_reg_en ),
|
||||
.o_src2_reg_en ( id_src2_reg_en ),
|
||||
.o_jal ( id_jal ),
|
||||
.o_jalr ( id_jalr ),
|
||||
.o_branch_may ( id_branch_may ),
|
||||
.o_nextpc2reg ( id_nextpc2reg ),
|
||||
.o_alures2reg ( id_alures2reg ),
|
||||
.o_memory2reg ( id_memory2reg ),
|
||||
.o_mem_write ( id_memwrite ),
|
||||
.o_pc_plus_imm ( id_pc_plus_imm ),
|
||||
.o_imm ( id_imm ),
|
||||
.o_src1_reg_addr ( id_src1_reg_addr ),
|
||||
.o_src2_reg_addr ( id_src2_reg_addr ),
|
||||
.o_dst_reg_addr ( id_dst_reg_addr ),
|
||||
.o_opcode ( id_opcode ),
|
||||
.o_funct7 ( id_funct7 ),
|
||||
.o_funct3 ( id_funct3 )
|
||||
.o_funct3 ( id_funct3 ),
|
||||
.o_imm ( id_imm )
|
||||
);
|
||||
|
||||
|
||||
// -------------------------------------------------------------------------------
|
||||
// ID-EX stage - timing logic
|
||||
// ID-EX stage seg reg - timing logic
|
||||
// -------------------------------------------------------------------------------
|
||||
core_regfile core_regfile_inst(
|
||||
core_regfile core_regfile_inst( // regfile is a part of ID-EX seg reg
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
.rd_latch ( ex_stall ),
|
||||
.i_re1 ( id_rs1_en ),
|
||||
.i_raddr1 ( id_rs1_addr ),
|
||||
.o_rdata1 ( ex_s1 ),
|
||||
.i_re2 ( id_rs2_en ),
|
||||
.i_raddr2 ( id_rs2_addr ),
|
||||
.o_rdata2 ( ex_s2 ),
|
||||
.i_forward1 ( ex_nextpc2reg ),
|
||||
.i_re1 ( id_src1_reg_en ),
|
||||
.i_raddr1 ( id_src1_reg_addr ),
|
||||
.o_rdata1 ( ex_src1_reg_data ),
|
||||
.i_re2 ( id_src2_reg_en ),
|
||||
.i_raddr2 ( id_src2_reg_addr ),
|
||||
.o_rdata2 ( ex_src2_reg_data ),
|
||||
.i_forward1 ( ex_alures2reg ),
|
||||
.i_faddr1 ( ex_dst_reg_addr ),
|
||||
.i_fdata1 ( ex_next_pc ),
|
||||
.i_forward2 ( mem_2reg ),
|
||||
.i_fdata1 ( ex_alu_res ),
|
||||
.i_forward2 ( mem_alures2reg ),
|
||||
.i_faddr2 ( mem_dst_reg_addr ),
|
||||
.i_fdata2 ( mem_2regdata ),
|
||||
.i_we ( wb_2reg ),
|
||||
.i_fdata2 ( mem_alu_res ),
|
||||
.i_we ( wb_regwrite ),
|
||||
.i_waddr ( wb_dst_reg_addr ),
|
||||
.i_wdata ( wb_reg_wdata )
|
||||
);
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if(~rst_n) begin
|
||||
ex_jalr <= 1'b0;
|
||||
ex_branch_may <= 1'b0;
|
||||
ex_nextpc2reg <= 1'b0;
|
||||
ex_alures2reg <= 1'b0;
|
||||
ex_memory2reg <= 1'b0;
|
||||
ex_memwrite <= 1'b0;
|
||||
@ -142,22 +123,17 @@ always @ (posedge clk or negedge rst_n)
|
||||
ex_funct3 <= 3'h0;
|
||||
ex_funct7 <= 7'h0;
|
||||
ex_imm <= 0;
|
||||
ex_next_pc <= 0;
|
||||
ex_pc_plus_imm <= 0;
|
||||
ex_pc <= 0;
|
||||
end else if(~ex_stall) begin
|
||||
ex_jalr <= ex_nop ? 1'b0 : id_jalr;
|
||||
ex_branch_may <= ex_nop ? 1'b0 : id_branch_may;
|
||||
ex_nextpc2reg <= ex_nop ? 1'b0 : id_nextpc2reg;
|
||||
ex_alures2reg <= ex_nop ? 1'b0 : id_alures2reg;
|
||||
ex_memory2reg <= ex_nop ? 1'b0 : id_memory2reg;
|
||||
ex_memwrite <= ex_nop ? 1'b0 : id_memwrite;
|
||||
ex_dst_reg_addr <= ex_nop ? 5'h0 : id_dst_reg_addr;
|
||||
ex_opcode <= ex_nop ? 7'h0 : id_opcode;
|
||||
ex_funct3 <= ex_nop ? 3'h0 : id_funct3;
|
||||
ex_funct7 <= ex_nop ? 7'h0 : id_funct7;
|
||||
ex_funct3 <= ex_nop ? 3'h0 : id_funct3;
|
||||
ex_imm <= ex_nop ? 0 : id_imm;
|
||||
ex_next_pc <= ex_nop ? 0 : id_next_pc;
|
||||
ex_pc_plus_imm <= ex_nop ? 0 : id_pc_plus_imm;
|
||||
ex_pc <= ex_nop ? 0 : id_pc;
|
||||
end
|
||||
|
||||
|
||||
@ -165,23 +141,18 @@ always @ (posedge clk or negedge rst_n)
|
||||
// EX stage - comb logic
|
||||
// -------------------------------------------------------------------------------
|
||||
core_alu core_alu_inst(
|
||||
.i_opcode ( ex_opcode ),
|
||||
.i_funct7 ( ex_funct7 ),
|
||||
.i_funct3 ( ex_funct3 ),
|
||||
.i_num1u ( ex_s1 ),
|
||||
.i_num2u ( ex_s2 ),
|
||||
.i_immu ( ex_imm ),
|
||||
.i_pc_immu ( ex_pc_plus_imm ),
|
||||
.o_res ( ex_alu_res )
|
||||
.i_opcode ( ex_opcode ),
|
||||
.i_funct7 ( ex_funct7 ),
|
||||
.i_funct3 ( ex_funct3 ),
|
||||
.i_num1u ( ex_src1_reg_data ),
|
||||
.i_num2u ( ex_src2_reg_data ),
|
||||
.i_pc ( ex_pc ),
|
||||
.i_immu ( ex_imm ),
|
||||
.o_branch_jalr ( ex_branch_jalr ),
|
||||
.o_branch_jalr_target ( ex_branch_jalr_target ),
|
||||
.o_res ( ex_alu_res )
|
||||
);
|
||||
core_ex_branch_judge core_ex_branch_judge_inst(
|
||||
.i_branch ( ex_branch_may ),
|
||||
.i_num1u ( ex_s1 ),
|
||||
.i_num2u ( ex_s2 ),
|
||||
.i_funct3 ( ex_funct3 ),
|
||||
.o_branch ( ex_branch )
|
||||
);
|
||||
assign ex_s1_plus_imm = ex_s1 + ex_imm;
|
||||
|
||||
|
||||
// -------------------------------------------------------------------------------
|
||||
// EX-MEM stage - timing logic
|
||||
@ -189,21 +160,21 @@ assign ex_s1_plus_imm = ex_s1 + ex_imm;
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if(~rst_n) begin
|
||||
mem_memory2reg <= 1'b0;
|
||||
mem_2reg <= 1'b0;
|
||||
mem_2regdata <= 0;
|
||||
mem_alures2reg <= 1'b0;
|
||||
mem_alu_res <= 0;
|
||||
mem_dst_reg_addr<= 5'h0;
|
||||
mem_memwrite <= 1'b0;
|
||||
mem_mem_addr <= 0;
|
||||
mem_mem_wdata <= 0;
|
||||
mem_s1_plus_imm <= 0;
|
||||
mem_funct3 <= 3'b0;
|
||||
end else if(~mem_stall) begin
|
||||
mem_memory2reg <= ex_memory2reg;
|
||||
mem_2reg <= ex_alures2reg | ex_nextpc2reg;
|
||||
mem_2regdata <= ex_alures2reg ? ex_alu_res : ex_next_pc;
|
||||
mem_alures2reg <= ex_alures2reg;
|
||||
mem_dst_reg_addr<= ex_dst_reg_addr;
|
||||
mem_alu_res <= ex_alu_res;
|
||||
mem_memwrite <= ex_memwrite;
|
||||
mem_mem_wdata <= ex_s2;
|
||||
mem_s1_plus_imm <= ex_s1_plus_imm;
|
||||
mem_mem_addr <= ex_src1_reg_data + ex_imm;
|
||||
mem_mem_wdata <= ex_src2_reg_data;
|
||||
mem_funct3 <= ex_funct3;
|
||||
end
|
||||
|
||||
@ -218,27 +189,27 @@ core_bus_wrapper core_bus_wrapper_inst(
|
||||
.i_we ( mem_memwrite ),
|
||||
.o_conflict ( mem_data_bus_conflict ),
|
||||
.i_funct3 ( mem_funct3 ),
|
||||
.i_addr ( mem_s1_plus_imm ),
|
||||
.i_addr ( mem_mem_addr ),
|
||||
.i_wdata ( mem_mem_wdata ),
|
||||
.o_rdata ( wb_memout ),
|
||||
.bus_master ( data_master )
|
||||
);
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if(~rst_n) begin
|
||||
wb_2reg <= 1'b0;
|
||||
wb_regwrite <= 1'b0;
|
||||
wb_memory2reg <= 1'b0;
|
||||
wb_dst_reg_addr <= 5'h0;
|
||||
wb_mem_2regdata <= 0;
|
||||
wb_alu_res <= 0;
|
||||
end else begin
|
||||
wb_2reg <= wb_nop ? 1'b0 : (mem_2reg | mem_memory2reg);
|
||||
wb_regwrite <= wb_nop ? 1'b0 : (mem_alures2reg | mem_memory2reg);
|
||||
wb_memory2reg <= wb_nop ? 1'b0 : mem_memory2reg;
|
||||
wb_dst_reg_addr <= wb_nop ? 5'h0 : mem_dst_reg_addr;
|
||||
wb_mem_2regdata <= wb_nop ? 0 : mem_2regdata;
|
||||
wb_alu_res <= wb_nop ? 0 : mem_alu_res;
|
||||
end
|
||||
|
||||
// -------------------------------------------------------------------------------
|
||||
// WB stage - comb logic
|
||||
// -------------------------------------------------------------------------------
|
||||
assign wb_reg_wdata = wb_memory2reg ? wb_memout : wb_mem_2regdata;
|
||||
assign wb_reg_wdata = wb_memory2reg ? wb_memout : wb_alu_res;
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3235:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3330:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00
|
||||
@ -11,8 +11,8 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f74797065:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:313633:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3439:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:313833:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3532:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6970636f7265766965775f7461626265645f70616e65:32:00:00
|
||||
@ -22,29 +22,29 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746f6f6c73:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f76696577:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f77696e646f77:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e746f6f6c6261726d67725f72756e:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e746f6f6c6261726d67725f72756e:3233:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e77696e6d656e756d67725f6c61796f7574:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d657373616765776974686f7074696f6e6469616c6f675f646f6e745f73686f775f746869735f6469616c6f675f616761696e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f7365766572697479:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:3537:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:3635:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f637269746963616c5f7761726e696e6773:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f7761726e696e675f6d65737361676573:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e65746c69737474726565766965775f6e65746c6973745f74726565:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:3134:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f676f746f5f6e65746c6973745f64657369676e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6c6963656e73655f6d616e616765:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7265706f7274735f77696e646f77:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f62697467656e:3133:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f696d706c656d656e746174696f6e:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f73796e746865736973:3133:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f62697467656e:3136:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f696d706c656d656e746174696f6e:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f73796e746865736973:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7365745f61735f746f70:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f646576696365:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061727463686f6f7365725f66616d696c795f63686f6f736572:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061727463686f6f7365725f7061727473:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f737065636966795f62697473747265616d5f66696c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f63686f6f73655f70726f6a6563745f6c6f636174696f6e:31:00:00
|
||||
@ -52,15 +52,15 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d61727974696d696e6770616e656c5f70726f6a6563745f73756d6d6172795f74696d696e675f70616e656c5f746162626564:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d6172797574696c697a6174696f6e6761646765745f70726f6a6563745f73756d6d6172795f7574696c697a6174696f6e5f6761646765745f746162626564:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d6172797574696c697a6174696f6e70616e656c5f70726f6a6563745f73756d6d6172795f7574696c697a6174696f6e5f70616e656c5f746162626564:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f72756e5f6761646765745f7461626265645f70616e65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f73686f775f6572726f72:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f73686f775f7761726e696e675f616e645f6572726f725f6d657373616765735f696e5f6d65737361676573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f63616e63656c:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:3132:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f726566726573685f686965726172636879:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7374616c6572756e6469616c6f675f796573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73746174656d6f6e69746f725f72657365745f72756e:31:00:00
|
||||
@ -68,4 +68,4 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:746f756368706f696e747375727665796469616c6f675f6e6f:31:00:00
|
||||
eof:379488275
|
||||
eof:3049335905
|
||||
|
||||
@ -1,21 +1,21 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f726576696577:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:3139:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:3230:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:3335:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:3230:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:3338:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:3231:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265706f72747574696c697a6174696f6e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:3133:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:3133:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:3133:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766566696c6570726f787968616e646c6572:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574746f706e6f6465:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7570646174657265676964:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b73796e746865736973:32:00:00
|
||||
eof:3925159981
|
||||
eof:388301127
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
version:1
|
||||
57656254616c6b5472616e736d697373696f6e417474656d70746564:8
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:15
|
||||
57656254616c6b5472616e736d697373696f6e417474656d70746564:10
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:17
|
||||
eof:
|
||||
|
||||
@ -33,7 +33,7 @@ version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a313673:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:3939352e3534374d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3730362e3030344d42:00:00
|
||||
eof:1494114757
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a333073:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313035382e3134384d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3736382e3638344d42:00:00
|
||||
eof:2715586631
|
||||
|
||||
@ -3,10 +3,10 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Sun Mar 10 22:41:44 2019">
|
||||
<application name="pa" timeStamp="Tue Mar 12 13:15:08 2019">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="802f49394334431ea9abba122e836e9e" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="24" type="ProjectIteration"/>
|
||||
<property name="ProjectIteration" value="29" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
@ -17,30 +17,30 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddSources" value="8" type="JavaHandler"/>
|
||||
<property name="AutoConnectTarget" value="9" type="JavaHandler"/>
|
||||
<property name="AddSources" value="10" type="JavaHandler"/>
|
||||
<property name="AutoConnectTarget" value="10" type="JavaHandler"/>
|
||||
<property name="CoreView" value="1" type="JavaHandler"/>
|
||||
<property name="CustomizeCore" value="1" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="5" type="JavaHandler"/>
|
||||
<property name="LaunchProgramFpga" value="19" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="7" type="JavaHandler"/>
|
||||
<property name="LaunchProgramFpga" value="20" type="JavaHandler"/>
|
||||
<property name="NewProject" value="1" type="JavaHandler"/>
|
||||
<property name="OpenHardwareManager" value="35" type="JavaHandler"/>
|
||||
<property name="OpenRecentTarget" value="10" type="JavaHandler"/>
|
||||
<property name="ProgramDevice" value="20" type="JavaHandler"/>
|
||||
<property name="OpenHardwareManager" value="38" type="JavaHandler"/>
|
||||
<property name="OpenRecentTarget" value="11" type="JavaHandler"/>
|
||||
<property name="ProgramDevice" value="21" type="JavaHandler"/>
|
||||
<property name="ReportUtilization" value="1" type="JavaHandler"/>
|
||||
<property name="RunBitgen" value="13" type="JavaHandler"/>
|
||||
<property name="RunImplementation" value="10" type="JavaHandler"/>
|
||||
<property name="RunSynthesis" value="13" type="JavaHandler"/>
|
||||
<property name="RunBitgen" value="15" type="JavaHandler"/>
|
||||
<property name="RunImplementation" value="13" type="JavaHandler"/>
|
||||
<property name="RunSynthesis" value="17" type="JavaHandler"/>
|
||||
<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/>
|
||||
<property name="SetTopNode" value="2" type="JavaHandler"/>
|
||||
<property name="ShowView" value="9" type="JavaHandler"/>
|
||||
<property name="ShowView" value="10" type="JavaHandler"/>
|
||||
<property name="UpdateRegId" value="1" type="JavaHandler"/>
|
||||
<property name="ViewTaskSynthesis" value="2" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="AddSrcWizard_SPECIFY_HDL_NETLIST_BLOCK_DESIGN" value="2" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CANCEL" value="5" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="25" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="30" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="1" type="GuiHandlerData"/>
|
||||
<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="2" type="GuiHandlerData"/>
|
||||
<property name="ConstraintsChooserPanel_ADD_FILES" value="1" type="GuiHandlerData"/>
|
||||
@ -50,8 +50,8 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="CreateSrcFileDialog_FILE_TYPE" value="1" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="163" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="49" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="183" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="52" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="7" type="GuiHandlerData"/>
|
||||
<property name="IPCoreView_TABBED_PANE" value="2" type="GuiHandlerData"/>
|
||||
@ -61,29 +61,29 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="MainMenuMgr_TOOLS" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_VIEW" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_WINDOW" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainToolbarMgr_RUN" value="18" type="GuiHandlerData"/>
|
||||
<property name="MainToolbarMgr_RUN" value="23" type="GuiHandlerData"/>
|
||||
<property name="MainWinMenuMgr_LAYOUT" value="2" type="GuiHandlerData"/>
|
||||
<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_SEVERITY" value="2" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="57" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="65" type="GuiHandlerData"/>
|
||||
<property name="MsgView_CRITICAL_WARNINGS" value="6" type="GuiHandlerData"/>
|
||||
<property name="MsgView_WARNING_MESSAGES" value="2" type="GuiHandlerData"/>
|
||||
<property name="NetlistTreeView_NETLIST_TREE" value="15" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_SOURCES" value="8" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="9" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_UPDATE_HIER" value="14" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_SOURCES" value="10" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="10" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_UPDATE_HIER" value="15" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GOTO_NETLIST_DESIGN" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_LICENSE_MANAGE" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_REPORTS_WINDOW" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_BITGEN" value="13" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_IMPLEMENTATION" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_SYNTHESIS" value="13" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_BITGEN" value="16" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_IMPLEMENTATION" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_SYNTHESIS" value="17" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SET_AS_TOP" value="2" type="GuiHandlerData"/>
|
||||
<property name="PAViews_CODE" value="11" type="GuiHandlerData"/>
|
||||
<property name="PAViews_DEVICE" value="2" type="GuiHandlerData"/>
|
||||
<property name="PartChooser_FAMILY_CHOOSER" value="1" type="GuiHandlerData"/>
|
||||
<property name="PartChooser_PARTS" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProgramFpgaDialog_PROGRAM" value="17" type="GuiHandlerData"/>
|
||||
<property name="ProgramFpgaDialog_PROGRAM" value="18" type="GuiHandlerData"/>
|
||||
<property name="ProgramFpgaDialog_SPECIFY_BITSTREAM_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="1" type="GuiHandlerData"/>
|
||||
@ -91,15 +91,15 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="ProjectSummaryTimingPanel_PROJECT_SUMMARY_TIMING_PANEL_TABBED" value="17" type="GuiHandlerData"/>
|
||||
<property name="ProjectSummaryUtilizationGadget_PROJECT_SUMMARY_UTILIZATION_GADGET_TABBED" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_PANEL_TABBED" value="5" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_DELETE" value="5" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_DELETE" value="7" type="GuiHandlerData"/>
|
||||
<property name="RunGadget_RUN_GADGET_TABBED_PANE" value="1" type="GuiHandlerData"/>
|
||||
<property name="RunGadget_SHOW_ERROR" value="2" type="GuiHandlerData"/>
|
||||
<property name="RunGadget_SHOW_WARNING_AND_ERROR_MESSAGES_IN_MESSAGES" value="1" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_SAVE" value="2" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="5" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_SAVE" value="3" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="6" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_HIERARCHY" value="11" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_HIERARCHY" value="12" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_REFRESH_HIERARCHY" value="1" type="GuiHandlerData"/>
|
||||
<property name="StaleRunDialog_YES" value="1" type="GuiHandlerData"/>
|
||||
<property name="StateMonitor_RESET_RUN" value="1" type="GuiHandlerData"/>
|
||||
@ -109,9 +109,9 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="TouchpointSurveyDialog_NO" value="1" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="37" type="GuiMode"/>
|
||||
<property name="GuiMode" value="40" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="31" type="TclMode"/>
|
||||
<property name="TclMode" value="34" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
@ -76,13 +76,6 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_ex_branch_judge.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_id_segreg.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
|
||||
@ -2,18 +2,27 @@
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Sun Mar 10 22:06:31 2019
|
||||
# Process ID: 17240
|
||||
# Start of session at: Tue Mar 12 00:06:43 2019
|
||||
# Process ID: 17980
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11140 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent15368 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
update_compile_order -fileset sources_1
|
||||
add_files -norecurse E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 8
|
||||
wait_on_run synth_1
|
||||
export_ip_user_files -of_objects [get_files E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv] -no_script -reset -force -quiet
|
||||
remove_files E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
|
||||
launch_runs impl_1 -jobs 8
|
||||
wait_on_run impl_1
|
||||
add_files -norecurse E:/work-Lab/RISCV-Pipline-CPU/1_VerilogSourceCode/1_CPUCore_src/BRAMModule/FakeCache.v
|
||||
update_compile_order -fileset sources_1
|
||||
export_ip_user_files -of_objects [get_files E:/work-Lab/RISCV-Pipline-CPU/1_VerilogSourceCode/1_CPUCore_src/BRAMModule/FakeCache.v] -no_script -reset -force -quiet
|
||||
remove_files E:/work-Lab/RISCV-Pipline-CPU/1_VerilogSourceCode/1_CPUCore_src/BRAMModule/FakeCache.v
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 8
|
||||
wait_on_run synth_1
|
||||
|
||||
@ -0,0 +1,35 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Mon Mar 11 16:18:42 2019
|
||||
# Process ID: 12448
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent12796 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
update_compile_order -fileset sources_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 8
|
||||
wait_on_run synth_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 8
|
||||
wait_on_run synth_1
|
||||
launch_runs impl_1 -jobs 8
|
||||
wait_on_run impl_1
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
wait_on_run impl_1
|
||||
open_hw
|
||||
connect_hw_server
|
||||
open_hw_target
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
current_hw_device [get_hw_devices xc7a100t_0]
|
||||
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
program_hw_devices [get_hw_devices xc7a100t_0]
|
||||
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
@ -0,0 +1,23 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Sun Mar 10 22:06:31 2019
|
||||
# Process ID: 17240
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11140 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
update_compile_order -fileset sources_1
|
||||
add_files -norecurse E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv
|
||||
update_compile_order -fileset sources_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 8
|
||||
wait_on_run synth_1
|
||||
launch_runs impl_1 -jobs 8
|
||||
wait_on_run impl_1
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
wait_on_run impl_1
|
||||
Loading…
x
Reference in New Issue
Block a user