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简化指令总线接口
This commit is contained in:
WangXuan95
parent
87e580c4af
commit
52b5e214bc
@ -159,7 +159,7 @@ namespace USTCRVSoC_tool
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{
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bool stat;
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string msg = "";
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string asm_command = "riscv32-elf-as " + fileSelectionText.Text + " -o compile_tmp.o -march=rv32i";
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string asm_command = "riscv32-elf-as " + fileSelectionText.Text + " -o compile_tmp.o -march=rv32im";
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string ld_command = "riscv32-elf-ld compile_tmp.o -o compile_tmp.om";
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compilePromptText.Clear();
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@ -254,6 +254,12 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name FLOW_DISABLE_ASSEMBLER OFF
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name SYSTEMVERILOG_FILE DE0Nano_USTCRVSoC_top.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/naive_bus.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/naive_bus_router.sv
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@ -271,15 +277,10 @@ set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/char8x16_rom.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/ram128B.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_top.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_regfile.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_id_segreg.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_id_stage.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_alu.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_ex_branch_judge.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_bus_wrapper.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/dual_read_port_ram_32x32.sv
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name FLOW_DISABLE_ASSEMBLER OFF
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -1,6 +1,6 @@
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<sld_project_info>
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<project>
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<hash md5_digest_80b="ead836b65d4d6cfe59ec"/>
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<hash md5_digest_80b="c0f22711e2ea592227c1"/>
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</project>
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<file_info>
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<file device="EP4CE22F17C6" path="DE0Nano_USTCRVSoC.sof" usercode="0xFFFFFFFF"/>
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Binary file not shown.
@ -1,8 +1,7 @@
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module core_bus_wrapper(
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input logic clk, rst_n,
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input logic i_en_n,
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input logic i_re, i_we,
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output logic o_conflict, o_conflict_latch,
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output logic o_conflict,
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input logic [ 2:0] i_funct3,
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input logic [31:0] i_addr,
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input logic [31:0] i_wdata,
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@ -11,10 +10,10 @@ module core_bus_wrapper(
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naive_bus.master bus_master
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);
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logic i_re_latch;
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logic [1:0] addr_lsb, rd_addr_lsb;
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logic [31:0] addr_bus, wdata, rdata, rdata_latch;
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logic [2:0] rd_funct3;
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logic i_re_latch=1'b0, o_conflict_latch=1'b0;
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logic [1:0] addr_lsb, rd_addr_lsb=2'b0;
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logic [31:0] addr_bus, wdata, rdata, rdata_latch=0;
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logic [2:0] rd_funct3=3'b0;
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logic [3:0] byte_enable;
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assign addr_bus = {i_addr[31:2], 2'b0};
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@ -71,10 +70,10 @@ always @ (posedge clk or negedge rst_n)
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o_conflict_latch <= 1'b0;
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rdata_latch <= 0;
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end else begin
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i_re_latch <= i_re & ~i_en_n;
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i_re_latch <= i_re;
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rd_addr_lsb <= addr_lsb;
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rd_funct3 <= i_funct3;
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o_conflict_latch <= o_conflict | i_en_n;
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o_conflict_latch <= o_conflict;
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rdata_latch <= o_rdata;
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end
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62
hardware/RTL/core_id_segreg.sv
Normal file
62
hardware/RTL/core_id_segreg.sv
Normal file
@ -0,0 +1,62 @@
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module core_id_segreg(
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input logic clk, rst_n,
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input logic [31:0] i_boot_addr,
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input logic i_en, i_re, i_ex_jmp, i_id_jmp,
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input logic [31:0] i_ex_jmp_target, i_id_jmp_target,
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output logic [31:0] o_pc, o_next_pc, o_instr,
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naive_bus.master bus_master
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);
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logic [31:0] target_pc, instr_latch=0;
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logic conflict, conflict_latch=1'b0, instr_hold_n = 1'b0;
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initial begin o_pc=0; end
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assign bus_master.wr_req = 1'b0; // core never write instruction ram
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assign bus_master.wr_be = 4'h0;
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assign bus_master.wr_addr = 0;
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assign bus_master.wr_data = 0;
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assign bus_master.rd_req = i_re;
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assign bus_master.rd_be = {4{i_re}};
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assign bus_master.rd_addr = i_re ? target_pc : 0;
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assign conflict = (bus_master.rd_req & ~bus_master.rd_gnt);
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assign o_next_pc = o_pc + 4;
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always_comb
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if(i_ex_jmp)
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target_pc <= i_ex_jmp_target;
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else if(i_id_jmp)
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target_pc <= i_id_jmp_target;
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else if( ~(i_re) | conflict_latch)
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target_pc <= o_pc;
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else
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target_pc <= o_next_pc;
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always @ (posedge clk or negedge rst_n)
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if(~rst_n) begin
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instr_hold_n <= 1'b0;
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conflict_latch <= 1'b0;
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instr_latch <= 0;
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end else begin
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instr_hold_n <= i_re & i_en;
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conflict_latch <= conflict;
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instr_latch <= o_instr;
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end
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always_comb
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if(~instr_hold_n)
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o_instr <= instr_latch;
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else if(i_ex_jmp | conflict_latch)
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o_instr <= 0;
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else
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o_instr <= bus_master.rd_data;
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always @ (posedge clk)
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if(~rst_n)
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o_pc <= {i_boot_addr[31:2],2'b00} - 4;
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else
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o_pc <= target_pc;
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endmodule
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@ -9,8 +9,7 @@ module core_id_stage(
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output logic [31:0] o_pc_plus_imm, o_imm,
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output logic [4:0] o_dst_reg_addr,
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output logic [6:0] o_opcode, o_funct7,
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output logic [2:0] o_funct3,
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output logic [31:0] o_next_pc
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output logic [2:0] o_funct3
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);
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logic [31:0] instr;
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@ -28,7 +27,6 @@ localparam OPCODE_AUIPC = 7'b0010111, // rd=pc+imm
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OPCODE_STORE = 7'b0100011; // store
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assign instr = i_instr;
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assign o_next_pc = i_pc + 4;
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assign o_pc_plus_imm = i_pc + o_imm;
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assign {o_funct7, o_rs2_addr, o_rs1_addr, o_funct3, o_dst_reg_addr, o_opcode} = instr;
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@ -3,15 +3,10 @@ module core_top(
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input logic [31:0] i_boot_addr,
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naive_bus.master instr_master, data_master
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);
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// IF stage out
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logic [31:0] if_pc;
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// ID stage
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logic [31:0] id_instr, id_pc;
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logic [31:0] id_instr, id_pc, id_next_pc;
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logic id_rs1_en, id_rs2_en;
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logic [4:0] id_rs1_addr, id_rs2_addr, id_dst_reg_addr;
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logic [31:0] id_next_pc;
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logic id_jal, id_jalr, id_branch_may;
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logic id_nextpc2reg, id_alures2reg, id_memory2reg;
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logic id_memwrite;
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@ -20,45 +15,42 @@ logic [2:0] id_funct3;
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logic [31:0] id_pc_plus_imm, id_imm;
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// EX stage
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logic ex_jalr, ex_branch_may, ex_branch;
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logic ex_nextpc2reg, ex_alures2reg, ex_memory2reg;
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logic ex_memwrite;
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logic ex_jalr=1'b0, ex_branch_may=1'b0, ex_branch;
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logic ex_nextpc2reg=1'b0, ex_alures2reg=1'b0, ex_memory2reg=1'b0, ex_memwrite=1'b0;
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logic [31:0] ex_s1, ex_s2;
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logic [6:0] ex_opcode, ex_funct7;
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logic [2:0] ex_funct3;
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logic [31:0] ex_imm, ex_alu_res;
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logic [4:0] ex_dst_reg_addr;
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logic [31:0] ex_s1_plus_imm, ex_next_pc, ex_pc_plus_imm;
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logic [6:0] ex_opcode=7'h0, ex_funct7=7'h0;
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logic [2:0] ex_funct3=3'h0;
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logic [31:0] ex_alu_res;
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logic [4:0] ex_dst_reg_addr=5'h0;
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logic [31:0] ex_s1_plus_imm, ex_imm=0, ex_next_pc=0, ex_pc_plus_imm=0;
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// MEM stage
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logic [2:0] mem_funct3;
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logic mem_memory2reg, mem_alures2reg, mem_alures_or_nextpc2reg, mem_memwrite;
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logic [31:0] mem_alu_res, mem_2regdata, mem_next_pc, mem_mem_wdata, mem_s1_plus_imm;
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logic [4:0] mem_dst_reg_addr;
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logic [2:0] mem_funct3=3'b0;
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logic mem_2reg=1'b0, mem_memory2reg=1'b0, mem_memwrite=1'b0;
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logic [31:0] mem_2regdata=0, mem_mem_wdata=0, mem_s1_plus_imm=0;
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logic [4:0] mem_dst_reg_addr=5'h0;
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// WB stage
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logic wb_memory2reg, wb_2reg;
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logic [31:0] wb_reg_wdata, wb_mem_2regdata, wb_memout;
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logic [4:0] wb_dst_reg_addr;
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logic wb_memory2reg=1'b0, wb_2reg=1'b0;
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logic [31:0] wb_mem_2regdata=0, wb_reg_wdata, wb_memout;
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logic [4:0] wb_dst_reg_addr=5'h0;
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// write regfile conflict signal
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logic launch_nop, pc_stall, id_stall, id_flush, ex_nop, ex_stall, mem_stall, wreg_conflict, wb_nop;
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logic id_data_bus_conflict, mem_data_bus_conflict;
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// hazard signal
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logic id_read_disable, id_stall, ex_stall, ex_nop, mem_stall, wb_nop;
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logic loaduse, mem_data_bus_conflict;
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// -------------------------------------------------------------------------------
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// conflict - comb logic
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// hazard - comb logic
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// -------------------------------------------------------------------------------
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assign pc_stall = wreg_conflict | id_data_bus_conflict;
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assign id_stall = wreg_conflict;
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assign id_flush = ex_branch | ex_jalr;
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assign ex_stall = mem_data_bus_conflict;
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assign ex_nop = wreg_conflict;
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assign mem_stall = mem_data_bus_conflict;
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assign wb_nop = mem_data_bus_conflict;
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assign id_read_disable = loaduse;
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assign id_stall = mem_data_bus_conflict;
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assign ex_stall = mem_data_bus_conflict;
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assign ex_nop = loaduse;
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assign mem_stall = mem_data_bus_conflict;
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assign wb_nop = mem_data_bus_conflict;
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assign wreg_conflict =
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assign loaduse =
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(id_rs1_en & ex_alures2reg & (id_rs1_addr== ex_dst_reg_addr) ) |
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(id_rs2_en & ex_alures2reg & (id_rs2_addr== ex_dst_reg_addr) ) |
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(id_rs1_en & ex_memory2reg & (id_rs1_addr== ex_dst_reg_addr) ) |
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@ -67,70 +59,50 @@ assign wreg_conflict =
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(id_rs2_en &mem_memory2reg & (id_rs2_addr==mem_dst_reg_addr) ) ;
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// -------------------------------------------------------------------------------
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// IF stage - comb logic
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// -------------------------------------------------------------------------------
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always_comb
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if(ex_branch)
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if_pc <= ex_pc_plus_imm;
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else if(ex_jalr)
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if_pc <= ex_s1_plus_imm;
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else if(id_jal)
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if_pc <= id_pc_plus_imm;
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else if(pc_stall)
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if_pc <= id_pc;
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else
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if_pc <= id_next_pc;
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// -------------------------------------------------------------------------------
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// IF-ID stage - timing logic
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// PC controller - timing logic
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// -------------------------------------------------------------------------------
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core_bus_wrapper inst_bus_wrap_inst(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.i_en_n ( mem_data_bus_conflict ),
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.i_re ( ~id_stall ),
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.i_we ( 1'b0 ),
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.o_conflict_latch ( id_data_bus_conflict ),
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.i_funct3 ( 3'b010 ),
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.i_addr ( if_pc ),
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.i_wdata ( 0 ),
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.o_rdata ( id_instr ),
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.bus_master ( instr_master )
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core_id_segreg inst_bus_wrap_inst(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.i_boot_addr ( i_boot_addr ),
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.i_en ( ~id_stall ),
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.i_re ( ~id_read_disable ),
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.i_ex_jmp ( ex_branch | ex_jalr ),
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.i_ex_jmp_target ( ex_branch ? ex_pc_plus_imm:ex_s1_plus_imm ),
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.i_id_jmp ( id_jal ),
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.i_id_jmp_target ( id_pc_plus_imm ),
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.o_pc ( id_pc ),
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.o_next_pc ( id_next_pc ),
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.o_instr ( id_instr ),
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.bus_master ( instr_master )
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);
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always @ (posedge clk)
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if(~rst_n)
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id_pc <= {i_boot_addr[31:2],2'b00} - 4;
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else if(~mem_data_bus_conflict)
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id_pc <= if_pc;
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// -------------------------------------------------------------------------------
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// ID stage - comb logic
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// -------------------------------------------------------------------------------
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core_id_stage core_id_stage_inst(
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.i_instr ( id_flush ? 0 : id_instr ),
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.i_pc ( id_pc ),
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.o_rs1_addr ( id_rs1_addr ),
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.o_rs2_addr ( id_rs2_addr ),
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.o_rs1_en ( id_rs1_en ),
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.o_rs2_en ( id_rs2_en ),
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.o_jal ( id_jal ),
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.o_jalr ( id_jalr ),
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.o_branch_may ( id_branch_may ),
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.o_nextpc2reg ( id_nextpc2reg ),
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.o_alures2reg ( id_alures2reg ),
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.o_memory2reg ( id_memory2reg ),
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.o_mem_write ( id_memwrite ),
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.o_pc_plus_imm ( id_pc_plus_imm ),
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.o_imm ( id_imm ),
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.o_dst_reg_addr ( id_dst_reg_addr),
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.o_opcode ( id_opcode ),
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.o_funct7 ( id_funct7 ),
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.o_funct3 ( id_funct3 ),
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.o_next_pc ( id_next_pc )
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.i_instr ( id_instr ),
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.i_pc ( id_pc ),
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.o_rs1_addr ( id_rs1_addr ),
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.o_rs2_addr ( id_rs2_addr ),
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.o_rs1_en ( id_rs1_en ),
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.o_rs2_en ( id_rs2_en ),
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.o_jal ( id_jal ),
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.o_jalr ( id_jalr ),
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.o_branch_may ( id_branch_may ),
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.o_nextpc2reg ( id_nextpc2reg ),
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.o_alures2reg ( id_alures2reg ),
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.o_memory2reg ( id_memory2reg ),
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.o_mem_write ( id_memwrite ),
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.o_pc_plus_imm ( id_pc_plus_imm ),
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.o_imm ( id_imm ),
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.o_dst_reg_addr ( id_dst_reg_addr ),
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.o_opcode ( id_opcode ),
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.o_funct7 ( id_funct7 ),
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.o_funct3 ( id_funct3 )
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);
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@ -150,7 +122,7 @@ core_regfile core_regfile_inst(
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.i_forward1 ( ex_nextpc2reg ),
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.i_faddr1 ( ex_dst_reg_addr ),
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.i_fdata1 ( ex_next_pc ),
|
||||
.i_forward2 ( mem_alures_or_nextpc2reg ),
|
||||
.i_forward2 ( mem_2reg ),
|
||||
.i_faddr2 ( mem_dst_reg_addr ),
|
||||
.i_fdata2 ( mem_2regdata ),
|
||||
.i_we ( wb_2reg ),
|
||||
@ -161,31 +133,31 @@ always @ (posedge clk or negedge rst_n)
|
||||
if(~rst_n) begin
|
||||
ex_jalr <= 1'b0;
|
||||
ex_branch_may <= 1'b0;
|
||||
ex_pc_plus_imm <= 0;
|
||||
ex_nextpc2reg <= 1'b0;
|
||||
ex_alures2reg <= 1'b0;
|
||||
ex_memory2reg <= 1'b0;
|
||||
ex_memwrite <= 1'b0;
|
||||
ex_dst_reg_addr <= 5'h0;
|
||||
ex_imm <= 0;
|
||||
ex_opcode <= 7'h0;
|
||||
ex_funct3 <= 3'h0;
|
||||
ex_funct7 <= 7'h0;
|
||||
ex_imm <= 0;
|
||||
ex_next_pc <= 0;
|
||||
ex_pc_plus_imm <= 0;
|
||||
end else if(~ex_stall) begin
|
||||
ex_jalr <= ex_nop ? 1'b0 : id_jalr;
|
||||
ex_branch_may <= ex_nop ? 1'b0 : id_branch_may;
|
||||
ex_pc_plus_imm <= ex_nop ? 0 : id_pc_plus_imm;
|
||||
ex_nextpc2reg <= ex_nop ? 1'b0 : id_nextpc2reg;
|
||||
ex_alures2reg <= ex_nop ? 1'b0 : id_alures2reg;
|
||||
ex_memory2reg <= ex_nop ? 1'b0 : id_memory2reg;
|
||||
ex_memwrite <= ex_nop ? 1'b0 : id_memwrite;
|
||||
ex_dst_reg_addr <= ex_nop ? 5'h0 : id_dst_reg_addr;
|
||||
ex_imm <= ex_nop ? 0 : id_imm;
|
||||
ex_opcode <= ex_nop ? 7'h0 : id_opcode;
|
||||
ex_funct3 <= ex_nop ? 3'h0 : id_funct3;
|
||||
ex_funct7 <= ex_nop ? 7'h0 : id_funct7;
|
||||
ex_imm <= ex_nop ? 0 : id_imm;
|
||||
ex_next_pc <= ex_nop ? 0 : id_next_pc;
|
||||
ex_pc_plus_imm <= ex_nop ? 0 : id_pc_plus_imm;
|
||||
end
|
||||
|
||||
|
||||
@ -217,10 +189,8 @@ assign ex_s1_plus_imm = ex_s1 + ex_imm;
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if(~rst_n) begin
|
||||
mem_memory2reg <= 1'b0;
|
||||
mem_alures2reg <= 1'b0;
|
||||
mem_alures_or_nextpc2reg <= 1'b0;
|
||||
mem_next_pc <= 0;
|
||||
mem_alu_res <= 0;
|
||||
mem_2reg <= 1'b0;
|
||||
mem_2regdata <= 0;
|
||||
mem_dst_reg_addr<= 5'h0;
|
||||
mem_memwrite <= 1'b0;
|
||||
mem_mem_wdata <= 0;
|
||||
@ -228,19 +198,14 @@ always @ (posedge clk or negedge rst_n)
|
||||
mem_funct3 <= 3'b0;
|
||||
end else if(~mem_stall) begin
|
||||
mem_memory2reg <= ex_memory2reg;
|
||||
mem_alures2reg <= ex_alures2reg;
|
||||
mem_alures_or_nextpc2reg <= ex_alures2reg | ex_nextpc2reg;
|
||||
mem_next_pc <= ex_next_pc;
|
||||
mem_alu_res <= ex_alu_res;
|
||||
mem_2reg <= ex_alures2reg | ex_nextpc2reg;
|
||||
mem_2regdata <= ex_alures2reg ? ex_alu_res : ex_next_pc;
|
||||
mem_dst_reg_addr<= ex_dst_reg_addr;
|
||||
mem_memwrite <= ex_memwrite;
|
||||
mem_mem_wdata <= ex_s2;
|
||||
mem_s1_plus_imm <= ex_s1_plus_imm;
|
||||
mem_funct3 <= ex_funct3;
|
||||
end
|
||||
|
||||
|
||||
assign mem_2regdata = mem_alures2reg ? mem_alu_res : mem_next_pc;
|
||||
|
||||
|
||||
// -------------------------------------------------------------------------------
|
||||
@ -249,7 +214,6 @@ assign mem_2regdata = mem_alures2reg ? mem_alu_res : mem_next_pc;
|
||||
core_bus_wrapper core_bus_wrapper_inst(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
.i_en_n ( 1'b0 ),
|
||||
.i_re ( mem_memory2reg ),
|
||||
.i_we ( mem_memwrite ),
|
||||
.o_conflict ( mem_data_bus_conflict ),
|
||||
@ -266,12 +230,15 @@ always @ (posedge clk or negedge rst_n)
|
||||
wb_dst_reg_addr <= 5'h0;
|
||||
wb_mem_2regdata <= 0;
|
||||
end else begin
|
||||
wb_2reg <= wb_nop ? 1'b0 : (mem_alures_or_nextpc2reg | mem_memory2reg);
|
||||
wb_2reg <= wb_nop ? 1'b0 : (mem_2reg | mem_memory2reg);
|
||||
wb_memory2reg <= wb_nop ? 1'b0 : mem_memory2reg;
|
||||
wb_dst_reg_addr <= wb_nop ? 5'h0 : mem_dst_reg_addr;
|
||||
wb_mem_2regdata <= wb_nop ? 0 : mem_2regdata;
|
||||
end
|
||||
|
||||
// -------------------------------------------------------------------------------
|
||||
// WB stage - comb logic
|
||||
// -------------------------------------------------------------------------------
|
||||
assign wb_reg_wdata = wb_memory2reg ? wb_memout : wb_mem_2regdata;
|
||||
|
||||
endmodule
|
||||
|
||||
@ -2,89 +2,26 @@ module instr_rom(
|
||||
input logic clk, rst_n,
|
||||
naive_bus.slave bus
|
||||
);
|
||||
localparam INSTR_CNT = 30'd81;
|
||||
localparam INSTR_CNT = 30'd18;
|
||||
wire [0:INSTR_CNT-1] [31:0] instr_rom_cell = {
|
||||
32'h00010537, // 0x00000000
|
||||
32'h40050113, // 0x00000004
|
||||
32'h00050513, // 0x00000008
|
||||
32'h00200293, // 0x0000000c
|
||||
32'h00552023, // 0x00000010
|
||||
32'h00100293, // 0x00000014
|
||||
32'h00552223, // 0x00000018
|
||||
32'h00100293, // 0x0000001c
|
||||
32'h00552423, // 0x00000020
|
||||
32'h00000593, // 0x00000024
|
||||
32'h00800613, // 0x00000028
|
||||
32'h00006f33, // 0x0000002c
|
||||
32'h020000ef, // 0x00000030
|
||||
32'h00030fb7, // 0x00000034
|
||||
32'h0fc06f13, // 0x00000038
|
||||
32'h01ef8023, // 0x0000003c
|
||||
32'h00c003b7, // 0x00000040
|
||||
32'hfff38393, // 0x00000044
|
||||
32'hfe039ee3, // 0x00000048
|
||||
32'hfb5ff06f, // 0x0000004c
|
||||
32'h0ec5d863, // 0x00000050
|
||||
32'h0005e333, // 0x00000054
|
||||
32'h000663b3, // 0x00000058
|
||||
32'h006502b3, // 0x0000005c
|
||||
32'h0002a283, // 0x00000060
|
||||
32'h04735463, // 0x00000064
|
||||
32'h00750e33, // 0x00000068
|
||||
32'h000e2e03, // 0x0000006c
|
||||
32'h00735863, // 0x00000070
|
||||
32'h005e4663, // 0x00000074
|
||||
32'hffc38393, // 0x00000078
|
||||
32'hfedff06f, // 0x0000007c
|
||||
32'h00650eb3, // 0x00000080
|
||||
32'h01cea023, // 0x00000084
|
||||
32'h00650e33, // 0x00000088
|
||||
32'h000e2e03, // 0x0000008c
|
||||
32'h00735863, // 0x00000090
|
||||
32'h01c2c663, // 0x00000094
|
||||
32'h00430313, // 0x00000098
|
||||
32'hfedff06f, // 0x0000009c
|
||||
32'h00750eb3, // 0x000000a0
|
||||
32'h01cea023, // 0x000000a4
|
||||
32'hfbdff06f, // 0x000000a8
|
||||
32'h00650eb3, // 0x000000ac
|
||||
32'h005ea023, // 0x000000b0
|
||||
32'hffc10113, // 0x000000b4
|
||||
32'h00112023, // 0x000000b8
|
||||
32'hffc10113, // 0x000000bc
|
||||
32'h00b12023, // 0x000000c0
|
||||
32'hffc10113, // 0x000000c4
|
||||
32'h00c12023, // 0x000000c8
|
||||
32'hffc10113, // 0x000000cc
|
||||
32'h00612023, // 0x000000d0
|
||||
32'hffc30613, // 0x000000d4
|
||||
32'hf79ff0ef, // 0x000000d8
|
||||
32'h00012303, // 0x000000dc
|
||||
32'h00410113, // 0x000000e0
|
||||
32'h00012603, // 0x000000e4
|
||||
32'h00410113, // 0x000000e8
|
||||
32'h00012583, // 0x000000ec
|
||||
32'h00410113, // 0x000000f0
|
||||
32'h00012083, // 0x000000f4
|
||||
32'h00410113, // 0x000000f8
|
||||
32'hffc10113, // 0x000000fc
|
||||
32'h00112023, // 0x00000100
|
||||
32'hffc10113, // 0x00000104
|
||||
32'h00b12023, // 0x00000108
|
||||
32'hffc10113, // 0x0000010c
|
||||
32'h00c12023, // 0x00000110
|
||||
32'hffc10113, // 0x00000114
|
||||
32'h00612023, // 0x00000118
|
||||
32'h00430593, // 0x0000011c
|
||||
32'h00012303, // 0x00000120
|
||||
32'h00410113, // 0x00000124
|
||||
32'h00012603, // 0x00000128
|
||||
32'h00410113, // 0x0000012c
|
||||
32'h00012583, // 0x00000130
|
||||
32'h00410113, // 0x00000134
|
||||
32'h00012083, // 0x00000138
|
||||
32'h00410113, // 0x0000013c
|
||||
32'h00008067 // 0x00000140
|
||||
32'h000062b3, // 0x00000000
|
||||
32'h000302b7, // 0x00000004
|
||||
32'h06806313, // 0x00000008
|
||||
32'h00628023, // 0x0000000c
|
||||
32'h06506313, // 0x00000010
|
||||
32'h00628023, // 0x00000014
|
||||
32'h06c06313, // 0x00000018
|
||||
32'h00628023, // 0x0000001c
|
||||
32'h06c06313, // 0x00000020
|
||||
32'h00628023, // 0x00000024
|
||||
32'h06f06313, // 0x00000028
|
||||
32'h00628023, // 0x0000002c
|
||||
32'h00a06313, // 0x00000030
|
||||
32'h00628023, // 0x00000034
|
||||
32'h00c003b7, // 0x00000038
|
||||
32'hfff38393, // 0x0000003c
|
||||
32'hfe039ee3, // 0x00000040
|
||||
32'hfc5ff06f // 0x00000044
|
||||
};
|
||||
|
||||
logic [29:0] cell_rd_addr;
|
||||
|
||||
@ -81,16 +81,16 @@ video_ram #(
|
||||
// 3<><33>?5从<35>?<3F>线仲裁<E4BBB2><E8A381>?
|
||||
//
|
||||
// 主（越靠前优先级越高）：
|
||||
// 0. UART调试<EFBFBD><EFBFBD>?
|
||||
// 1. Core Instr Master
|
||||
// 2. Core Data Master
|
||||
// 0. UART Debugger?
|
||||
// 1. Core Data Master
|
||||
// 2. Core Instruction Master
|
||||
//
|
||||
// 从：
|
||||
// 1. 指令ROM<4F><4D>? 地址空间 00000000~00000fff
|
||||
// 2. 指令RAM<41><4D>? 地址空间 00008000~00008fff
|
||||
// 3. 数据RAM<41><4D>? 地址空间 00010000~00010fff
|
||||
// 4. 显存RAM<41><4D>? 地址空间 00020000~00020fff
|
||||
// 5. 用户UART，地<EFBFBD><EFBFBD>?空间 00030000~00030003
|
||||
// 5. 用户UART， 地址空间 00030000~00030003
|
||||
naive_bus_router #(
|
||||
.N_MASTER ( 3 ),
|
||||
.N_SLAVE ( 5 ),
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3231:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3234:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00
|
||||
@ -11,8 +11,8 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f74797065:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:313336:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3434:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:313539:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3439:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6970636f7265766965775f7461626265645f70616e65:32:00:00
|
||||
@ -22,7 +22,7 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746f6f6c73:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f76696577:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f77696e646f77:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e746f6f6c6261726d67725f72756e:3136:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e746f6f6c6261726d67725f72756e:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e77696e6d656e756d67725f6c61796f7574:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d657373616765776974686f7074696f6e6469616c6f675f646f6e745f73686f775f746869735f6469616c6f675f616761696e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f7365766572697479:32:00:00
|
||||
@ -30,21 +30,21 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f637269746963616c5f7761726e696e6773:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f7761726e696e675f6d65737361676573:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e65746c69737474726565766965775f6e65746c6973745f74726565:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:3134:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f676f746f5f6e65746c6973745f64657369676e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6c6963656e73655f6d616e616765:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7265706f7274735f77696e646f77:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f62697467656e:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f62697467656e:3133:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f696d706c656d656e746174696f6e:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f73796e746865736973:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f73796e746865736973:3133:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7365745f61735f746f70:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f646576696365:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061727463686f6f7365725f66616d696c795f63686f6f736572:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061727463686f6f7365725f7061727473:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f737065636966795f62697473747265616d5f66696c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f63686f6f73655f70726f6a6563745f6c6f636174696f6e:31:00:00
|
||||
@ -58,7 +58,7 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f73686f775f7761726e696e675f616e645f6572726f725f6d657373616765735f696e5f6d65737361676573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f63616e63656c:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f726566726573685f686965726172636879:31:00:00
|
||||
@ -66,6 +66,6 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73746174656d6f6e69746f725f72657365745f72756e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:746f756368706f696e747375727665796469616c6f675f6e6f:31:00:00
|
||||
eof:4106945434
|
||||
eof:1976891599
|
||||
|
||||
@ -1,21 +1,21 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f726576696577:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:3139:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:3331:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:3335:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:3230:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265706f72747574696c697a6174696f6e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:3133:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:3133:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766566696c6570726f787968616e646c6572:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574746f706e6f6465:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7570646174657265676964:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b73796e746865736973:32:00:00
|
||||
eof:3430014336
|
||||
eof:3926706254
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
version:1
|
||||
57656254616c6b5472616e736d697373696f6e417474656d70746564:7
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:12
|
||||
57656254616c6b5472616e736d697373696f6e417474656d70746564:8
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:15
|
||||
eof:
|
||||
|
||||
@ -33,7 +33,7 @@ version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a333073:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313036372e3932324d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3737382e3639394d42:00:00
|
||||
eof:3866055585
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a313673:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:3939352e3534374d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3730362e3030344d42:00:00
|
||||
eof:1494114757
|
||||
|
||||
@ -3,10 +3,10 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Wed Mar 6 16:26:52 2019">
|
||||
<application name="pa" timeStamp="Sun Mar 10 22:14:56 2019">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="802f49394334431ea9abba122e836e9e" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="20" type="ProjectIteration"/>
|
||||
<property name="ProjectIteration" value="24" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
@ -17,20 +17,20 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddSources" value="7" type="JavaHandler"/>
|
||||
<property name="AutoConnectTarget" value="8" type="JavaHandler"/>
|
||||
<property name="AddSources" value="8" type="JavaHandler"/>
|
||||
<property name="AutoConnectTarget" value="9" type="JavaHandler"/>
|
||||
<property name="CoreView" value="1" type="JavaHandler"/>
|
||||
<property name="CustomizeCore" value="1" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="5" type="JavaHandler"/>
|
||||
<property name="LaunchProgramFpga" value="17" type="JavaHandler"/>
|
||||
<property name="LaunchProgramFpga" value="19" type="JavaHandler"/>
|
||||
<property name="NewProject" value="1" type="JavaHandler"/>
|
||||
<property name="OpenHardwareManager" value="31" type="JavaHandler"/>
|
||||
<property name="OpenRecentTarget" value="9" type="JavaHandler"/>
|
||||
<property name="ProgramDevice" value="18" type="JavaHandler"/>
|
||||
<property name="OpenHardwareManager" value="35" type="JavaHandler"/>
|
||||
<property name="OpenRecentTarget" value="10" type="JavaHandler"/>
|
||||
<property name="ProgramDevice" value="20" type="JavaHandler"/>
|
||||
<property name="ReportUtilization" value="1" type="JavaHandler"/>
|
||||
<property name="RunBitgen" value="11" type="JavaHandler"/>
|
||||
<property name="RunImplementation" value="8" type="JavaHandler"/>
|
||||
<property name="RunSynthesis" value="11" type="JavaHandler"/>
|
||||
<property name="RunBitgen" value="13" type="JavaHandler"/>
|
||||
<property name="RunImplementation" value="10" type="JavaHandler"/>
|
||||
<property name="RunSynthesis" value="13" type="JavaHandler"/>
|
||||
<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/>
|
||||
<property name="SetTopNode" value="2" type="JavaHandler"/>
|
||||
<property name="ShowView" value="8" type="JavaHandler"/>
|
||||
@ -40,7 +40,7 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<item name="Gui Handlers">
|
||||
<property name="AddSrcWizard_SPECIFY_HDL_NETLIST_BLOCK_DESIGN" value="2" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CANCEL" value="5" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="21" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="24" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="1" type="GuiHandlerData"/>
|
||||
<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="2" type="GuiHandlerData"/>
|
||||
<property name="ConstraintsChooserPanel_ADD_FILES" value="1" type="GuiHandlerData"/>
|
||||
@ -50,8 +50,8 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="CreateSrcFileDialog_FILE_TYPE" value="1" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="136" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="44" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="159" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="49" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="7" type="GuiHandlerData"/>
|
||||
<property name="IPCoreView_TABBED_PANE" value="2" type="GuiHandlerData"/>
|
||||
@ -61,7 +61,7 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="MainMenuMgr_TOOLS" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_VIEW" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_WINDOW" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainToolbarMgr_RUN" value="16" type="GuiHandlerData"/>
|
||||
<property name="MainToolbarMgr_RUN" value="18" type="GuiHandlerData"/>
|
||||
<property name="MainWinMenuMgr_LAYOUT" value="2" type="GuiHandlerData"/>
|
||||
<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_SEVERITY" value="2" type="GuiHandlerData"/>
|
||||
@ -69,21 +69,21 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="MsgView_CRITICAL_WARNINGS" value="5" type="GuiHandlerData"/>
|
||||
<property name="MsgView_WARNING_MESSAGES" value="2" type="GuiHandlerData"/>
|
||||
<property name="NetlistTreeView_NETLIST_TREE" value="15" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_SOURCES" value="7" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="8" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_SOURCES" value="8" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="9" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_UPDATE_HIER" value="14" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GOTO_NETLIST_DESIGN" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_LICENSE_MANAGE" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_REPORTS_WINDOW" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_BITGEN" value="11" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_BITGEN" value="13" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_IMPLEMENTATION" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_SYNTHESIS" value="11" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_SYNTHESIS" value="13" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SET_AS_TOP" value="2" type="GuiHandlerData"/>
|
||||
<property name="PAViews_CODE" value="11" type="GuiHandlerData"/>
|
||||
<property name="PAViews_DEVICE" value="2" type="GuiHandlerData"/>
|
||||
<property name="PartChooser_FAMILY_CHOOSER" value="1" type="GuiHandlerData"/>
|
||||
<property name="PartChooser_PARTS" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProgramFpgaDialog_PROGRAM" value="15" type="GuiHandlerData"/>
|
||||
<property name="ProgramFpgaDialog_PROGRAM" value="17" type="GuiHandlerData"/>
|
||||
<property name="ProgramFpgaDialog_SPECIFY_BITSTREAM_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="1" type="GuiHandlerData"/>
|
||||
@ -97,7 +97,7 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="RunGadget_SHOW_WARNING_AND_ERROR_MESSAGES_IN_MESSAGES" value="1" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_SAVE" value="2" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="4" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="5" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_HIERARCHY" value="11" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_REFRESH_HIERARCHY" value="1" type="GuiHandlerData"/>
|
||||
@ -105,14 +105,9 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="StateMonitor_RESET_RUN" value="1" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="6" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaStateMonitor_CANCEL" value="2" type="GuiHandlerData"/>
|
||||
<property name="TaskBanner_CLOSE" value="1" type="GuiHandlerData"/>
|
||||
<property name="TaskBanner_CLOSE" value="2" type="GuiHandlerData"/>
|
||||
<property name="TouchpointSurveyDialog_NO" value="1" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="33" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="29" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
|
||||
@ -10,7 +10,7 @@
|
||||
<Properties Property="FULL_PROBES.FILE" value=""/>
|
||||
<Properties Property="PROBES.FILE" value=""/>
|
||||
<Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/Nexys4_USTCRVSoC_top.bit"/>
|
||||
<Properties Property="SLR.COUNT" value="C:/Users/wgg/AppData/Roaming/Xilinx/Vivado/1"/>
|
||||
<Properties Property="SLR.COUNT" value="1"/>
|
||||
</Object>
|
||||
</ObjectList>
|
||||
<probeset name="hw project" active="false"/>
|
||||
|
||||
@ -83,6 +83,13 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_id_segreg.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_id_stage.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
|
||||
@ -2,24 +2,22 @@
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Tue Mar 5 19:07:42 2019
|
||||
# Process ID: 4532
|
||||
# Start of session at: Sun Mar 10 22:06:31 2019
|
||||
# Process ID: 17240
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent12668 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11140 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
update_compile_order -fileset sources_1
|
||||
open_hw
|
||||
connect_hw_server
|
||||
open_hw_target
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
current_hw_device [get_hw_devices xc7a100t_0]
|
||||
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
program_hw_devices [get_hw_devices xc7a100t_0]
|
||||
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
add_files -norecurse E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv
|
||||
update_compile_order -fileset sources_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 8
|
||||
wait_on_run synth_1
|
||||
launch_runs impl_1 -jobs 8
|
||||
wait_on_run impl_1
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
wait_on_run impl_1
|
||||
|
||||
@ -0,0 +1,38 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Sat Mar 9 11:23:21 2019
|
||||
# Process ID: 13384
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent10732 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
update_compile_order -fileset sources_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 8
|
||||
wait_on_run synth_1
|
||||
launch_runs impl_1 -jobs 8
|
||||
wait_on_run impl_1
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
wait_on_run impl_1
|
||||
open_hw
|
||||
connect_hw_server
|
||||
open_hw_target
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
current_hw_device [get_hw_devices xc7a100t_0]
|
||||
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
program_hw_devices [get_hw_devices xc7a100t_0]
|
||||
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
program_hw_devices [get_hw_devices xc7a100t_0]
|
||||
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
close_hw
|
||||
@ -0,0 +1,25 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Tue Mar 5 19:07:42 2019
|
||||
# Process ID: 4532
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent12668 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
update_compile_order -fileset sources_1
|
||||
open_hw
|
||||
connect_hw_server
|
||||
open_hw_target
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
current_hw_device [get_hw_devices xc7a100t_0]
|
||||
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
program_hw_devices [get_hw_devices xc7a100t_0]
|
||||
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
191
hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado_pid17240.str
Normal file
191
hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado_pid17240.str
Normal file
@ -0,0 +1,191 @@
|
||||
/*
|
||||
|
||||
Xilinx Vivado v2017.4 (64-bit) [Major: 2017, Minor: 4]
|
||||
SW Build: 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
IP Build: 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
|
||||
Process ID: 17240
|
||||
License: Customer
|
||||
|
||||
Current time: Sun Mar 10 22:06:47 CST 2019
|
||||
Time zone: China Standard Time (Asia/Shanghai)
|
||||
|
||||
OS: Windows 10
|
||||
OS Version: 10.0
|
||||
OS Architecture: amd64
|
||||
Available processors (cores): 12
|
||||
|
||||
Screen size: 1536x864
|
||||
Screen resolution (DPI): 96
|
||||
Available screens: 2
|
||||
Available disk space: 103 GB
|
||||
Default font: family=Dialog,name=Dialog,style=plain,size=12
|
||||
|
||||
Java version: 1.8.0_112 64-bit
|
||||
Java home: C:/Xilinx/Vivado/2017.4/tps/win64/jre
|
||||
JVM executable location: C:/Xilinx/Vivado/2017.4/tps/win64/jre/bin/java.exe
|
||||
|
||||
User name: wgg
|
||||
User home directory: C:/Users/wgg
|
||||
User working directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
User country: CN
|
||||
User language: zh
|
||||
User locale: zh_CN
|
||||
|
||||
RDI_BASEROOT: C:/Xilinx/Vivado
|
||||
HDI_APPROOT: C:/Xilinx/Vivado/2017.4
|
||||
RDI_DATADIR: C:/Xilinx/Vivado/2017.4/data
|
||||
RDI_BINDIR: C:/Xilinx/Vivado/2017.4/bin
|
||||
|
||||
Vivado preferences file location: C:/Users/wgg/AppData/Roaming/Xilinx/Vivado/2017.4/vivado.xml
|
||||
Vivado preferences directory: C:/Users/wgg/AppData/Roaming/Xilinx/Vivado/2017.4/
|
||||
Vivado layouts directory: C:/Users/wgg/AppData/Roaming/Xilinx/Vivado/2017.4/layouts
|
||||
PlanAhead jar file location: C:/Xilinx/Vivado/2017.4/lib/classes/planAhead.jar
|
||||
Vivado log file location: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
Vivado journal file location: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.jou
|
||||
Engine tmp dir: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/.Xil/Vivado-17240-DESKTOP-C6I6OAQ
|
||||
|
||||
GUI allocated memory: 189 MB
|
||||
GUI max memory: 3,052 MB
|
||||
Engine allocated memory: 547 MB
|
||||
|
||||
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
*/
|
||||
|
||||
// TclEventType: START_GUI
|
||||
// Tcl Message: start_gui
|
||||
// TclEventType: PROJECT_OPEN_DIALOG
|
||||
// [GUI Memory]: 50 MB (+50319kb) [00:00:05]
|
||||
// [Engine Memory]: 467 MB (+338389kb) [00:00:05]
|
||||
// Opening Vivado Project: E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr. Version: Vivado v2017.4
|
||||
// bs (cj): Open Project : addNotify
|
||||
// TclEventType: DEBUG_PROBE_SET_CHANGE
|
||||
// Tcl Message: open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
// TclEventType: MSGMGR_MOVEMSG
|
||||
// TclEventType: FILE_SET_NEW
|
||||
// TclEventType: RUN_COMPLETED
|
||||
// TclEventType: RUN_CURRENT
|
||||
// TclEventType: PROJECT_NEW
|
||||
// [GUI Memory]: 61 MB (+8814kb) [00:00:07]
|
||||
// [Engine Memory]: 545 MB (+56806kb) [00:00:07]
|
||||
// Tcl Message: open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
// Tcl Message: Scanning sources... Finished scanning sources
|
||||
// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
// TclEventType: PROJECT_NEW
|
||||
// [Engine Memory]: 602 MB (+31924kb) [00:00:09]
|
||||
// [GUI Memory]: 82 MB (+18518kb) [00:00:10]
|
||||
// [GUI Memory]: 90 MB (+3516kb) [00:00:11]
|
||||
// [Engine Memory]: 666 MB (+35411kb) [00:00:11]
|
||||
// [GUI Memory]: 96 MB (+1685kb) [00:00:11]
|
||||
// Tcl Message: INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 677 MB. GUI used memory: 45 MB. Current time: 3/10/19 10:06:52 PM CST
|
||||
// Tcl Message: open_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 850.613 ; gain = 135.648
|
||||
// Project name: USTCRVSoC-nexys4; location: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4; part: xc7a100tcsg324-1
|
||||
dismissDialog("Open Project"); // bs (cj)
|
||||
// TclEventType: DG_ANALYSIS_MSG_RESET
|
||||
// TclEventType: DG_GRAPH_GENERATED
|
||||
// Tcl Message: update_compile_order -fileset sources_1
|
||||
// Elapsed time: 30 seconds
|
||||
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Nexys4_USTCRVSoC_top (Nexys4_USTCRVSoC_top.sv)]", 1); // B (D, cj)
|
||||
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Nexys4_USTCRVSoC_top (Nexys4_USTCRVSoC_top.sv), soc_inst : soc_top (soc_top.sv)]", 2); // B (D, cj)
|
||||
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Nexys4_USTCRVSoC_top (Nexys4_USTCRVSoC_top.sv), soc_inst : soc_top (soc_top.sv), core_top_inst : core_top (core_top.sv)]", 4); // B (D, cj)
|
||||
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Nexys4_USTCRVSoC_top (Nexys4_USTCRVSoC_top.sv), soc_inst : soc_top (soc_top.sv), core_top_inst : core_top (core_top.sv)]", 4, true, false, false, false, true, false); // B (D, cj) - Popup Trigger - Node
|
||||
selectMenuItem(PAResourceCommand.PACommandNames_ADD_SOURCES, "Add Sources..."); // ac (ai, cj)
|
||||
// Run Command: PAResourceCommand.PACommandNames_ADD_SOURCES
|
||||
// c (cj): Add Sources: addNotify
|
||||
selectButton("NEXT", "Next >"); // JButton (h, c)
|
||||
selectButton(PAResourceQtoS.SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT, "Add Files"); // a (C, c)
|
||||
// Elapsed time: 17 seconds
|
||||
setFileChooser("E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv");
|
||||
selectButton("FINISH", "Finish"); // JButton (h, c)
|
||||
// 'h' command handler elapsed time: 23 seconds
|
||||
dismissDialog("Add Sources"); // c (cj)
|
||||
// TclEventType: DG_GRAPH_STALE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// Tcl Message: add_files -norecurse E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv
|
||||
// TclEventType: DG_ANALYSIS_MSG_RESET
|
||||
// TclEventType: DG_GRAPH_GENERATED
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// Tcl Message: update_compile_order -fileset sources_1
|
||||
// [Engine Memory]: 701 MB (+1885kb) [00:01:18]
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 708 MB. GUI used memory: 48 MB. Current time: 3/10/19 10:08:00 PM CST
|
||||
// Elapsed time: 11 seconds
|
||||
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Nexys4_USTCRVSoC_top (Nexys4_USTCRVSoC_top.sv)]", 1, true); // B (D, cj) - Node
|
||||
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Nexys4_USTCRVSoC_top (Nexys4_USTCRVSoC_top.sv)]", 1, true); // B (D, cj) - Node
|
||||
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Nexys4_USTCRVSoC_top (Nexys4_USTCRVSoC_top.sv)]", 1, true, false, false, false, false, true); // B (D, cj) - Double Click - Node
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 205, 261); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 205, 261, false, false, false, false, true); // cd (w, cj) - Double Click
|
||||
// Elapsed time: 15 seconds
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 242, 202); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 242, 202, false, false, false, false, true); // cd (w, cj) - Double Click
|
||||
selectButton(PAResourceItoN.MainToolbarMgr_RUN, (String) null); // aw (f, cj)
|
||||
selectMenuItem(PAResourceCommand.PACommandNames_RUN_SYNTHESIS, "Run Synthesis"); // ac (cj)
|
||||
// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
|
||||
// bs (cj): Resetting Runs : addNotify
|
||||
// TclEventType: RUN_MODIFY
|
||||
// TclEventType: RUN_RESET
|
||||
// TclEventType: RUN_MODIFY
|
||||
// Tcl Message: reset_run synth_1
|
||||
// bs (cj): Starting Design Runs : addNotify
|
||||
// TclEventType: RUN_LAUNCH
|
||||
// TclEventType: RUN_MODIFY
|
||||
// Tcl Message: launch_runs synth_1 -jobs 8
|
||||
// Tcl Message: [Sun Mar 10 22:08:28 2019] Launched synth_1... Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1/runme.log
|
||||
dismissDialog("Starting Design Runs"); // bs (cj)
|
||||
// TclEventType: RUN_COMPLETED
|
||||
// WARNING: HTimer (ActiveMsgMonitor Process Messages Timer) is taking too long to process. Increasing delay to 2000 ms.
|
||||
// ah (cj): Synthesis Completed: addNotify
|
||||
// Elapsed time: 178 seconds
|
||||
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (ah)
|
||||
// Run Command: PAResourceCommand.PACommandNames_RUN_IMPLEMENTATION
|
||||
// bs (cj): Starting Design Runs : addNotify
|
||||
// TclEventType: RUN_LAUNCH
|
||||
// TclEventType: RUN_MODIFY
|
||||
// Tcl Message: launch_runs impl_1 -jobs 8
|
||||
// Tcl Message: [Sun Mar 10 22:11:27 2019] Launched impl_1... Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/runme.log
|
||||
dismissDialog("Starting Design Runs"); // bs (cj)
|
||||
// TclEventType: RUN_STEP_COMPLETED
|
||||
// Elapsed time: 133 seconds
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 198, 90); // cd (w, cj)
|
||||
selectCodeEditor("Nexys4_USTCRVSoC_top.sv", 198, 90, false, false, false, false, true); // cd (w, cj) - Double Click
|
||||
// TclEventType: RUN_COMPLETED
|
||||
// Elapsed time: 74 seconds
|
||||
selectButton(PAResourceCommand.PACommandNames_RUN_BITGEN, "run_bitstream"); // B (f, cj)
|
||||
// Run Command: PAResourceCommand.PACommandNames_RUN_BITGEN
|
||||
// TclEventType: RUN_LAUNCH
|
||||
// TclEventType: RUN_MODIFY
|
||||
// Tcl Message: launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
// Tcl Message: [Sun Mar 10 22:14:56 2019] Launched impl_1... Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/runme.log
|
||||
// HMemoryUtils.trashcanNow. Engine heap size: 734 MB. GUI used memory: 51 MB. Current time: 3/10/19 10:15:00 PM CST
|
||||
// TclEventType: RUN_FAILED
|
||||
// ah (cj): Bitstream Generation Failed: addNotify
|
||||
// Elapsed time: 56 seconds
|
||||
selectButton(RDIResource.BaseDialog_OK, "OK"); // a (ah)
|
||||
// Run Command: PAResourceCommand.PACommandNames_LOG_WINDOW
|
||||
dismissDialog("Bitstream Generation Failed"); // ah (cj)
|
||||
selectTab((HResource) null, (HResource) null, "Messages", 1); // aF (Q, cj)
|
||||
selectCheckBox(PAResourceItoN.MsgView_CRITICAL_WARNINGS, (String) null, false); // g (aQ, cj): FALSE
|
||||
// Elapsed time: 15 seconds
|
||||
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Nexys4_USTCRVSoC_top (Nexys4_USTCRVSoC_top.sv)]", 1); // B (D, cj)
|
||||
expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Nexys4_USTCRVSoC_top (Nexys4_USTCRVSoC_top.sv), soc_inst : soc_top (soc_top.sv)]", 2); // B (D, cj)
|
||||
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Nexys4_USTCRVSoC_top (Nexys4_USTCRVSoC_top.sv), soc_inst : soc_top (soc_top.sv), core_top_inst : core_top (core_top.sv)]", 4, true); // B (D, cj) - Node
|
||||
selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Nexys4_USTCRVSoC_top (Nexys4_USTCRVSoC_top.sv), soc_inst : soc_top (soc_top.sv), core_top_inst : core_top (core_top.sv), inst_bus_wrap_inst : core_id_segreg (core_id_segreg.sv)]", 5, false, false, false, false, false, true); // B (D, cj) - Double Click
|
||||
selectCodeEditor("core_top.sv", 268, 75); // cd (w, cj)
|
||||
selectCodeEditor("core_top.sv", 268, 75, false, false, false, false, true); // cd (w, cj) - Double Click
|
||||
selectCodeEditor("core_top.sv", 261, 66); // cd (w, cj)
|
||||
selectCodeEditor("core_top.sv", 262, 66, false, false, false, false, true); // cd (w, cj) - Double Click
|
||||
selectCodeEditor("core_top.sv", 88, 123); // cd (w, cj)
|
||||
selectCodeEditor("core_top.sv", 88, 123, false, false, false, false, true); // cd (w, cj) - Double Click
|
||||
selectCodeEditor("core_top.sv", 111, 158); // cd (w, cj)
|
||||
selectCodeEditor("core_top.sv", 111, 158, false, false, false, false, true); // cd (w, cj) - Double Click
|
||||
// [GUI Memory]: 100 MB (+35kb) [00:13:44]
|
||||
// TclEventType: DG_GRAPH_STALE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: DG_ANALYSIS_MSG_RESET
|
||||
// TclEventType: DG_GRAPH_GENERATED
|
||||
// TclEventType: DG_GRAPH_STALE
|
||||
// TclEventType: FILE_SET_CHANGE
|
||||
// TclEventType: DG_ANALYSIS_MSG_RESET
|
||||
// TclEventType: DG_GRAPH_GENERATED
|
||||
// [GUI Memory]: 106 MB (+100kb) [00:20:06]
|
||||
27
software/asm-code/basic-test/big_endian_little_endian.S
Normal file
27
software/asm-code/basic-test/big_endian_little_endian.S
Normal file
@ -0,0 +1,27 @@
|
||||
# 概述：判断系统的存储结构是大端序还是小端序
|
||||
# 如果为大端序则t0寄存器置 0x00000001，且DataRam第五个字节置0x01
|
||||
# 如果为小端序则t0寄存器置 0x00000002，且DataRam第五个字节置0x02
|
||||
# Author: WangXuan
|
||||
#
|
||||
#
|
||||
#
|
||||
# 系统要求：1、具有一个数据RAM （该程序中，其高地址用作栈）
|
||||
# 2、请根据实际情况将a0设置为你的DataRam的地址，例如我的SoC DataRam起始地址为0x00010000，则我第一个指令是lui sp, 0x00010
|
||||
#
|
||||
|
||||
|
||||
.org 0x0
|
||||
.global _start
|
||||
_start:
|
||||
|
||||
lui a0, 0x00010
|
||||
lui t1, 0x01000
|
||||
ori t1, t1, 0x002
|
||||
sw t1, (a0)
|
||||
lb t0, (a0)
|
||||
sb t0, 5(a0)
|
||||
|
||||
here:
|
||||
jal zero, here # 死循环
|
||||
|
||||
|
||||
@ -1,20 +0,0 @@
|
||||
|
||||
.org 0x0
|
||||
.global _start
|
||||
_start:
|
||||
|
||||
lui a0, 0x00010
|
||||
addi t2, zero, 0x04 # t2 = 4
|
||||
sw t2, 8(a0) # (0x00010008) = 4
|
||||
addi t1, a0, 0x08 # t1=0x00010008
|
||||
lw t1, (t1) # t1 = 4
|
||||
blt t1, t2, next # if t1<t2, branch to next step
|
||||
beq t1, t2, next # if t1=t2, branch to next step
|
||||
addi t2, t2, -4 # t2-=4
|
||||
jal zero, _start
|
||||
next:
|
||||
add t0 , a0, t1 # t0=0x00010004
|
||||
sw t2 , (t0) # (0x00010004) = 4
|
||||
here:
|
||||
jal zero, here
|
||||
|
||||
@ -41,13 +41,13 @@ tag:
|
||||
addi sp, sp, -4 # sp-=4 # push t0 to stack
|
||||
sw t0, (sp) # mem[sp] = t0
|
||||
|
||||
jal ra, Fibonacci # 计算 Fib(n-1)
|
||||
jal ra, Fibonacci # 计算 Fib(n-1)
|
||||
|
||||
lw t0, (sp) # t0=mem[sp] # pop t0 from stack
|
||||
addi t0, t0, -1 # t0--
|
||||
|
||||
sw t1, (sp) # mem[sp] = t1
|
||||
jal ra, Fibonacci # 计算 Fib(n-2)
|
||||
jal ra, Fibonacci # 计算 Fib(n-2)
|
||||
lw t2, (sp) # ra=mem[sp] # pop t2 from stack
|
||||
addi sp, sp, 4 # sp+=4
|
||||
add t1, t1, t2 # t1+=t2
|
||||
|
||||
@ -12,8 +12,9 @@
|
||||
_start:
|
||||
|
||||
main: # main函数开始，在DataRam里初始化一段数据，然后调用QuickSort进行排序，排序后进入死循环。请使用仿真或UART调试器查看排序后的数据
|
||||
lui a0, 0x00020 # 设置DataRam的起始地址为0x00010000，也用作被排序数组的起始地址是，即DataRam的起始地址
|
||||
lui a0, 0x00010 # 设置DataRam的起始地址为0x00010000，也用作被排序数组的起始地址是，即DataRam的起始地址
|
||||
addi sp, a0 , 0x400 # 设置栈顶指针
|
||||
|
||||
or a2, a0, zero
|
||||
|
||||
addi t0, zero, -3 # 用一系列指令向a0里写入被排序的数组，可以是负数
|
||||
|
||||
106
software/asm-code/calculation-test/SimpleSprintf.S
Normal file
106
software/asm-code/calculation-test/SimpleSprintf.S
Normal file
@ -0,0 +1,106 @@
|
||||
# 概述：实现一个简单的 sprintf 函数，支持 %c %s %u %d 格式化串
|
||||
# 以 a0 寄存器为目的地址，a1 寄存器为格式字符串地址，a2为起始指针的内存里有待格式化的参数，所有参数以4字节对齐
|
||||
# Author: WangXuan
|
||||
#
|
||||
# 系统要求：1、具有一个大小至少为0x400 Byte的数据RAM （该程序中，其高地址用作栈，低地址用作被排序的数组）
|
||||
# 2、测试该代码时，不需要初始化DataRam，只需要将指令流烧入InstrRam。因为有一系列指令去准备被排序的数组。
|
||||
# 3、请根据实际情况将a0设置为你的DataRam的地址，例如我的SoC DataRam起始地址为0x00010000，则第一条指令就是 lui a0, 0x00010
|
||||
#
|
||||
|
||||
|
||||
.org 0x0
|
||||
.global _start
|
||||
_start:
|
||||
|
||||
main: # main函数开始，在DataRam里初始化一段数据
|
||||
lui a0, 0x00020 # 设置DataRam的起始地址为0x00020000，即显存RAM，也用作
|
||||
lui a2, 0x00010
|
||||
addi sp, a2 , 0x400 # 设置栈顶指针 = 0x00010400
|
||||
|
||||
auipc a1, 0x00000 # 获取当前的PC值，目的是能够推算出以下的.string的起始地址
|
||||
jal zero, AfterString1 # 跳转到以下.string 之后，因为string是一个指令RAM中的数据，不能被执行
|
||||
.string "(a2):%s (a2+4):%c\0" # 在指令RAM中实现一个string，该string作为sprintf的格式串，在之后调用sprintf时被使用，为了与C语言sprintf一致，显式规定以\0结尾
|
||||
|
||||
.align 4 # 下一条指令以4字节对齐
|
||||
AfterString1:
|
||||
addi a1, a1, 0x08 # 将a1+8,以得到真正的.string的起始地址
|
||||
|
||||
auipc a3, 0x00000 # 获取当前的PC值，目的是能够推算出以下的.string的起始地址
|
||||
jal zero, AfterString2 # 跳转到以下.string 之后，因为string是一个指令RAM中的数据，不能被执行
|
||||
.string "hello!\0" # 在指令RAM中实现另一个string
|
||||
.align 4 # 下一条指令以4字节对齐
|
||||
AfterString2:
|
||||
addi a3, a3 , 0x08 # 将a3+8,以得到真正的.string的起始地址
|
||||
|
||||
sw a3, (a2)
|
||||
ori a3, zero, 'a'
|
||||
sw a3, 4(a2)
|
||||
jal ra, SimpleSprintf
|
||||
infinity_loop:
|
||||
jal zero, infinity_loop # 死循环
|
||||
|
||||
|
||||
SimpleSprintf:
|
||||
# 以 a0 寄存器为目的地址，a1 寄存器为格式字符串地址，a2为起始指针的内存里有待格式化的参数，所有参数以4字节对齐
|
||||
# 在调用该函数时，需要准备a0，a1两个寄存器，并在栈中从后向前的(cdecl调用顺序) push 参数
|
||||
or t0, zero, zero # t0 清零
|
||||
SimpleSprintfLoopStart:
|
||||
or t1, t0, zero # 备份t0到t1
|
||||
lbu t0, (a1)
|
||||
sb t0, (a0)
|
||||
addi a1, a1, 1
|
||||
addi a0, a0, 1
|
||||
bne t0, zero, DontReturn # 如果没遇到遇到\0，就跳过函数返回
|
||||
jalr zero, ra, 0 # 遇到\0，函数返回
|
||||
DontReturn:
|
||||
ori t2, zero, '%'
|
||||
bne t1, t2, SimpleSprintfLoopStart # 如果t1!='%'，说明还没碰到需要格式化打印的情况，跳到函数开始去循环执行
|
||||
|
||||
addi a0, a0, -1 # 目的字符串指针回退一步，回到%之后
|
||||
ori t2, zero, 'c'
|
||||
bne t0, t2, NotC
|
||||
lw t2, (a2) # 从a2地址中获得一个参数
|
||||
addi a2, a2, 4
|
||||
sb t2, -1(a0) # 向目标字符串中写入
|
||||
jal zero, SimpleSprintfLoopStart
|
||||
|
||||
NotC:
|
||||
ori t2, zero, 's'
|
||||
bne t0, t2, NotS
|
||||
lw t2, (a2) # 从a2地址中获得一个参数
|
||||
addi a2, a2, 4
|
||||
StringCopystart:
|
||||
lbu t3, (t2)
|
||||
beq t3, zero, SimpleSprintfLoopStart
|
||||
addi t2, t2, 1
|
||||
sb t3, -1(a0)
|
||||
addi a0, a0, 1
|
||||
jal zero, StringCopystart
|
||||
|
||||
NotS:
|
||||
ori t2, zero, 'd'
|
||||
bne t0, t2, NotD
|
||||
lw t2, (a2) # 从a2地址中获得一个参数
|
||||
addi a2, a2, 4
|
||||
jal zero, SimpleSprintfLoopStart
|
||||
|
||||
NotD:
|
||||
ori t2, zero, 'u'
|
||||
bne t0, t2, NotU
|
||||
lw t2, (a2) # 从a2地址中获得一个参数
|
||||
addi a2, a2, 4
|
||||
jal zero, SimpleSprintfLoopStart
|
||||
|
||||
NotU:
|
||||
ori t2, zero, 'x'
|
||||
bne t0, t2, SimpleSprintfLoopStart
|
||||
lw t2, (a2) # 从a2地址中获得一个参数
|
||||
addi a2, a2, 4
|
||||
jal zero, SimpleSprintfLoopStart
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user