diff --git a/README.md b/README.md index 872e2c3..de896c3 100644 --- a/README.md +++ b/README.md @@ -1,27 +1,25 @@ # USTCRVSoC -一个用SystemVerilog编写的，基于RISC-V的，普林斯顿结构的SoC +一个用 SystemVerilog 编写的，基于 RISC-V 的，普林斯顿结构的 SoC # 特点 -> * 5段流水线RISC-V，能运行RV32I指令集 -> * 简单直观的32bit握手总线 (naive_bus.sv)， -> * 总线仲裁器(naive_bus_router.sv)可修改，以方便拓展外设、多核、DMA等 -> * 具有交互式UART调试器(isp_uart.sv)，用户可以使用PC上的串口助手、minicom等软件，实现系统复位、上传程序、查看内存等功能 -> * 全部使用 SystemVerilog 实现，不调用IP核，方便在 Altera、Xilinx、Lattice 等不同FPGA平台上移植，也方便在各种工具中进行仿真 -> * RAM 和 ROM 符合一定的Verilog写法，自动综合成 Block RAM +* **CPU**：5段流水线 RISC-V ，能运行 **RV32I** 指令集中的大部分指令 +* **总线**：简单直观的，具有**握手机制**的，32-bit地址位宽和32-bit数据位宽的总线 +* **总线仲裁**：可使用宏定义修改，以方便拓展外设、DMA、多核等 +* **交互式 UART 调试**：支持使用PC上的Putty、串口助手、minicom等软件，实现**系统复位**、**上传程序**、**查看内存**等功能 +* **纯 RTL 实现**：完全使用SystemVerilog，不调用IP核，便于移植和仿真 +* RAM 和 ROM 符合一定的Verilog写法，**自动综合成 Block RAM** # SoC 结构 ![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/SoC.png) -上图展示了SoC的结构，总线仲裁器bus_router为SoC的中心，上面挂载了2个“主设备”和5个“从设备”。实际上，CPU具有两个“主接口”，因此bus_router共有3个“主接口”和5个“从接口”。 +上图展示了SoC的结构，总线仲裁器**bus_router**为SoC的中心，上面挂载了3个**主接口**和5个**从接口**。这个SoC使用的总线并不来自于任何标准（例如AXI或APB总线），而是笔者自编的，因为简单所以命名为**naive_bus**。 -这个SoC使用的总线并不来自于任何标准（例如AXI或APB总线），而是笔者自编的，因为简单所以命名为“naive_bus”。 +每个**从接口**都占有一段地址空间。当**主接口**访问总线时，**bus_router**判断该地址属于哪个地址空间，然后将它**路由**到相应的**从接口**。下表展示了5个**从接口**的地址空间。 -每个“从接口”都占有一段地址空间。当“主接口”访问总线时，bus_router判断该地址属于哪个地址空间，然后将它“路由”到相应的“从接口”。下表展示了5个“从接口”的地址空间。 - -| 外设类型 | 起始地址 | 结束地址 | +| 外设类型 | 起始地址 | 结束地址 | | :-----: | :-----: | :----: | | 指令ROM | 0x00000000 | 0x00007fff | | 指令RAM | 0x00008000 | 0x00008fff | @@ -29,87 +27,208 @@ | 显存RAM | 0x00020000 | 0x00020fff | | 用户UART | 0x00030000 | 0x00030003 | -### 主要部件 +### 组成部件 -> * **多主多从总线仲裁器(naive_bus_router.sv)**：为每个从设备划分地址空间，将主设备的总线读写请求路由到从设备。当多个主设备同时访问一个从设备时，还能进行访问冲突控制。 -> * **RV32I Core(core_top.sv)**：包括两个主接口。一个用于取指令，一个用于读写数据 -> * **UART调试器(isp_uart.sv)**：包括一个主接口和一个从接口。它接收用户从UART发来的命令，对总线进行读写。它可以用于在线烧写、在线调试。也可以接收CPU的命令去发送数据。 -> * **指令ROM(instr_rom.sv)**：CPU默认从这里开始取指令，多用于仿真 -> * **指令RAM(ram_bus_wrapper.sv)**：用户在线烧写程序到这里。 -> * **数据RAM(ram_bus_wrapper.sv)**：存放运行时的数据。 -> * **显存RAM(vedio_ram.sv)**：在屏幕上显示98列*36行=3528个字符，显存RAM的前3528B对应的ASCII码值就决定了每个字符是什么 +* **多主多从总线仲裁器**：对应文件 naive_bus_router.sv。为每个从设备划分地址空间，将主设备的总线读写请求路由到从设备。当多个主设备同时访问一个从设备时，还能根据主设备的优先级进行冲突仲裁。 +* **RV32I Core**：对应文件 core_top.sv。包括两个主接口。一个用于取指令，一个用于读写数据。 +* **UART调试器**：对应文件 isp_uart.sv。将UART调试功能和用户UART结合为一体。包括一个主接口和一个从接口。它接收上位机从UART发来的命令，对总线进行读写。它可以用于在线烧写、在线调试。也可以接收CPU的命令去发送数据给用户。 +* **指令ROM**：对应文件 instr_rom.sv。CPU默认从这里开始取指令，里面的指令流是在硬件代码编译综合时就固定的，不能在运行时修改。唯一的修改方法是编辑 **instr_rom.sv** 中的代码，然后重新编译综合、烧写FPGA逻辑。因此**instr_rom** 多用于仿真。 +* **指令RAM**：对应文件 ram_bus_wrapper.sv。用户使用 isp_uart 在线烧写指令流到这里，然后将 Boot 地址指向这里，再复位SoC后，CPU就从这里开始运行指令流。 +* **数据RAM**：对应文件 ram_bus_wrapper.sv。存放运行时的数据。 +* **显存RAM**：对应文件 vedio_ram.sv。在屏幕上显示 86列 * 32行 = 2752 个字符，显存 RAM 的 4096B 被划分为 32 个块，每块对应一行，占 128B，前 86 字节对应 86 个列。屏幕上显示的是每个字节作为 ASCII 码所对应的字符。 -# RV32I CPU 结构 -![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/Core-RTL.png) +# 部署 SoC 到 FPGA -TODO +目前，我们提供了 Xilinx 的 **Nexys4-DDR** 开发板和 Altera 的 **DE0-Nano** 开发板的工程。 -# 在开发板上运行SoC +为了进行部署和测试，你需要准备以下的东西： -我们提供了两种方式运行代码： +* 装有 **Windows7 系统** 或更高版本的 PC（如果使用 Linux 则很难用上我提供的几个C#编写的工具） +* **Nexys4-DDR** 开发板或 **DE0-Nano** 开发板或其它 FPGA 开发板 +* 开发板对应的 **RTL 开发环境**，例如 Nexys4-DDR 对应 Vivado（推荐 Vivado 2017.4 或更高版本），DE0-Nano 对应 Quartus （推荐Quartus II 11.1 或更高版本） +* 如果你的开发板没有自带 **USB转UART** 电路（例如 DE0-Nano 就不自带），则需要一个 **USB转UART模块**。 +* **可选**：* 屏幕、VGA线 * -1、**使用指令ROM**：修改instr_rom.sv中的代码，然后重新编译综合，重新烧写FPGA逻辑。虽然麻烦，但这便于进行RTL仿真，你可以将想要运行的程序放入指令ROM，然后仅需在testbench中给予SoC一个时钟，就可以观察整个SoC在运行这段代码时的波形。 +## 部署到 Nexys4-DDR -2、**使用指令RAM**：使用UART调试器在线上传程序到指令RAM。 +![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/nexys4-connection2.png) -### 部署电路到FPGA +1. **硬件连接**：如上图，Nexys4 开发板上有一个 USB 口既可以用于 FPGA 烧录，也可以用于 UART 通信，我们需要连接该 USB 口到电脑。另外，VGA 的连接是可选的，你可以把它连接到屏幕上。 +2. **综合、烧写**：请用 Vivado 打开 **./hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr**。综合并烧写到开发板。 -目前，我们提供了Xilinx的Nexys4板子和Altera的DE0-Nano板子的工程。 -1、**Nexys4硬件连接**：Nexys4开发板上有一个USB口既可以用于FPGA烧录，也可以用于UART通信，我们需要连接该USB口到电脑。另外，VGA的连接是可选的，你可以把它连接到屏幕上。 +## 部署到 DE0-Nano ![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/DE0-Nano.png) -2、**DE0-Nano硬件连接**：DE0-Nano开发板上既没有串口转USB，也没有VGA接口。因此都需要以来外部模块。我们使用DE0-Nano上的两排GPIO作为外接模块的引脚，接口意义如上图。你至少需要一个USB转UART的模块，将ISP-UART的TX和RX引脚连接上去，使之能与电脑通信，如下图： - +1、**硬件连接**：DE0-Nano开发板上既没有串口转USB，也没有VGA接口。因此需要外部模块，以及一些动手能力和硬件知识。我们使用DE0-Nano上的两排GPIO作为外接模块的引脚，接口意义如上图。你需要一个USB转UART的模块，将UART的TX和RX引脚连接上去，使之能与电脑通信。VGA的连接是可选的，需要符合上图中VGA的引脚定义。最后连接的效果如下图： ![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/connection.png) +2、**综合、烧写**：请用 Quartus 打开 **./hardware/Quartus/DE0_Nano/DE0_Nano.qpf**。综合并烧写到开发板。 -![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/usb_uart.png) +## 部署到其它开发板 -3、**综合、烧写FPGA**：如果你用的是Nexys4板子，请用Vivado打开./hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr。如果你用的是DE0-Nano板子，请用Quartus打开./hardware/Quartus/DE0_Nano/DE0_Nano.qpf。综合并烧写到开发板。 +如果很不幸，你手头的 FPGA 开发板既不是 Nexys4，也不是 DE0-Nano，则需要手动建立工程，连接信号到开发板顶层。分为以下步骤： -4、**HelloWorld**：烧录FPGA后，在电脑上的串口终端软件（超级终端、串口助手、minicom）中，使用格式(115200,n,8,1)打开串口，如果看到不断收到"hello\n"，那么恭喜你SoC部署成功，因为SoC的instr_rom里的程序就是循环打印hello的程序。 +* **建立工程**：建立工程后，需要将 **./hardware/RTL/** 中的所有 .sv 文件添加进工程。 +* **编写顶层**：SoC 的顶层文件是 **./hardware/RTL/soc_top.sv**，你需要编写一个针对该开发板的顶层文件，调用 **soc_top**，并将 FPGA 的引脚连接到 **soc_top** 中。以下是对 **soc_top** 的信号说明。 +* **编译、综合、烧写到FPGA** -5、**尝试读取总线**：下面让我们尝试UART的调试功能，首先发送"s\n"进入调试模式，可以看到对方发来"debug\n"，说明进入调试模式成功。然后，发送"00000000\n"，会看到对方发来一个8位16进制数。该数代表SoC数据总线的地址0x00000000处的读取数据。 +```Verilog +module soc_top #( + // UART接收分频系数，请根据clk的时钟频率决定，计算公式 UART_RX_CLK_DIV=clk频率(Hz)/460800，四舍五入 + parameter UART_RX_CLK_DIV = 108, + // UART发送分频系数，请根据clk的时钟频率决定，计算公式 UART_TX_CLK_DIV=clk频率(Hz)/115200，四舍五入 + parameter UART_TX_CLK_DIV = 434, + // VGA分频系数，请根据clk的时钟频率决定，计算公式 VGA_CLK_DIV=clk频率(Hz)/50000000 + parameter VGA_CLK_DIV = 1 +)( + input logic clk, // SoC 时钟，推荐使用 50MHz 的倍数 + input logic isp_uart_rx, // 连接到开发板的 UART RX 引脚 + output logic isp_uart_tx, // 连接到开发板的 UART TX 引脚 + output logic vga_hsync, vga_vsync, // 连接到VGA（可以不连接） + output logic vga_red, vga_green, vga_blue // 连接到VGA（可以不连接） +); +``` -6、上一步我们尝试了UART调试器的读总线命令，下表显示了它的所有3种命令。 -![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/commands.png) -> * 注意：无论是发送还是接受，所有命令都以\n或\r或\r\n结尾 +# 测试软件 + +硬件烧写后，开始对它进行测试 + +### 查看 Hello World + +硬件烧写后，如果你的开发板上有 UART 指示灯，就已经能看到 TX 指示灯在闪烁，每闪烁一下其实是在发送一个"Hello"，这说明CPU在运行指令ROM里默认的程序。下面我们来查看这个Hello。 + +首先我们需要一款**串口终端软件**，例如： +* minicom +* 串口助手 +* 超级终端 +* Putty + +这些工具用起来都不够爽快，因此这里使用该仓库中自带的小工具 **UartSession** 做示范。它的路径是 **./tools/UartSession.exe**。使用C#编写。 + +> UartSession.exe使用C#编写，VisualStudio 工程的路径是 **./UartSession-VS2012**。 + +首先，我们运行 **UartSession.exe**，可以看到该软件将电脑的所有可用端口都列了出来，并给出了几个选项： +* **打开端口**：输入数字，按回车可以打开数字对应的端口。 +* **修改波特率**：输入"baud [数字]"，再按回车可以修改波特率。例如输入baud 9600可以修改波特率为9600。 +* **刷新端口列表**：输入"refresh"，再按回车可以刷新端口列表。 +* **退出**：输入"exit"可以退出 + +![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/UartSession2.png) + +波特率默认是115200，与我们的 SoC 一致，不需要修改。直接从端口列表里找到 FPGA 开发板所对应的端口，打开它。我们就可以看到窗口中不断显示"hello"，根本停不下来，如上图，这说明CPU在正常运行程序。 + +> 如果不知道端口列表中哪个端口对应 FPGA 开发板，可以拔下开发板的 USB，刷新一次端口列表，则消失的端口就是开发板对应的端口。然后再插上USB（如果FPGA内的电路丢失则需要重新烧录FPGA） + + +### 使用 UART 调试总线 + +现在 **UartSession.exe** 界面中不断地打印出"hello"，我们打一个回车，可以看到对方不再打出"hello"，并出现了一个"debug"，这样就成功进入了 **DEBUG模式**。 + +![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/UartSession1.png) + +UART 调试器有两种模式： +* **USER 模式**：该模式下可以收到 CPU 通过 isp_uart 发送的用户打印数据。FPGA烧写后默认处于这个模式。hello只有在这个模式下才能被我们看到。通过向 uart **发送一个\n** 可以跳出 **USER模式**，进入DEBUG模式。 +* **DEBUG 模式**：该模式下 CPU 打印的任何数据都会被抑制，UART 不再主动发送数据，变成了**一问一答**的形式，用户发送的调试命令和接收到的应答都**以\n结尾**，通过发送"o"或系统复位可以回到 **USER模式**。 + +下面让我们尝试 **UART 的调试功能**，输入 **"0"** 并按回车，会看到对方发来一个8位16进制数。该数就是SoC总线的地址 0x00000000 处读取出的数据，也就是**指令ROM**中的第一个指令，如下图。 + +![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/UartSession3.png) + +当然我们也可以用调试器写总线，输入一条写命令： **"10000 abcd1234"** 并按回车，会看到对方发来**"wr done"**，意为写成功，该命令意为向地址 0x10000 中写入 0xabcd1234 (0x10000是数据RAM的首地址）。 + +为了验证写成功，输入读指令：**"10000"** 并按回车，会看到对方发来**"abcd1234"**。 + +> 注：UART 调试器每次读写总线只能以**4字节对齐**的形式，并且一次必须读写4字节。 + +下表显示了 **DEBUG模式** 的所有命令格式。 + +| 命令类型 | 命令格式 | 返回格式 | 命令示例 | 返回示例 | 含义 | +| :-----: | :-----: | :----: | :-----: | :-----: | :----: | +| 读总线 | [十六进制地址] | [十六进制数据] | 00020000 | abcd1234 | 地址0x00020000读出的数据是0xabcd1234 | +| 写总线 | [十六进制地址] [十六进制数据] | wr done | 00020004 1276acd0 | wr done | 向地址0x00020004写数据0x1276acd0 | +| 切换至调试模式 | o | user | o | user | 切换回USER模式 +| 复位 | r[十六进制boot地址] | rst done | r00008000 | rst done | CPU 复位并从地址 0x00008000 处开始执行，同时切换回 USER 模式 | +| 非法命令 | [其它格式] | invalid | ^^$aslfdi | invalid | 发送的指令未定义 | + +> 注：无论是发送还是接收，所有命令都以\n或\r或\r\n结尾，**UartSession.exe**是自动插入\n的。如果使用串口助手等其它软件，需要注意这个问题。 根据这些命令，不难猜出，在线上传程序的流程是： -> 1、使用写命令，将指令流写入指令RAM，（指令RAM的地址是00008000~00008fff） +1. 使用写命令，将指令流写入指令RAM，（指令RAM的地址是00008000~00008fff） +2. 使用复位命令r00008000，将CPU复位并从指令RAM中BOOT -> 2、使用复位命令r00008000，将CPU复位并从指令RAM中BOOT +### 使用 VGA 屏幕 -### 使用工具：USTCRVSoC-tool （该软件有所改动，文档稍后补充） +没有连接屏幕的可以跳过这一步。 -./USTCRVSoC-tool/USTCRVSoC-tool.exe 是一个能汇编和烧写的小工具，相当于一个汇编语言的IDE。 +如果开发板通过 VGA 连接到了屏幕，我们可以看到屏幕上出现一个红框，里面空空如也。实际上里面隐藏了 86列32行的字符空位。下面用 UART调试器 让屏幕上显示字符。 -我们提供了几个汇编小程序如下表。 +> 提示：如果屏幕中的红框不在正中间，可以使用屏幕的“自动校正”按钮校正一下 + +在**DEBUG模式**下，发送一条写命令： **"20000 31323334"** ，可以看到第一行出现了 **4321** 。这是因为显存RAM的起始地址是 0x20000，使用 UART调试器 正好向其中的前4个字节写入了 0x34、0x33、0x32、0x31，也就是**4321**的ASCII码。 + +显存 RAM 占 4096 字节，分为32个块，对应屏幕中的32个行；每块128B，前 86 字节对应该行中的前 86 个字符的 ASCII 码。后面128-86个字节不会显示在屏幕上。 + +显存 RAM 与 数据 RAM 行为相同，即可读又可写，但不能保证一个时钟周期一定能读出数据。 + +### 使用工具：USTCRVSoC-tool + +玩了好久的 UART调试，也该用 CPU 跑跑 benchmark 了。 + +**./software/asm-code** 中提供几个汇编语言的小程序作为 benchmark，如下表。 | 文件名 | 说明 | | :----- | :----- | -| uart_print.S | 用户UART循环打印hello! | -| vga_hello.S | 屏幕上显示hello！ | -| fibonacci_recursive.S | 递归法计算斐波那契数列第7个数并，用用户UART打印结果 | -| load_store.S | 完成一些内存读写，没有具体表现，为了观察现象，可以使用UART调试器查看内存 | +| io-test/uart_print.S | 用户UART循环打印hello, 即**指令ROM**中的程序 | +| io-test/vga_hello.S | 屏幕上显示hello | +| calculation-test/Fibonacci.S | 递归法计算**斐波那契数列**第8个数 | +| calculation-test/Number2Ascii.S | 将数字转化成ASCII字符串，类似于C语言中的 **itoa** 或 **sprintf %d** | +| calculation-test/QuickSort.S | 在RAM中初始化一段数据，并进行**快速排序** | +| basic-test/big_endian_little_endian.S | 测试这个系统是**大端序**还是**小端序**（这里自然是小端序） | +| basic-test/load_store.S | 完成一些内存读写 | -现在我们尝试让SoC运行一个计算斐波那契数列并UART打印的程序。点击“打开...”按钮，浏览到目录./software/asm-code，打开汇编文件 fibonacci_recursive.S。点击右侧的“汇编”按钮，可以看到右方框里出现了一串16进制数，这就是汇编得到的机器码。然后，选择正确的COM口，点击“烧写”，如果下方状态栏里显示“烧写成功”，则CPU就已经开始运行该机器码了。这时，在右侧的“串口查看”框里选中“16进制显示”，可以看到不断显示出22，这说明CPU正确的计算出斐波那契数列的第七个数是0x22，即十进制的34。 +**USTCRVSoC-tool.exe** 是一个能汇编和烧写的小工具，相当于一个 **汇编语言的IDE**，其路径是 **./tools/USTCRVSoC-tool.exe**，界面如下图。 + +![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/USTCRVSoC-tool-image.png) + +现在尝试让SoC运行一个计算快速排序的程序。步骤： +1. **打开 USTCRVSoC-tool.exe ** +2. **打开**：点击**打开...**按钮，浏览到目录./software/asm-code/calculation-test/，打开汇编文件 **QuickSort.S**。 +3. **汇编**：点击**汇编**按钮，可以看到下方框里出现了一串16进制数，这就是汇编得到的机器码。 +4. **烧写**：确保FPGA连接到电脑并烧录了SoC的硬件，然后选择正确的 COM 端口，点击**烧写**，如果下方状态栏里显示“烧写成功”，则CPU就已经开始运行该机器码了。 +5. **查看内存**：这时，在右侧点击**DUMP内存**，可以看到一个有序的数列。QuickSort程序对-9~+9的乱序数组进行了排序，每个数重复了两次。默认的**DUMP内存**不能显示完全，可以将长度设置为100，这样DUMP的字节数量为0x100字节，能看到排序的完整结果。 + +另外，**USTCRVSoC-tool** 也能查看USER模式下的串口数据。请打开 **io-test/uart_print.S**，汇编并烧写，可以看到右侧的**串口查看**框中不断的打印hello。 + +现在，你可以尝试运行这些汇编 benchmark，或者自己编写汇编进行测试。**Have fun!** + +> 关于**普林斯顿结构**：我们虽然区分了**指令RAM**、**数据RAM**、**显存RAM**，但这写存储器在普林斯顿结构中都没有区别。你可以把指令烧写到**数据RAM**、**显存RAM**中去运行，也可以把变量放在**指令RAM**中。甚至，指令和数据都可以放在**数据RAM**中，只要地址别冲突，程序也能正常运行。但是这样的运行效率就会降低，因为CPU的**指令接口**和**数据接口**会**争抢总线**。 # RTL仿真 -### 生成Verilog ROM - -USTCRVSoC-tool.exe 除了进行烧写，也可以生成指令ROM的Verilog代码。当你使用“汇编”按钮产生指令流后，可以点击右侧的“保存指令流(Verilog)”按钮，用生成的ROM代码替换 ./RTL/instr_rom.sv +该仓库提供了 **Vivado** 和 **ModelSim-Altera** 两种仿真环境的仿真工程 ### 进行仿真 -生成ROM后请直接使用soc_top_tb.sv文件进行仿真，这个仿真是针对整个SoC的，因此你可以修改ROM程序后进行仿真，观察SoC运行该程序的行为。 +* 如果你用 **Vivado** ，请打开工程 **./hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr** ，工程已经选择了 **soc_top_tb.sv** 作为仿真的顶层，可以直接进行**行为仿真**。 +* 如果你用 **Quartus** ，请确认你也有 **ModelSim-Altera** 组件。使用 **ModelSim-Altera** 打开 **./hardware/ModelSim/USTCRVSoC.mpf**，编译之后请对**soc_top_tb**进行仿真。 + +仿真时运行的指令流来自**指令ROM**，如果你还没修改过**指令ROM**，则仿真时可以看到 **uart_tx** 信号出现 **uart** 发送的波形，这是它在打印 **hello**。 + +> 提示：通常，安装 **Quartus** 时，如果不是刻意的不勾选，都会自动安装上 **ModelSim-Altera** + +### 修改指令ROM + +如果你想仿真某个指令流，需要对**指令ROM**进行修改。 + +**USTCRVSoC-tool** 除了进行烧写，也可以用编译后的指令流生成**指令ROM**的Verilog代码。当你使用**汇编**按钮产生指令流后，可以点击右侧的**保存指令流(Verilog)**按钮，保存时替换 **./RTL/instr_rom.sv**，再重新进行仿真即可。 + + diff --git a/USTCRVSoC-tool-VS2012/USTCRVSoC-tool/MainForm.Designer.cs b/USTCRVSoC-tool-VS2012/USTCRVSoC-tool/MainForm.Designer.cs index a33fdef..d476dd5 100644 --- a/USTCRVSoC-tool-VS2012/USTCRVSoC-tool/MainForm.Designer.cs +++ b/USTCRVSoC-tool-VS2012/USTCRVSoC-tool/MainForm.Designer.cs @@ -301,6 +301,7 @@ this.tableLayoutPanel6.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Percent, 50F)); this.tableLayoutPanel6.Size = new System.Drawing.Size(232, 44); this.tableLayoutPanel6.TabIndex = 1; + this.tableLayoutPanel6.Paint += new System.Windows.Forms.PaintEventHandler(this.tableLayoutPanel6_Paint); // // programBtn // diff --git a/USTCRVSoC-tool-VS2012/USTCRVSoC-tool/MainForm.cs b/USTCRVSoC-tool-VS2012/USTCRVSoC-tool/MainForm.cs index 3619f90..52913c0 100644 --- a/USTCRVSoC-tool-VS2012/USTCRVSoC-tool/MainForm.cs +++ b/USTCRVSoC-tool-VS2012/USTCRVSoC-tool/MainForm.cs @@ -408,7 +408,7 @@ namespace USTCRVSoC_tool if (!refreshSerial()) return; - if (!serialSessionB("s", "debug")) + if (!serialSessionB("s", "")) return; uint index = 0; @@ -463,7 +463,8 @@ namespace USTCRVSoC_tool if (!refreshSerial()) return; - if (!serialSessionB("s", "debug")) + string response = ""; + if (!serialSessionB("s", "")) return; 内存内容.Clear(); @@ -472,7 +473,7 @@ namespace USTCRVSoC_tool for (index = 0; index < len; index++) { string send_str = String.Format("{0:x8}", start + index * 4); - string response = ""; + response = ""; if (!serialSessionA(send_str, ref response)) return; 内存内容.AppendText(String.Format("{0:x8} : {1:S}\r\n", start + index * 4, response.Trim())); @@ -549,5 +550,10 @@ namespace USTCRVSoC_tool } } #endregion + + private void tableLayoutPanel6_Paint(object sender, PaintEventArgs e) + { + + } } } diff --git a/UartSession-VS2012/UartSession.sln b/UartSession-VS2012/UartSession.sln new file mode 100644 index 0000000..d40d27b --- /dev/null +++ b/UartSession-VS2012/UartSession.sln @@ -0,0 +1,20 @@ + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Visual Studio 2012 +Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "UartSession", "UartSession\UartSession.csproj", "{90E1C916-2A9E-43DC-A0A4-56D029F666C2}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Any CPU = Debug|Any CPU + Release|Any CPU = Release|Any CPU + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {90E1C916-2A9E-43DC-A0A4-56D029F666C2}.Debug|Any CPU.ActiveCfg = Debug|Any CPU + {90E1C916-2A9E-43DC-A0A4-56D029F666C2}.Debug|Any CPU.Build.0 = Debug|Any CPU + {90E1C916-2A9E-43DC-A0A4-56D029F666C2}.Release|Any CPU.ActiveCfg = Release|Any CPU + {90E1C916-2A9E-43DC-A0A4-56D029F666C2}.Release|Any CPU.Build.0 = Release|Any CPU + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/UartSession-VS2012/UartSession/App.config b/UartSession-VS2012/UartSession/App.config new file mode 100644 index 0000000..fad249e --- /dev/null +++ b/UartSession-VS2012/UartSession/App.config @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/UartSession-VS2012/UartSession/Program.cs b/UartSession-VS2012/UartSession/Program.cs new file mode 100644 index 0000000..47dd327 --- /dev/null +++ b/UartSession-VS2012/UartSession/Program.cs @@ -0,0 +1,110 @@ +using System; +using System.IO.Ports; + +namespace UartSession +{ + class Program + { + static SerialPort port = new SerialPort(); + + static void DataReceived(object sender, System.IO.Ports.SerialDataReceivedEventArgs e) + { + SerialPort sp = (SerialPort)sender; + try + { + string recvdata = sp.ReadExisting(); + Console.Write(recvdata); + } + catch { } + } + + static void Main(string[] args) + { + int index; + string input; + + port.BaudRate = 115200; + port.DataBits = 8; + port.Parity = Parity.None; + port.StopBits = StopBits.One; + port.DtrEnable = false; + port.RtsEnable = false; + port.ReadTimeout = 1000; + port.WriteTimeout = 500; + port.DataReceived += new SerialDataReceivedEventHandler(DataReceived); + + while (true) + { + int set_baud = -1; + int ser_no = -1; + string[] ser_names = { }; + + Console.WriteLine("\n\n命令列表:"); + try { ser_names = SerialPort.GetPortNames(); }catch { } + for (index = 0; index < ser_names.Length; index++) + Console.WriteLine(" {0:#0} : 打开 {1:S}", index, ser_names[index]); + if(index<=0) + Console.WriteLine(" (* 未找到端口 *)"); + Console.WriteLine(" baud [数字] : 设置COM口波特率，例如 baud 9600 表示设置波特率为9600"); + Console.WriteLine(" refresh : 刷新COM口列表"); + Console.WriteLine(" exit : 退出"); + + Console.Write("\n当前波特率为{0:D}\n请输入你的命令:", port.BaudRate); + input = Console.ReadLine().Trim(); + try { ser_no = Convert.ToInt32(input); } catch {} + try{ + string[] tmps = input.Split(); + if (tmps.Length == 2 && tmps[0] == "baud") + set_baud = Convert.ToInt32(tmps[1]); + }catch{} + + if (input == "exit") + break; + else if (input == "refresh") + { + Console.WriteLine("\n\n"); + continue; + } + else if (set_baud>0) + { + try + { + port.BaudRate = set_baud; + } + catch (Exception ex) + { + Console.WriteLine(" *** 错误: {0:S} ***", ex.Message); + continue; + } + } + else if (ser_no >= 0 && ser_no < index) + { + string ser_name = ser_names[ser_no]; + try + { + port.PortName = ser_name; + port.Open(); + } + catch (Exception ex) + { + Console.WriteLine(" *** 开启串口错误: {0:S} ***", ex.Message); + continue; + } + Console.WriteLine(" 已经打开{0:S}，请输入发送数据，输入exit退出", ser_name); + while (true) + { + input = Console.ReadLine().Trim(); + if (input == "exit") + break; + try { port.WriteLine(input); } + catch { } + } + port.Close(); + break; + } + else + Console.WriteLine(" *** 格式错误 ***"); + } + } + } +} diff --git a/UartSession-VS2012/UartSession/Properties/AssemblyInfo.cs b/UartSession-VS2012/UartSession/Properties/AssemblyInfo.cs new file mode 100644 index 0000000..e95efe8 --- /dev/null +++ b/UartSession-VS2012/UartSession/Properties/AssemblyInfo.cs @@ -0,0 +1,36 @@ +using System.Reflection; +using System.Runtime.CompilerServices; +using System.Runtime.InteropServices; + +// 有关程序集的常规信息通过以下 +// 特性集控制。更改这些特性值可修改 +// 与程序集关联的信息。 +[assembly: AssemblyTitle("UartSession")] +[assembly: AssemblyDescription("")] +[assembly: AssemblyConfiguration("")] +[assembly: AssemblyCompany("")] +[assembly: AssemblyProduct("UartSession")] +[assembly: AssemblyCopyright("Copyright © 2019")] +[assembly: AssemblyTrademark("")] +[assembly: AssemblyCulture("")] + +// 将 ComVisible 设置为 false 使此程序集中的类型 +// 对 COM 组件不可见。如果需要从 COM 访问此程序集中的类型， +// 则将该类型上的 ComVisible 特性设置为 true。 +[assembly: ComVisible(false)] + +// 如果此项目向 COM 公开，则下列 GUID 用于类型库的 ID +[assembly: Guid("03cfee7d-74be-4491-8eff-8f2b5393d25d")] + +// 程序集的版本信息由下面四个值组成: +// +// 主版本 +// 次版本 +// 生成号 +// 修订号 +// +// 可以指定所有这些值，也可以使用“生成号”和“修订号”的默认值， +// 方法是按如下所示使用“*”: +// [assembly: AssemblyVersion("1.0.*")] +[assembly: AssemblyVersion("1.0.0.0")] +[assembly: AssemblyFileVersion("1.0.0.0")] diff --git a/UartSession-VS2012/UartSession/USB.ico b/UartSession-VS2012/UartSession/USB.ico new file mode 100644 index 0000000..0abcde2 Binary files /dev/null and b/UartSession-VS2012/UartSession/USB.ico differ diff --git a/UartSession-VS2012/UartSession/UartSession.csproj b/UartSession-VS2012/UartSession/UartSession.csproj new file mode 100644 index 0000000..78dc74b --- /dev/null +++ b/UartSession-VS2012/UartSession/UartSession.csproj @@ -0,0 +1,64 @@ + + + + + Debug + AnyCPU + {90E1C916-2A9E-43DC-A0A4-56D029F666C2} + Exe + Properties + UartSession + UartSession + v4.5 + 512 + + + AnyCPU + true + full + false + bin\Debug\ + DEBUG;TRACE + prompt + 4 + + + AnyCPU + pdbonly + true + bin\Release\ + TRACE + prompt + 4 + + + USB.ico + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/hardware/ModelSim/USTCRVSoC.mpf b/hardware/ModelSim/USTCRVSoC.mpf index e1ddddc..f22f7ee 100644 --- a/hardware/ModelSim/USTCRVSoC.mpf +++ b/hardware/ModelSim/USTCRVSoC.mpf @@ -448,50 +448,50 @@ Project_Version = 6 Project_DefaultLib = work Project_SortMethod = unused Project_Files_Count = 22 -Project_File_0 = ../RTL/dual_read_port_ram_32x32.sv -Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551597268 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_1 = ../RTL/vga_char_86x32.sv -Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1551536388 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_2 = ../RTL/ram128B.sv -Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1551597237 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_3 = ../RTL/uart_rx.sv -Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1549876350 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_0 = ../RTL/vga_char_86x32.sv +Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551536388 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 20 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_1 = ../RTL/dual_read_port_ram_32x32.sv +Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551597268 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_2 = ../RTL/uart_rx.sv +Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1549876350 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_3 = ../RTL/ram128B.sv +Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551597237 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_4 = ../RTL/instr_rom.sv -Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551863110 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1552416592 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_5 = ../RTL/video_ram.sv -Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551536461 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551536461 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_6 = ../RTL/soc_top.sv -Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551587626 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_7 = ../RTL/core_ex_branch_judge.sv -Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1549876350 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_8 = ../RTL/ram.sv -Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551597245 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_9 = ../RTL/ram_bus_wrapper.sv -Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1550846066 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_10 = ../RTL/core_bus_wrapper.sv -Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551591033 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_11 = ../RTL/core_alu.sv -Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551588536 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_12 = ../RTL/char8x16_rom.sv -Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551539060 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_13 = ../RTL/core_top.sv -Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551597558 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_14 = ../RTL/soc_top_tb.sv -Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551861246 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_15 = ../RTL/user_uart_tx.sv -Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551512538 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_16 = ../RTL/uart_tx_line.sv -Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1551092170 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_17 = ../RTL/core_regfile.sv -Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551587650 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_18 = ../RTL/isp_uart.sv -Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1551102643 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_19 = ../RTL/core_id_stage.sv -Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551588579 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_20 = ../RTL/naive_bus.sv -Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1549876350 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_21 = ../RTL/naive_bus_router.sv -Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1549876350 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1552152562 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_7 = ../RTL/ram.sv +Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551597245 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_8 = ../RTL/ram_bus_wrapper.sv +Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1550846066 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_9 = ../RTL/core_bus_wrapper.sv +Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1552153482 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_10 = ../RTL/core_alu.sv +Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1552301004 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_11 = ../RTL/char8x16_rom.sv +Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551539060 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_12 = ../RTL/core_top.sv +Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1552364652 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_13 = ../RTL/soc_top_tb.sv +Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551980366 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_14 = ../RTL/user_uart_tx.sv +Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551512538 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 19 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_15 = ../RTL/uart_tx_line.sv +Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551092170 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_16 = ../RTL/core_regfile.sv +Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551587650 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_17 = ../RTL/isp_uart.sv +Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1553085889 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_18 = ../RTL/core_id_stage.sv +Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1552301088 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_19 = ../RTL/core_id_segreg.sv +Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1552291334 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_20 = ../RTL/naive_bus_router.sv +Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1549876350 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_21 = ../RTL/naive_bus.sv +Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1549876350 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 diff --git a/hardware/ModelSim/work/_info b/hardware/ModelSim/work/_info index 9cb7727..1576cc6 100644 --- a/hardware/ModelSim/work/_info +++ b/hardware/ModelSim/work/_info @@ -20,20 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I7hf=@mlD?E>:AKDSDL2O]1 +Z176 VkLTgIQbfzI]@>Jm[T?T@F0 +Z177 !s105 soc_top_tb_sv_unit S1 R6 -Z166 w1551861246 -Z167 8E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv -Z168 FE:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv +Z178 w1551980366 +Z179 8E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv +Z180 FE:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv L0 1 R10 r1 31 -Z169 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv| +Z181 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv| R12 -Z170 !s108 1551863115.642000 -Z171 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv| +Z182 !s108 1553097471.403000 +Z183 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv| !i10b 1 !s85 0 !s101 -O0 vuart_rx R1 -Z172 !s100 :`YDkKm;LaUQOjOXmaKB:0 -Z173 IL9Ji^>V6GeZ<;c7I`o3LQ1 -Z174 Vh0;PUSD9VYIXe2P@6jV9;0 -Z175 !s105 uart_rx_sv_unit +Z184 !s100 :`YDkKm;LaUQOjOXmaKB:0 +Z185 IL9Ji^>V6GeZ<;c7I`o3LQ1 +Z186 Vh0;PUSD9VYIXe2P@6jV9;0 +Z187 !s105 uart_rx_sv_unit S1 R6 R39 -Z176 8E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv -Z177 FE:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv +Z188 8E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv +Z189 FE:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv L0 1 R10 r1 31 -Z178 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv| +Z190 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv| R12 -Z179 !s108 1551863115.708000 -Z180 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv| +Z191 !s108 1553097471.473000 +Z192 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv| !i10b 1 !s85 0 !s101 -O0 vuart_tx_line R1 -Z181 !s100 WEQ@68?0=RGj1iFdbOOcP2 -Z182 IK1;[1cPPe^6]7LKQ15Lf21 -Z183 VW`_FGfF=@_3 -Z184 !s105 uart_tx_line_sv_unit +Z193 !s100 WEQ@68?0=RGj1iFdbOOcP2 +Z194 IK1;[1cPPe^6]7LKQ15Lf21 +Z195 VW`_FGfF=@_3 +Z196 !s105 uart_tx_line_sv_unit S1 R6 -Z185 w1551092170 -Z186 8E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv -Z187 FE:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv +Z197 w1551092170 +Z198 8E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv +Z199 FE:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv L0 2 R10 r1 31 -Z188 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv| +Z200 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv| R12 -Z189 !s108 1551863115.776000 -Z190 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv| +Z201 !s108 1553097471.550000 +Z202 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv| !i10b 1 !s85 0 !s101 -O0 vuser_uart_tx R1 -Z191 !s100 YA]KWMS3fOD:CQT@0Y9C83 -Z192 I0JOL7FjkENP;iNc25_jl92 -Z193 V<1FQ0oW1UA`j`9IX[bcdE1 -Z194 !s105 user_uart_tx_sv_unit +Z203 !s100 YA]KWMS3fOD:CQT@0Y9C83 +Z204 I0JOL7FjkENP;iNc25_jl92 +Z205 V<1FQ0oW1UA`j`9IX[bcdE1 +Z206 !s105 user_uart_tx_sv_unit S1 R6 -Z195 w1551512538 -Z196 8E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv -Z197 FE:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv +Z207 w1551512538 +Z208 8E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv +Z209 FE:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv L0 2 R10 r1 31 -Z198 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv| +Z210 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv| R12 -Z199 !s108 1551863115.848000 -Z200 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv| +Z211 !s108 1553097471.620000 +Z212 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv| !i10b 1 !s85 0 !s101 -O0 vvga R1 -Z201 !s100 9f0>Y=7iSmCK^QMkzVhdz2 -Z202 IK]n:1gV]8z:A^2DY=7iSmCK^QMkzVhdz2 +Z214 IK]n:1gV]8z:A^2D9AM[`i8>D>79]^5c=iL3 -Z213 IXCM=P_6km0Hk^IPzU0S0N1 -Z214 VE9AM[`i8>D>79]^5c=iL3 +Z225 IXCM=P_6km0Hk^IPzU0S0N1 +Z226 VE9aFYMNc5Beh0 -R204 +Z234 !s100 3ih;Pko8X4XgOhl5e4_Gh0 +Z235 IaM^Q2hPSE=jENCH[nQnb^0 +Z236 VkYR^g;?9@>9aFYMNc5Beh0 +R216 S1 R6 -R205 -R206 -R207 +R217 +R218 +R219 L0 82 R10 r1 31 -R209 -R210 -R211 +R221 +R222 +R223 R12 -Z225 nvga@char98x36 +Z237 nvga@char98x36 !i10b 1 !s85 0 !s101 -O0 vvideo_ram R1 -Z226 !s100 5Km:lJ5=^^Z=H?Vg4dnQM0 -Z227 I8o - +
- +
@@ -17,31 +17,34 @@ This means code written to parse this file will need to be revisited each subseq - - + + - + - - - + + + - - - + + + - + + + + - - + + @@ -50,10 +53,11 @@ This means code written to parse this file will need to be revisited each subseq - - + + - + + @@ -61,7 +65,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -69,49 +73,53 @@ This means code written to parse this file will need to be revisited each subseq - - - + + + - + - - + + + + - + + + - - + + - + - - - + + + - + - +
diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/xsim.wdf b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/xsim.wdf new file mode 100644 index 0000000..0f875db --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/xsim.wdf @@ -0,0 +1,4 @@ +version:1 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 +eof:241934075 diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.hw/hw_1/hw.xml b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.hw/hw_1/hw.xml index e78cd84..d302265 100644 --- a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.hw/hw_1/hw.xml +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.hw/hw_1/hw.xml @@ -10,7 +10,7 @@ - + diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/compile.bat b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/compile.bat new file mode 100644 index 0000000..6ed7450 --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/compile.bat @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2017.4 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Wed Mar 20 23:48:26 +0800 2019 +REM SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 +REM +REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvlog --incr --relax -L xil_defaultlib -prj soc_top_tb_vlog.prj" +call xvlog --incr --relax -L xil_defaultlib -prj soc_top_tb_vlog.prj -log xvlog.log +call type xvlog.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/compile.log b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/compile.log new file mode 100644 index 0000000..1cd727b --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/compile.log @@ -0,0 +1,45 @@ +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module char8x16_rom +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module core_alu +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module core_bus_wrapper +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module core_id_segreg +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module core_id_stage +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module core_regfile +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module core_top +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module dual_read_port_ram_32x32 +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module instr_rom +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module isp_uart +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv" into library xil_defaultlib +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module naive_bus_router +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module ram +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module ram128B +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module ram_bus_wrapper +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module soc_top +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module uart_rx +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module uart_tx_line +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module user_uart_tx +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module vga_char_86x32 +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module video_ram +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module soc_top_tb +INFO: [VRFC 10-2263] Analyzing Verilog file "E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module glbl diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/elaborate.bat b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/elaborate.bat new file mode 100644 index 0000000..08c7087 --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/elaborate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2017.4 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Wed Mar 20 23:48:30 +0800 2019 +REM SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 +REM +REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +call xelab -wto ddc8340f1eba4b8bbb076a11b9b82028 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot soc_top_tb_behav xil_defaultlib.soc_top_tb xil_defaultlib.glbl -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/elaborate.log b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/elaborate.log new file mode 100644 index 0000000..0e4b0eb --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/elaborate.log @@ -0,0 +1,34 @@ +Vivado Simulator 2017.4 +Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto ddc8340f1eba4b8bbb076a11b9b82028 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot soc_top_tb_behav xil_defaultlib.soc_top_tb xil_defaultlib.glbl -log elaborate.log +Using 2 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +WARNING: [XSIM 43-4100] "E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale. +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling module xil_defaultlib.naive_bus +Compiling module xil_defaultlib.uart_rx +Compiling module xil_defaultlib.uart_tx_line +Compiling module xil_defaultlib.ram +Compiling module xil_defaultlib.user_uart_tx +Compiling module xil_defaultlib.isp_uart_default +Compiling module xil_defaultlib.core_id_segreg +Compiling module xil_defaultlib.core_id_stage +Compiling module xil_defaultlib.dual_read_port_ram_32x32 +Compiling module xil_defaultlib.core_regfile +Compiling module xil_defaultlib.core_alu +Compiling module xil_defaultlib.core_bus_wrapper +Compiling module xil_defaultlib.core_top +Compiling module xil_defaultlib.instr_rom +Compiling module xil_defaultlib.ram_bus_wrapper +Compiling module xil_defaultlib.ram128B +Compiling module xil_defaultlib.char8x16_rom +Compiling module xil_defaultlib.vga_char_86x32_default +Compiling module xil_defaultlib.video_ram +Compiling module xil_defaultlib.naive_bus_router(N_MASTER=8'b011... +Compiling module xil_defaultlib.soc_top_default +Compiling module xil_defaultlib.soc_top_tb +Compiling module xil_defaultlib.glbl +Built simulation snapshot soc_top_tb_behav diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/glbl.v b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/simulate.bat b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/simulate.bat new file mode 100644 index 0000000..8f81f22 --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/simulate.bat @@ -0,0 +1,23 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2017.4 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Wed Mar 20 23:48:37 +0800 2019 +REM SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 +REM +REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +call xsim soc_top_tb_behav -key {Behavioral:sim_1:Functional:soc_top_tb} -tclbatch soc_top_tb.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/simulate.log b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/simulate.log new file mode 100644 index 0000000..8e54048 --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/simulate.log @@ -0,0 +1,2 @@ +Vivado Simulator 2017.4 +Time resolution is 1 ps diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/soc_top_tb.tcl b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/soc_top_tb.tcl new file mode 100644 index 0000000..f09b1c3 --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/soc_top_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/soc_top_tb_behav.wdb b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/soc_top_tb_behav.wdb new file mode 100644 index 0000000..40134f4 Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/soc_top_tb_behav.wdb differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/soc_top_tb_vlog.prj b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/soc_top_tb_vlog.prj new file mode 100644 index 0000000..2d46a69 --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/soc_top_tb_vlog.prj @@ -0,0 +1,30 @@ +# compile verilog/system verilog design source files +sv xil_defaultlib --include "C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include" \ +"../../../../../../../RTL/char8x16_rom.sv" \ +"../../../../../../../RTL/core_alu.sv" \ +"../../../../../../../RTL/core_bus_wrapper.sv" \ +"../../../../../../../RTL/core_id_segreg.sv" \ +"../../../../../../../RTL/core_id_stage.sv" \ +"../../../../../../../RTL/core_regfile.sv" \ +"../../../../../../../RTL/core_top.sv" \ +"../../../../../../../RTL/dual_read_port_ram_32x32.sv" \ +"../../../../../../../RTL/instr_rom.sv" \ +"../../../../../../../RTL/isp_uart.sv" \ +"../../../../../../../RTL/naive_bus.sv" \ +"../../../../../../../RTL/naive_bus_router.sv" \ +"../../../../../../../RTL/ram.sv" \ +"../../../../../../../RTL/ram128B.sv" \ +"../../../../../../../RTL/ram_bus_wrapper.sv" \ +"../../../../../../../RTL/soc_top.sv" \ +"../../../../../../../RTL/uart_rx.sv" \ +"../../../../../../../RTL/uart_tx_line.sv" \ +"../../../../../../../RTL/user_uart_tx.sv" \ +"../../../../../../../RTL/vga_char_86x32.sv" \ +"../../../../../../../RTL/video_ram.sv" \ +"../../../../../../../RTL/soc_top_tb.sv" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk.jou b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..b2d690c --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2017.4 (64-bit) +# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 +# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 +# Start of session at: Wed Mar 20 23:49:45 2019 +# Process ID: 39800 +# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk.log +# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk.log b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk.log new file mode 100644 index 0000000..c379e16 --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2017.4 (64-bit) +# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 +# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 +# Start of session at: Wed Mar 20 23:49:45 2019 +# Process ID: 39800 +# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk.log +# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Wed Mar 20 23:49:46 2019... diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk_30224.backup.jou b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk_30224.backup.jou new file mode 100644 index 0000000..90ad2d9 --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk_30224.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2017.4 (64-bit) +# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 +# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 +# Start of session at: Wed Mar 20 23:48:36 2019 +# Process ID: 30224 +# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk.log +# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk_30224.backup.log b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk_30224.backup.log new file mode 100644 index 0000000..b375a3c --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk_30224.backup.log @@ -0,0 +1,13 @@ +#----------------------------------------------------------- +# Webtalk v2017.4 (64-bit) +# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 +# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 +# Start of session at: Wed Mar 20 23:48:36 2019 +# Process ID: 30224 +# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk.log +# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-206] Exiting Webtalk at Wed Mar 20 23:48:37 2019... diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xelab.pb b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..822a1ab Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/Compile_Options.txt b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..e3fe588 --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "ddc8340f1eba4b8bbb076a11b9b82028" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "soc_top_tb_behav" "xil_defaultlib.soc_top_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/TempBreakPointFile.txt b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..8082a44 --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/obj/xsim_0.win64.obj b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/obj/xsim_0.win64.obj new file mode 100644 index 0000000..4f87214 Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/obj/xsim_0.win64.obj differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/obj/xsim_1.c b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..6a4b3e8 --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/obj/xsim_1.c @@ -0,0 +1,405 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_2(char*, char *); +extern void execute_3(char*, char *); +extern void execute_186(char*, char *); +extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +extern void execute_428(char*, char *); +extern void execute_429(char*, char *); +extern void execute_430(char*, char *); +extern void execute_431(char*, char *); +extern void execute_432(char*, char *); +extern void execute_433(char*, char *); +extern void execute_434(char*, char *); +extern void execute_420(char*, char *); +extern void execute_421(char*, char *); +extern void execute_422(char*, char *); +extern void execute_423(char*, char *); +extern void execute_424(char*, char *); +extern void execute_425(char*, char *); +extern void execute_426(char*, char *); +extern void execute_30(char*, char *); +extern void execute_31(char*, char *); +extern void execute_58(char*, char *); +extern void execute_59(char*, char *); +extern void execute_60(char*, char *); +extern void execute_61(char*, char *); +extern void execute_62(char*, char *); +extern void execute_63(char*, char *); +extern void execute_64(char*, char *); +extern void execute_65(char*, char *); +extern void execute_66(char*, char *); +extern void execute_67(char*, char *); +extern void execute_68(char*, char *); +extern void execute_69(char*, char *); +extern void execute_70(char*, char *); +extern void execute_71(char*, char *); +extern void execute_72(char*, char *); +extern void execute_73(char*, char *); +extern void execute_74(char*, char *); +extern void execute_191(char*, char *); +extern void execute_192(char*, char *); +extern void execute_193(char*, char *); +extern void execute_194(char*, char *); +extern void execute_195(char*, char *); +extern void execute_210(char*, char *); +extern void execute_211(char*, char *); +extern void execute_33(char*, char *); +extern void execute_34(char*, char *); +extern void execute_35(char*, char *); +extern void execute_36(char*, char *); +extern void execute_37(char*, char *); +extern void execute_38(char*, char *); +extern void execute_196(char*, char *); +extern void execute_197(char*, char *); +extern void execute_40(char*, char *); +extern void execute_41(char*, char *); +extern void execute_42(char*, char *); +extern void execute_43(char*, char *); +extern void execute_44(char*, char *); +extern void execute_45(char*, char *); +extern void execute_46(char*, char *); +extern void execute_198(char*, char *); +extern void execute_199(char*, char *); +extern void execute_48(char*, char *); +extern void execute_49(char*, char *); +extern void execute_50(char*, char *); +extern void execute_51(char*, char *); +extern void execute_52(char*, char *); +extern void execute_53(char*, char *); +extern void execute_200(char*, char *); +extern void execute_201(char*, char *); +extern void execute_202(char*, char *); +extern void execute_203(char*, char *); +extern void execute_204(char*, char *); +extern void execute_205(char*, char *); +extern void execute_206(char*, char *); +extern void execute_207(char*, char *); +extern void execute_208(char*, char *); +extern void execute_209(char*, char *); +extern void execute_55(char*, char *); +extern void execute_56(char*, char *); +extern void execute_57(char*, char *); +extern void execute_94(char*, char *); +extern void execute_98(char*, char *); +extern void execute_104(char*, char *); +extern void vlog_simple_process_execute_0_fast_for_reg(char*, char*, char*); +extern void execute_218(char*, char *); +extern void execute_252(char*, char *); +extern void execute_253(char*, char *); +extern void execute_254(char*, char *); +extern void execute_255(char*, char *); +extern void execute_256(char*, char *); +extern void execute_257(char*, char *); +extern void execute_258(char*, char *); +extern void execute_259(char*, char *); +extern void execute_260(char*, char *); +extern void execute_261(char*, char *); +extern void execute_262(char*, char *); +extern void execute_263(char*, char *); +extern void execute_264(char*, char *); +extern void execute_265(char*, char *); +extern void execute_266(char*, char *); +extern void execute_267(char*, char *); +extern void execute_268(char*, char *); +extern void execute_269(char*, char *); +extern void execute_270(char*, char *); +extern void execute_271(char*, char *); +extern void execute_272(char*, char *); +extern void execute_273(char*, char *); +extern void execute_274(char*, char *); +extern void execute_275(char*, char *); +extern void execute_276(char*, char *); +extern void execute_277(char*, char *); +extern void execute_278(char*, char *); +extern void execute_279(char*, char *); +extern void execute_280(char*, char *); +extern void execute_281(char*, char *); +extern void execute_282(char*, char *); +extern void execute_283(char*, char *); +extern void execute_284(char*, char *); +extern void execute_285(char*, char *); +extern void execute_77(char*, char *); +extern void execute_78(char*, char *); +extern void execute_79(char*, char *); +extern void execute_80(char*, char *); +extern void execute_81(char*, char *); +extern void execute_219(char*, char *); +extern void execute_220(char*, char *); +extern void execute_221(char*, char *); +extern void execute_222(char*, char *); +extern void execute_223(char*, char *); +extern void execute_224(char*, char *); +extern void execute_225(char*, char *); +extern void execute_226(char*, char *); +extern void execute_83(char*, char *); +extern void execute_84(char*, char *); +extern void execute_85(char*, char *); +extern void execute_227(char*, char *); +extern void execute_228(char*, char *); +extern void execute_229(char*, char *); +extern void execute_230(char*, char *); +extern void execute_231(char*, char *); +extern void execute_87(char*, char *); +extern void execute_88(char*, char *); +extern void execute_232(char*, char *); +extern void execute_233(char*, char *); +extern void execute_90(char*, char *); +extern void execute_91(char*, char *); +extern void execute_92(char*, char *); +extern void execute_93(char*, char *); +extern void execute_96(char*, char *); +extern void execute_97(char*, char *); +extern void execute_234(char*, char *); +extern void execute_235(char*, char *); +extern void execute_236(char*, char *); +extern void execute_237(char*, char *); +extern void execute_100(char*, char *); +extern void execute_101(char*, char *); +extern void execute_102(char*, char *); +extern void execute_103(char*, char *); +extern void execute_241(char*, char *); +extern void execute_242(char*, char *); +extern void execute_243(char*, char *); +extern void execute_244(char*, char *); +extern void execute_245(char*, char *); +extern void execute_246(char*, char *); +extern void execute_247(char*, char *); +extern void execute_248(char*, char *); +extern void execute_249(char*, char *); +extern void execute_250(char*, char *); +extern void execute_251(char*, char *); +extern void execute_106(char*, char *); +extern void execute_286(char*, char *); +extern void execute_287(char*, char *); +extern void execute_288(char*, char *); +extern void execute_289(char*, char *); +extern void execute_290(char*, char *); +extern void execute_291(char*, char *); +extern void execute_292(char*, char *); +extern void execute_293(char*, char *); +extern void execute_294(char*, char *); +extern void execute_295(char*, char *); +extern void execute_296(char*, char *); +extern void execute_297(char*, char *); +extern void execute_298(char*, char *); +extern void execute_299(char*, char *); +extern void execute_300(char*, char *); +extern void execute_301(char*, char *); +extern void execute_302(char*, char *); +extern void execute_303(char*, char *); +extern void execute_304(char*, char *); +extern void execute_305(char*, char *); +extern void execute_306(char*, char *); +extern void execute_307(char*, char *); +extern void execute_308(char*, char *); +extern void execute_309(char*, char *); +extern void execute_310(char*, char *); +extern void execute_311(char*, char *); +extern void execute_312(char*, char *); +extern void execute_313(char*, char *); +extern void execute_314(char*, char *); +extern void execute_315(char*, char *); +extern void execute_316(char*, char *); +extern void execute_317(char*, char *); +extern void execute_142(char*, char *); +extern void execute_159(char*, char *); +extern void execute_346(char*, char *); +extern void execute_347(char*, char *); +extern void execute_348(char*, char *); +extern void execute_349(char*, char *); +extern void execute_350(char*, char *); +extern void execute_359(char*, char *); +extern void execute_360(char*, char *); +extern void execute_361(char*, char *); +extern void execute_362(char*, char *); +extern void execute_363(char*, char *); +extern void execute_364(char*, char *); +extern void execute_365(char*, char *); +extern void execute_366(char*, char *); +extern void execute_367(char*, char *); +extern void execute_368(char*, char *); +extern void execute_369(char*, char *); +extern void execute_370(char*, char *); +extern void execute_371(char*, char *); +extern void execute_372(char*, char *); +extern void execute_373(char*, char *); +extern void execute_374(char*, char *); +extern void execute_375(char*, char *); +extern void execute_376(char*, char *); +extern void execute_161(char*, char *); +extern void execute_162(char*, char *); +extern void execute_163(char*, char *); +extern void execute_164(char*, char *); +extern void execute_165(char*, char *); +extern void execute_166(char*, char *); +extern void execute_167(char*, char *); +extern void execute_168(char*, char *); +extern void execute_169(char*, char *); +extern void execute_351(char*, char *); +extern void execute_352(char*, char *); +extern void execute_353(char*, char *); +extern void execute_355(char*, char *); +extern void execute_356(char*, char *); +extern void execute_357(char*, char *); +extern void execute_358(char*, char *); +extern void execute_171(char*, char *); +extern void execute_172(char*, char *); +extern void execute_173(char*, char *); +extern void execute_175(char*, char *); +extern void execute_354(char*, char *); +extern void execute_177(char*, char *); +extern void execute_178(char*, char *); +extern void execute_179(char*, char *); +extern void execute_180(char*, char *); +extern void execute_181(char*, char *); +extern void execute_182(char*, char *); +extern void execute_183(char*, char *); +extern void execute_184(char*, char *); +extern void execute_185(char*, char *); +extern void execute_377(char*, char *); +extern void execute_378(char*, char *); +extern void execute_379(char*, char *); +extern void execute_380(char*, char *); +extern void execute_381(char*, char *); +extern void execute_382(char*, char *); +extern void execute_383(char*, char *); +extern void execute_384(char*, char *); +extern void execute_385(char*, char *); +extern void execute_386(char*, char *); +extern void execute_387(char*, char *); +extern void execute_388(char*, char *); +extern void execute_389(char*, char *); +extern void execute_390(char*, char *); +extern void execute_391(char*, char *); +extern void execute_392(char*, char *); +extern void execute_393(char*, char *); +extern void execute_394(char*, char *); +extern void execute_395(char*, char *); +extern void execute_396(char*, char *); +extern void execute_397(char*, char *); +extern void execute_398(char*, char *); +extern void execute_399(char*, char *); +extern void execute_400(char*, char *); +extern void execute_401(char*, char *); +extern void execute_402(char*, char *); +extern void execute_403(char*, char *); +extern void execute_404(char*, char *); +extern void execute_405(char*, char *); +extern void execute_406(char*, char *); +extern void execute_407(char*, char *); +extern void execute_408(char*, char *); +extern void execute_409(char*, char *); +extern void execute_410(char*, char *); +extern void execute_411(char*, char *); +extern void execute_412(char*, char *); +extern void execute_413(char*, char *); +extern void execute_414(char*, char *); +extern void execute_415(char*, char *); +extern void execute_416(char*, char *); +extern void execute_417(char*, char *); +extern void execute_418(char*, char *); +extern void execute_419(char*, char *); +extern void execute_188(char*, char *); +extern void execute_189(char*, char *); +extern void execute_190(char*, char *); +extern void execute_435(char*, char *); +extern void execute_436(char*, char *); +extern void execute_437(char*, char *); +extern void execute_438(char*, char *); +extern void execute_439(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +extern void transaction_356(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_357(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_407(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_408(char*, char*, unsigned, unsigned, unsigned); +extern void vlog_transfunc_eventcallback_2state(char*, char*, unsigned, unsigned, unsigned, char *); +extern void transaction_210(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_328(char*, char*, unsigned, unsigned, unsigned); +extern void transaction_329(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[317] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_186, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_428, (funcp)execute_429, (funcp)execute_430, (funcp)execute_431, (funcp)execute_432, (funcp)execute_433, (funcp)execute_434, (funcp)execute_420, (funcp)execute_421, (funcp)execute_422, (funcp)execute_423, (funcp)execute_424, (funcp)execute_425, (funcp)execute_426, (funcp)execute_30, (funcp)execute_31, (funcp)execute_58, (funcp)execute_59, (funcp)execute_60, (funcp)execute_61, (funcp)execute_62, (funcp)execute_63, (funcp)execute_64, (funcp)execute_65, (funcp)execute_66, (funcp)execute_67, (funcp)execute_68, (funcp)execute_69, (funcp)execute_70, (funcp)execute_71, (funcp)execute_72, (funcp)execute_73, (funcp)execute_74, (funcp)execute_191, (funcp)execute_192, (funcp)execute_193, (funcp)execute_194, (funcp)execute_195, (funcp)execute_210, (funcp)execute_211, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_196, (funcp)execute_197, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_198, (funcp)execute_199, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)execute_53, (funcp)execute_200, (funcp)execute_201, (funcp)execute_202, (funcp)execute_203, (funcp)execute_204, (funcp)execute_205, (funcp)execute_206, (funcp)execute_207, (funcp)execute_208, (funcp)execute_209, (funcp)execute_55, (funcp)execute_56, (funcp)execute_57, (funcp)execute_94, (funcp)execute_98, (funcp)execute_104, (funcp)vlog_simple_process_execute_0_fast_for_reg, (funcp)execute_218, (funcp)execute_252, (funcp)execute_253, (funcp)execute_254, (funcp)execute_255, (funcp)execute_256, (funcp)execute_257, (funcp)execute_258, (funcp)execute_259, (funcp)execute_260, (funcp)execute_261, (funcp)execute_262, (funcp)execute_263, (funcp)execute_264, (funcp)execute_265, (funcp)execute_266, (funcp)execute_267, (funcp)execute_268, (funcp)execute_269, (funcp)execute_270, (funcp)execute_271, (funcp)execute_272, (funcp)execute_273, (funcp)execute_274, (funcp)execute_275, (funcp)execute_276, (funcp)execute_277, (funcp)execute_278, (funcp)execute_279, (funcp)execute_280, (funcp)execute_281, (funcp)execute_282, (funcp)execute_283, (funcp)execute_284, (funcp)execute_285, (funcp)execute_77, (funcp)execute_78, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_219, (funcp)execute_220, (funcp)execute_221, (funcp)execute_222, (funcp)execute_223, (funcp)execute_224, (funcp)execute_225, (funcp)execute_226, (funcp)execute_83, (funcp)execute_84, (funcp)execute_85, (funcp)execute_227, (funcp)execute_228, (funcp)execute_229, (funcp)execute_230, (funcp)execute_231, (funcp)execute_87, (funcp)execute_88, (funcp)execute_232, (funcp)execute_233, (funcp)execute_90, (funcp)execute_91, (funcp)execute_92, (funcp)execute_93, (funcp)execute_96, (funcp)execute_97, (funcp)execute_234, (funcp)execute_235, (funcp)execute_236, (funcp)execute_237, (funcp)execute_100, (funcp)execute_101, (funcp)execute_102, (funcp)execute_103, (funcp)execute_241, (funcp)execute_242, (funcp)execute_243, (funcp)execute_244, (funcp)execute_245, (funcp)execute_246, (funcp)execute_247, (funcp)execute_248, (funcp)execute_249, (funcp)execute_250, (funcp)execute_251, (funcp)execute_106, (funcp)execute_286, (funcp)execute_287, (funcp)execute_288, (funcp)execute_289, (funcp)execute_290, (funcp)execute_291, (funcp)execute_292, (funcp)execute_293, (funcp)execute_294, (funcp)execute_295, (funcp)execute_296, (funcp)execute_297, (funcp)execute_298, (funcp)execute_299, (funcp)execute_300, (funcp)execute_301, (funcp)execute_302, (funcp)execute_303, (funcp)execute_304, (funcp)execute_305, (funcp)execute_306, (funcp)execute_307, (funcp)execute_308, (funcp)execute_309, (funcp)execute_310, (funcp)execute_311, (funcp)execute_312, (funcp)execute_313, (funcp)execute_314, (funcp)execute_315, (funcp)execute_316, (funcp)execute_317, (funcp)execute_142, (funcp)execute_159, (funcp)execute_346, (funcp)execute_347, (funcp)execute_348, (funcp)execute_349, (funcp)execute_350, (funcp)execute_359, (funcp)execute_360, (funcp)execute_361, (funcp)execute_362, (funcp)execute_363, (funcp)execute_364, (funcp)execute_365, (funcp)execute_366, (funcp)execute_367, (funcp)execute_368, (funcp)execute_369, (funcp)execute_370, (funcp)execute_371, (funcp)execute_372, (funcp)execute_373, (funcp)execute_374, (funcp)execute_375, (funcp)execute_376, (funcp)execute_161, (funcp)execute_162, (funcp)execute_163, (funcp)execute_164, (funcp)execute_165, (funcp)execute_166, (funcp)execute_167, (funcp)execute_168, (funcp)execute_169, (funcp)execute_351, (funcp)execute_352, (funcp)execute_353, (funcp)execute_355, (funcp)execute_356, (funcp)execute_357, (funcp)execute_358, (funcp)execute_171, (funcp)execute_172, (funcp)execute_173, (funcp)execute_175, (funcp)execute_354, (funcp)execute_177, (funcp)execute_178, (funcp)execute_179, (funcp)execute_180, (funcp)execute_181, (funcp)execute_182, (funcp)execute_183, (funcp)execute_184, (funcp)execute_185, (funcp)execute_377, (funcp)execute_378, (funcp)execute_379, (funcp)execute_380, (funcp)execute_381, (funcp)execute_382, (funcp)execute_383, (funcp)execute_384, (funcp)execute_385, (funcp)execute_386, (funcp)execute_387, (funcp)execute_388, (funcp)execute_389, (funcp)execute_390, (funcp)execute_391, (funcp)execute_392, (funcp)execute_393, (funcp)execute_394, (funcp)execute_395, (funcp)execute_396, (funcp)execute_397, (funcp)execute_398, (funcp)execute_399, (funcp)execute_400, (funcp)execute_401, (funcp)execute_402, (funcp)execute_403, (funcp)execute_404, (funcp)execute_405, (funcp)execute_406, (funcp)execute_407, (funcp)execute_408, (funcp)execute_409, (funcp)execute_410, (funcp)execute_411, (funcp)execute_412, (funcp)execute_413, (funcp)execute_414, (funcp)execute_415, (funcp)execute_416, (funcp)execute_417, (funcp)execute_418, (funcp)execute_419, (funcp)execute_188, (funcp)execute_189, (funcp)execute_190, (funcp)execute_435, (funcp)execute_436, (funcp)execute_437, (funcp)execute_438, (funcp)execute_439, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_356, (funcp)transaction_357, (funcp)transaction_407, (funcp)transaction_408, (funcp)vlog_transfunc_eventcallback_2state, (funcp)transaction_210, (funcp)transaction_328, (funcp)transaction_329}; +const int NumRelocateId= 317; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/soc_top_tb_behav/xsim.reloc", (void **)funcTab, 317); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/soc_top_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/soc_top_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/soc_top_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/soc_top_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/soc_top_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/obj/xsim_1.win64.obj b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/obj/xsim_1.win64.obj new file mode 100644 index 0000000..08b3423 Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/obj/xsim_1.win64.obj differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/.xsim_webtallk.info b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..53964b2 --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1553096914 +1553096984 +3 +1 +ddc8340f1eba4b8bbb076a11b9b82028 diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/usage_statistics_ext_xsim.html b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..22031eb --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2086221
date_generatedWed Mar 20 23:49:44 2019os_platformWIN64
product_versionXSIM v2017.4 (64-bit)project_idddc8340f1eba4b8bbb076a11b9b82028
project_iteration2random_id96b72edc-7f7f-45e5-88d1-5286a4317325
registration_id96b72edc-7f7f-45e5-88d1-5286a4317325route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i7-8750H CPU @ 2.20GHzcpu_speed2208 MHz
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
system_ram25.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=5runtime=91 ussimulation_memory=10916_KBsimulation_time=2.58_sec
trace_waveform=true
+

+ + diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..658c43c --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + + +
+
+
+ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.dbg b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.dbg new file mode 100644 index 0000000..623ade0 Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.dbg differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.mem b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.mem new file mode 100644 index 0000000..41df49b Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.mem differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.reloc b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.reloc new file mode 100644 index 0000000..de84ff3 Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.reloc differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.rlx b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.rlx new file mode 100644 index 0000000..6d8b969 --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 6182122172325740929 , + ccp_crc : 0 , + cmdline : " -wto ddc8340f1eba4b8bbb076a11b9b82028 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot soc_top_tb_behav xil_defaultlib.soc_top_tb xil_defaultlib.glbl" , + buildDate : "Dec 15 2017" , + buildTime : "21:07:18" , + linkCmd : "C:\\Xilinx\\Vivado\\2017.4\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/soc_top_tb_behav/xsimk.exe\" \"xsim.dir/soc_top_tb_behav/obj/xsim_0.win64.obj\" \"xsim.dir/soc_top_tb_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx\\Vivado\\2017.4\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx\\Vivado\\2017.4\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.rtti b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.rtti new file mode 100644 index 0000000..31db38e Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.rtti differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.svtype b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.svtype new file mode 100644 index 0000000..74cb41d Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.svtype differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.type b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.type new file mode 100644 index 0000000..14a09a2 Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.type differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.xdbg b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.xdbg new file mode 100644 index 0000000..60f026d Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.xdbg differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsimSettings.ini b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsimSettings.ini new file mode 100644 index 0000000..04557cf --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsimSettings.ini @@ -0,0 +1,26 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=0 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=0 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=0 +OBJECT_NAME_COLUMN_WIDTH=120 +OBJECT_VALUE_COLUMN_WIDTH=241 +OBJECT_DATA_TYPE_COLUMN_WIDTH=60 diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsimcrash.log b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsimcrash.log new file mode 100644 index 0000000..c4d59bb --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsimcrash.log @@ -0,0 +1,29 @@ +Exception at PC 0x00007FFEAA6FA388 +Exception at PC 0x00007FFEAA6FA388 +Exception at PC 0x00007FFEAA6FA388 +Exception at PC 0x00007FFEAA6FA388 +Exception at PC 0x00007FFE118FE132 +Attemped to write at address 0x00007FFE655D4AA4 +Printing stacktrace... + +[0] [0x00007FFE118FE132] +[1] [0x00007FFE118FE132] +[2] [0x00007FFE118FE194] +[3] [0x00007FFE1154D0D7] +[4] [0x00007FFE11432BCA] +[5] [0x00007FFE11432FD1] +[6] [0x00007FFE118FEB2F] +[7] [0x00007FFE117BC19D] +[8] [0x00007FFE117B5942] +[9] [0x00007FFE117B5AB5] +[10] (RtlActivateActivationContextUnsafeFast+0x123) [0x00007FFEAD68B583] +[11] (LdrShutdownProcess+0x125) [0x00007FFEAD697F85] +[12] (RtlExitUserProcess+0xd8) [0x00007FFEAD697E48] +[13] (FatalExit+0xa) [0x00007FFEAC19C80A] +[14] (exit+0x75) [0x00007FFEACAA9CE5] +[15] (initterm_e+0x235) [0x00007FFEACAAA345] +[16] [0x00000000004014CD] +[17] [0x000000000040151B] +[18] (BaseThreadInitThunk+0x14) [0x00007FFEAC193DC4] +[19] (RtlUserThreadStart+0x21) [0x00007FFEAD6C3691] +Done diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsimk.exe b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsimk.exe new file mode 100644 index 0000000..ebb8622 Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsimk.exe differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsimkernel.log b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsimkernel.log new file mode 100644 index 0000000..36f32fd --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/soc_top_tb_behav/xsimk.exe -simmode gui -wdb soc_top_tb_behav.wdb -simrunnum 0 -socket 62220 +Design successfully loaded +Design Loading Memory Usage: 7024 KB (Peak: 7024 KB) +Design Loading CPU Usage: 15 ms +Simulation completed +Simulation Memory Usage: 10916 KB (Peak: 10916 KB) +Simulation CPU Usage: 2578 ms diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/char8x16_rom.sdb b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/char8x16_rom.sdb new file mode 100644 index 0000000..2fafbd6 Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/char8x16_rom.sdb differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/core_alu.sdb b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/core_alu.sdb new file mode 100644 index 0000000..a6fc90f Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/core_alu.sdb differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/core_bus_wrapper.sdb b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/core_bus_wrapper.sdb new file mode 100644 index 0000000..5c214e4 Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/core_bus_wrapper.sdb differ diff --git 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b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/soc_top_tb.sdb differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/uart_rx.sdb b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/uart_rx.sdb new file mode 100644 index 0000000..bd4e97a Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/uart_rx.sdb differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/uart_tx_line.sdb b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/uart_tx_line.sdb new file mode 100644 index 0000000..2aaaff0 Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/uart_tx_line.sdb differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/user_uart_tx.sdb b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/user_uart_tx.sdb new file mode 100644 index 0000000..63e6465 Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/user_uart_tx.sdb differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/vga_char_86x32.sdb b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/vga_char_86x32.sdb new file mode 100644 index 0000000..2167a2e Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/vga_char_86x32.sdb differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/video_ram.sdb b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/video_ram.sdb new file mode 100644 index 0000000..ac50f59 Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/video_ram.sdb differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..a1063dc --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,27 @@ +0.6 +2017.4 +Dec 15 2017 +21:07:18 +E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv,1551539060,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv,,char8x16_rom,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv,1552301004,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv,,core_alu,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv,1552153482,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv,,core_bus_wrapper,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv,1552291334,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv,,core_id_segreg,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv,1552301088,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv,,core_id_stage,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv,1551587650,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv,,core_regfile,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv,1552364652,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv,,core_top,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv,1551597268,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv,,dual_read_port_ram_32x32,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv,1552416592,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv,,instr_rom,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv,1553085889,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv,,isp_uart,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv,1549876350,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv,,naive_bus,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv,1549876350,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv,,naive_bus_router,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv,1551597245,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv,,ram,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv,1551597237,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv,,ram128B,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv,1550846066,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv,,ram_bus_wrapper,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv,1552152562,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv,,soc_top,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv,1551980366,systemVerilog,,,,soc_top_tb,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv,1549876350,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv,,uart_rx,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv,1551092170,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv,,uart_tx_line,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv,1551512538,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv,,user_uart_tx,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv,1551536388,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv,,vga_char_86x32,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv,1551536461,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv,,video_ram,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,, +E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/glbl.v,1513215259,verilog,,,,glbl,,xil_defaultlib,,,,,, diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xsim.svtype b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xsim.svtype new file mode 100644 index 0000000..5142c79 Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/xsim.svtype differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.ini b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.ini new file mode 100644 index 0000000..d47f722 --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.ini @@ -0,0 +1,2 @@ +xil_defaultlib=xsim.dir/xil_defaultlib +xilinx_vip=C:/Xilinx/Vivado/2017.4/data/xsim/ip/xilinx_vip diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xvlog.log b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xvlog.log new file mode 100644 index 0000000..1cd727b --- /dev/null +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xvlog.log @@ -0,0 +1,45 @@ +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module char8x16_rom +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module core_alu +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module core_bus_wrapper +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module core_id_segreg +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module core_id_stage +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module core_regfile +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module core_top +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module dual_read_port_ram_32x32 +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module instr_rom +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module isp_uart +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv" into library xil_defaultlib +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module naive_bus_router +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module ram +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module ram128B +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module ram_bus_wrapper +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module soc_top +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module uart_rx +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module uart_tx_line +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module user_uart_tx +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module vga_char_86x32 +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module video_ram +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module soc_top_tb +INFO: [VRFC 10-2263] Analyzing Verilog file "E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module glbl diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xvlog.pb b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..af0cbca Binary files /dev/null and b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr index e09fe68..73ca069 100644 --- a/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr +++ b/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr @@ -31,7 +31,7 @@