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# USTCRVSoC # USTCRVSoC
一个用SystemVerilog编写的，基于RISC-V的，普林斯顿结构的SoC 一个用 SystemVerilog 编写的，基于 RISC-V 的，普林斯顿结构的 SoC
# 特点 # 特点
> * 5段流水线RISC-V，能运行RV32I指令集 * **CPU**：5段流水线 RISC-V ，能运行 **RV32I** 指令集中的大部分指令
> * 简单直观的32bit握手总线 (naive_bus.sv)， * **总线**：简单直观的，具有**握手机制**的，32-bit地址位宽和32-bit数据位宽的总线
> * 总线仲裁器(naive_bus_router.sv)可修改，以方便拓展外设、多核、DMA等 * **总线仲裁**：可使用宏定义修改，以方便拓展外设、DMA、多核等
> * 具有交互式UART调试器(isp_uart.sv)，用户可以使用PC上的串口助手、minicom等软件，实现系统复位、上传程序、查看内存等功能 * **交互式 UART 调试**：支持使用PC上的Putty、串口助手、minicom等软件，实现**系统复位**、**上传程序**、**查看内存**等功能
> * 全部使用 SystemVerilog 实现，不调用IP核，方便在 Altera、Xilinx、Lattice 等不同FPGA平台上移植，也方便在各种工具中进行仿真 * **纯 RTL 实现**：完全使用SystemVerilog，不调用IP核，便于移植和仿真
> * RAM 和 ROM 符合一定的Verilog写法，自动综合成 Block RAM * RAM 和 ROM 符合一定的Verilog写法，**自动综合成 Block RAM**
# SoC 结构 # SoC 结构
![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/SoC.png) ![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/SoC.png)
上图展示了SoC的结构，总线仲裁器bus_router为SoC的中心，上面挂载了2个“主设备”和5个“从设备”。实际上，CPU具有两个“主接口”，因此bus_router共有3个“主接口”和5个“从接口”。 上图展示了SoC的结构，总线仲裁器**bus_router**为SoC的中心，上面挂载了3个**主接口**和5个**从接口**。这个SoC使用的总线并不来自于任何标准（例如AXI或APB总线），而是笔者自编的，因为简单所以命名为**naive_bus**。
这个SoC使用的总线并不来自于任何标准（例如AXI或APB总线），而是笔者自编的，因为简单所以命名为“naive_bus”。 每个**从接口**都占有一段地址空间。当**主接口**访问总线时，**bus_router**判断该地址属于哪个地址空间，然后将它**路由**到相应的**从接口**。下表展示了5个**从接口**的地址空间。
每个“从接口”都占有一段地址空间。当“主接口”访问总线时，bus_router判断该地址属于哪个地址空间，然后将它“路由”到相应的“从接口”。下表展示了5个“从接口”的地址空间。 | 外设类型 | 起始地址 | 结束地址 |
| 外设类型 | 起始地址 | 结束地址 |
| :-----: | :-----: | :----: | | :-----: | :-----: | :----: |
| 指令ROM | 0x00000000 | 0x00007fff | | 指令ROM | 0x00000000 | 0x00007fff |
| 指令RAM | 0x00008000 | 0x00008fff | | 指令RAM | 0x00008000 | 0x00008fff |
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| 显存RAM | 0x00020000 | 0x00020fff | | 显存RAM | 0x00020000 | 0x00020fff |
| 用户UART | 0x00030000 | 0x00030003 | | 用户UART | 0x00030000 | 0x00030003 |
### 主要部件 ### 组成部件
> * **多主多从总线仲裁器(naive_bus_router.sv)**：为每个从设备划分地址空间，将主设备的总线读写请求路由到从设备。当多个主设备同时访问一个从设备时，还能进行访问冲突控制。 * **多主多从总线仲裁器**：对应文件 naive_bus_router.sv。为每个从设备划分地址空间，将主设备的总线读写请求路由到从设备。当多个主设备同时访问一个从设备时，还能根据主设备的优先级进行冲突仲裁。
> * **RV32I Core(core_top.sv)**：包括两个主接口。一个用于取指令，一个用于读写数据 * **RV32I Core**：对应文件 core_top.sv。包括两个主接口。一个用于取指令，一个用于读写数据。
> * **UART调试器(isp_uart.sv)**：包括一个主接口和一个从接口。它接收用户从UART发来的命令，对总线进行读写。它可以用于在线烧写、在线调试。也可以接收CPU的命令去发送数据。 * **UART调试器**：对应文件 isp_uart.sv。将UART调试功能和用户UART结合为一体。包括一个主接口和一个从接口。它接收上位机从UART发来的命令，对总线进行读写。它可以用于在线烧写、在线调试。也可以接收CPU的命令去发送数据给用户。
> * **指令ROM(instr_rom.sv)**：CPU默认从这里开始取指令，多用于仿真 * **指令ROM**：对应文件 instr_rom.sv。CPU默认从这里开始取指令，里面的指令流是在硬件代码编译综合时就固定的，不能在运行时修改。唯一的修改方法是编辑 **instr_rom.sv** 中的代码，然后重新编译综合、烧写FPGA逻辑。因此**instr_rom** 多用于仿真。
> * **指令RAM(ram_bus_wrapper.sv)**：用户在线烧写程序到这里。 * **指令RAM**：对应文件 ram_bus_wrapper.sv。用户使用 isp_uart 在线烧写指令流到这里，然后将 Boot 地址指向这里，再复位SoC后，CPU就从这里开始运行指令流。
> * **数据RAM(ram_bus_wrapper.sv)**：存放运行时的数据。 * **数据RAM**：对应文件 ram_bus_wrapper.sv。存放运行时的数据。
> * **显存RAM(vedio_ram.sv)**：在屏幕上显示98列*36行=3528个字符，显存RAM的前3528B对应的ASCII码值就决定了每个字符是什么 * **显存RAM**：对应文件 vedio_ram.sv。在屏幕上显示 86列 * 32行 = 2752 个字符，显存 RAM 的 4096B 被划分为 32 个块，每块对应一行，占 128B，前 86 字节对应 86 个列。屏幕上显示的是每个字节作为 ASCII 码所对应的字符。
# RV32I CPU 结构
![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/Core-RTL.png) # 部署 SoC 到 FPGA
TODO 目前，我们提供了 Xilinx 的 **Nexys4-DDR** 开发板和 Altera 的 **DE0-Nano** 开发板的工程。
# 在开发板上运行SoC 为了进行部署和测试，你需要准备以下的东西：
我们提供了两种方式运行代码： * 装有 **Windows7 系统** 或更高版本的 PC（如果使用 Linux 则很难用上我提供的几个C#编写的工具）
* **Nexys4-DDR** 开发板或 **DE0-Nano** 开发板或其它 FPGA 开发板
* 开发板对应的 **RTL 开发环境**，例如 Nexys4-DDR 对应 Vivado（推荐 Vivado 2017.4 或更高版本），DE0-Nano 对应 Quartus （推荐Quartus II 11.1 或更高版本）
* 如果你的开发板没有自带 **USB转UART** 电路（例如 DE0-Nano 就不自带），则需要一个 **USB转UART模块**。
* **可选**：* 屏幕、VGA线 *
1、**使用指令ROM**：修改instr_rom.sv中的代码，然后重新编译综合，重新烧写FPGA逻辑。虽然麻烦，但这便于进行RTL仿真，你可以将想要运行的程序放入指令ROM，然后仅需在testbench中给予SoC一个时钟，就可以观察整个SoC在运行这段代码时的波形。 ## 部署到 Nexys4-DDR
2、**使用指令RAM**：使用UART调试器在线上传程序到指令RAM。 ![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/nexys4-connection2.png)
### 部署电路到FPGA 1. **硬件连接**：如上图，Nexys4 开发板上有一个 USB 口既可以用于 FPGA 烧录，也可以用于 UART 通信，我们需要连接该 USB 口到电脑。另外，VGA 的连接是可选的，你可以把它连接到屏幕上。
2. **综合、烧写**：请用 Vivado 打开 **./hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr**。综合并烧写到开发板。
目前，我们提供了Xilinx的Nexys4板子和Altera的DE0-Nano板子的工程。
1、**Nexys4硬件连接**：Nexys4开发板上有一个USB口既可以用于FPGA烧录，也可以用于UART通信，我们需要连接该USB口到电脑。另外，VGA的连接是可选的，你可以把它连接到屏幕上。 ## 部署到 DE0-Nano
![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/DE0-Nano.png) ![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/DE0-Nano.png)
2、**DE0-Nano硬件连接**：DE0-Nano开发板上既没有串口转USB，也没有VGA接口。因此都需要以来外部模块。我们使用DE0-Nano上的两排GPIO作为外接模块的引脚，接口意义如上图。你至少需要一个USB转UART的模块，将ISP-UART的TX和RX引脚连接上去，使之能与电脑通信，如下图： 1、**硬件连接**：DE0-Nano开发板上既没有串口转USB，也没有VGA接口。因此需要外部模块，以及一些动手能力和硬件知识。我们使用DE0-Nano上的两排GPIO作为外接模块的引脚，接口意义如上图。你需要一个USB转UART的模块，将UART的TX和RX引脚连接上去，使之能与电脑通信。VGA的连接是可选的，需要符合上图中VGA的引脚定义。最后连接的效果如下图：
![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/connection.png) ![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/connection.png)
2、**综合、烧写**：请用 Quartus 打开 **./hardware/Quartus/DE0_Nano/DE0_Nano.qpf**。综合并烧写到开发板。
![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/usb_uart.png) ## 部署到其它开发板
3、**综合、烧写FPGA**：如果你用的是Nexys4板子，请用Vivado打开./hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr。如果你用的是DE0-Nano板子，请用Quartus打开./hardware/Quartus/DE0_Nano/DE0_Nano.qpf。综合并烧写到开发板。 如果很不幸，你手头的 FPGA 开发板既不是 Nexys4，也不是 DE0-Nano，则需要手动建立工程，连接信号到开发板顶层。分为以下步骤：
4、**HelloWorld**：烧录FPGA后，在电脑上的串口终端软件（超级终端、串口助手、minicom）中，使用格式(115200,n,8,1)打开串口，如果看到不断收到"hello\n"，那么恭喜你SoC部署成功，因为SoC的instr_rom里的程序就是循环打印hello的程序。 * **建立工程**：建立工程后，需要将 **./hardware/RTL/** 中的所有 .sv 文件添加进工程。
* **编写顶层**：SoC 的顶层文件是 **./hardware/RTL/soc_top.sv**，你需要编写一个针对该开发板的顶层文件，调用 **soc_top**，并将 FPGA 的引脚连接到 **soc_top** 中。以下是对 **soc_top** 的信号说明。
* **编译、综合、烧写到FPGA**
5、**尝试读取总线**：下面让我们尝试UART的调试功能，首先发送"s\n"进入调试模式，可以看到对方发来"debug\n"，说明进入调试模式成功。然后，发送"00000000\n"，会看到对方发来一个8位16进制数。该数代表SoC数据总线的地址0x00000000处的读取数据。 ```Verilog
module soc_top #(
// UART接收分频系数，请根据clk的时钟频率决定，计算公式 UART_RX_CLK_DIV=clk频率(Hz)/460800，四舍五入
parameter UART_RX_CLK_DIV = 108,
// UART发送分频系数，请根据clk的时钟频率决定，计算公式 UART_TX_CLK_DIV=clk频率(Hz)/115200，四舍五入
parameter UART_TX_CLK_DIV = 434,
// VGA分频系数，请根据clk的时钟频率决定，计算公式 VGA_CLK_DIV=clk频率(Hz)/50000000
parameter VGA_CLK_DIV = 1
)(
input logic clk, // SoC 时钟，推荐使用 50MHz 的倍数
input logic isp_uart_rx, // 连接到开发板的 UART RX 引脚
output logic isp_uart_tx, // 连接到开发板的 UART TX 引脚
output logic vga_hsync, vga_vsync, // 连接到VGA（可以不连接）
output logic vga_red, vga_green, vga_blue // 连接到VGA（可以不连接）
);
```
6、上一步我们尝试了UART调试器的读总线命令，下表显示了它的所有3种命令。
![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/commands.png)
> * 注意：无论是发送还是接受，所有命令都以\n或\r或\r\n结尾 # 测试软件
硬件烧写后，开始对它进行测试
### 查看 Hello World
硬件烧写后，如果你的开发板上有 UART 指示灯，就已经能看到 TX 指示灯在闪烁，每闪烁一下其实是在发送一个"Hello"，这说明CPU在运行指令ROM里默认的程序。下面我们来查看这个Hello。
首先我们需要一款**串口终端软件**，例如：
* minicom
* 串口助手
* 超级终端
* Putty
这些工具用起来都不够爽快，因此这里使用该仓库中自带的小工具 **UartSession** 做示范。它的路径是 **./tools/UartSession.exe**。使用C#编写。
> UartSession.exe使用C#编写，VisualStudio 工程的路径是 **./UartSession-VS2012**。
首先，我们运行 **UartSession.exe**，可以看到该软件将电脑的所有可用端口都列了出来，并给出了几个选项：
* **打开端口**：输入数字，按回车可以打开数字对应的端口。
* **修改波特率**：输入"baud [数字]"，再按回车可以修改波特率。例如输入baud 9600可以修改波特率为9600。
* **刷新端口列表**：输入"refresh"，再按回车可以刷新端口列表。
* **退出**：输入"exit"可以退出
![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/UartSession2.png)
波特率默认是115200，与我们的 SoC 一致，不需要修改。直接从端口列表里找到 FPGA 开发板所对应的端口，打开它。我们就可以看到窗口中不断显示"hello"，根本停不下来，如上图，这说明CPU在正常运行程序。
> 如果不知道端口列表中哪个端口对应 FPGA 开发板，可以拔下开发板的 USB，刷新一次端口列表，则消失的端口就是开发板对应的端口。然后再插上USB（如果FPGA内的电路丢失则需要重新烧录FPGA）
### 使用 UART 调试总线
现在 **UartSession.exe** 界面中不断地打印出"hello"，我们打一个回车，可以看到对方不再打出"hello"，并出现了一个"debug"，这样就成功进入了 **DEBUG模式**。
![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/UartSession1.png)
UART 调试器有两种模式：
* **USER 模式**：该模式下可以收到 CPU 通过 isp_uart 发送的用户打印数据。FPGA烧写后默认处于这个模式。hello只有在这个模式下才能被我们看到。通过向 uart **发送一个\n** 可以跳出 **USER模式**，进入DEBUG模式。
* **DEBUG 模式**：该模式下 CPU 打印的任何数据都会被抑制，UART 不再主动发送数据，变成了**一问一答**的形式，用户发送的调试命令和接收到的应答都**以\n结尾**，通过发送"o"或系统复位可以回到 **USER模式**。
下面让我们尝试 **UART 的调试功能**，输入 **"0"** 并按回车，会看到对方发来一个8位16进制数。该数就是SoC总线的地址 0x00000000 处读取出的数据，也就是**指令ROM**中的第一个指令，如下图。
![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/UartSession3.png)
当然我们也可以用调试器写总线，输入一条写命令： **"10000 abcd1234"** 并按回车，会看到对方发来**"wr done"**，意为写成功，该命令意为向地址 0x10000 中写入 0xabcd1234 (0x10000是数据RAM的首地址）。
为了验证写成功，输入读指令：**"10000"** 并按回车，会看到对方发来**"abcd1234"**。
> 注：UART 调试器每次读写总线只能以**4字节对齐**的形式，并且一次必须读写4字节。
下表显示了 **DEBUG模式** 的所有命令格式。
| 命令类型 | 命令格式 | 返回格式 | 命令示例 | 返回示例 | 含义 |
| :-----: | :-----: | :----: | :-----: | :-----: | :----: |
| 读总线 | [十六进制地址] | [十六进制数据] | 00020000 | abcd1234 | 地址0x00020000读出的数据是0xabcd1234 |
| 写总线 | [十六进制地址] [十六进制数据] | wr done | 00020004 1276acd0 | wr done | 向地址0x00020004写数据0x1276acd0 |
| 切换至调试模式 | o | user | o | user | 切换回USER模式
| 复位 | r[十六进制boot地址] | rst done | r00008000 | rst done | CPU 复位并从地址 0x00008000 处开始执行，同时切换回 USER 模式 |
| 非法命令 | [其它格式] | invalid | ^^$aslfdi | invalid | 发送的指令未定义 |
> 注：无论是发送还是接收，所有命令都以\n或\r或\r\n结尾，**UartSession.exe**是自动插入\n的。如果使用串口助手等其它软件，需要注意这个问题。
根据这些命令，不难猜出，在线上传程序的流程是： 根据这些命令，不难猜出，在线上传程序的流程是：
> 1、使用写命令，将指令流写入指令RAM，（指令RAM的地址是00008000~00008fff） 1. 使用写命令，将指令流写入指令RAM，（指令RAM的地址是00008000~00008fff）
2. 使用复位命令r00008000，将CPU复位并从指令RAM中BOOT
> 2、使用复位命令r00008000，将CPU复位并从指令RAM中BOOT ### 使用 VGA 屏幕
### 使用工具：USTCRVSoC-tool （该软件有所改动，文档稍后补充） 没有连接屏幕的可以跳过这一步。
./USTCRVSoC-tool/USTCRVSoC-tool.exe 是一个能汇编和烧写的小工具，相当于一个汇编语言的IDE。 如果开发板通过 VGA 连接到了屏幕，我们可以看到屏幕上出现一个红框，里面空空如也。实际上里面隐藏了 86列32行的字符空位。下面用 UART调试器 让屏幕上显示字符。
我们提供了几个汇编小程序如下表。 > 提示：如果屏幕中的红框不在正中间，可以使用屏幕的“自动校正”按钮校正一下
在**DEBUG模式**下，发送一条写命令： **"20000 31323334"** ，可以看到第一行出现了 **4321** 。这是因为显存RAM的起始地址是 0x20000，使用 UART调试器 正好向其中的前4个字节写入了 0x34、0x33、0x32、0x31，也就是**4321**的ASCII码。
显存 RAM 占 4096 字节，分为32个块，对应屏幕中的32个行；每块128B，前 86 字节对应该行中的前 86 个字符的 ASCII 码。后面128-86个字节不会显示在屏幕上。
显存 RAM 与 数据 RAM 行为相同，即可读又可写，但不能保证一个时钟周期一定能读出数据。
### 使用工具：USTCRVSoC-tool
玩了好久的 UART调试，也该用 CPU 跑跑 benchmark 了。
**./software/asm-code** 中提供几个汇编语言的小程序作为 benchmark，如下表。
| 文件名 | 说明 | | 文件名 | 说明 |
| :----- | :----- | | :----- | :----- |
| uart_print.S | 用户UART循环打印hello! | | io-test/uart_print.S | 用户UART循环打印hello, 即**指令ROM**中的程序 |
| vga_hello.S | 屏幕上显示hello！ | | io-test/vga_hello.S | 屏幕上显示hello |
| fibonacci_recursive.S | 递归法计算斐波那契数列第7个数并，用用户UART打印结果 | | calculation-test/Fibonacci.S | 递归法计算**斐波那契数列**第8个数 |
| load_store.S | 完成一些内存读写，没有具体表现，为了观察现象，可以使用UART调试器查看内存 | | calculation-test/Number2Ascii.S | 将数字转化成ASCII字符串，类似于C语言中的 **itoa** 或 **sprintf %d** |
| calculation-test/QuickSort.S | 在RAM中初始化一段数据，并进行**快速排序** |
| basic-test/big_endian_little_endian.S | 测试这个系统是**大端序**还是**小端序**（这里自然是小端序） |
| basic-test/load_store.S | 完成一些内存读写 |
现在我们尝试让SoC运行一个计算斐波那契数列并UART打印的程序。点击“打开...”按钮，浏览到目录./software/asm-code，打开汇编文件 fibonacci_recursive.S。点击右侧的“汇编”按钮，可以看到右方框里出现了一串16进制数，这就是汇编得到的机器码。然后，选择正确的COM口，点击“烧写”，如果下方状态栏里显示“烧写成功”，则CPU就已经开始运行该机器码了。这时，在右侧的“串口查看”框里选中“16进制显示”，可以看到不断显示出22，这说明CPU正确的计算出斐波那契数列的第七个数是0x22，即十进制的34。 **USTCRVSoC-tool.exe** 是一个能汇编和烧写的小工具，相当于一个 **汇编语言的IDE**，其路径是 **./tools/USTCRVSoC-tool.exe**，界面如下图。
![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/USTCRVSoC-tool-image.png)
现在尝试让SoC运行一个计算快速排序的程序。步骤：
1. **打开 USTCRVSoC-tool.exe **
2. **打开**：点击**打开...**按钮，浏览到目录./software/asm-code/calculation-test/，打开汇编文件 **QuickSort.S**。
3. **汇编**：点击**汇编**按钮，可以看到下方框里出现了一串16进制数，这就是汇编得到的机器码。
4. **烧写**：确保FPGA连接到电脑并烧录了SoC的硬件，然后选择正确的 COM 端口，点击**烧写**，如果下方状态栏里显示“烧写成功”，则CPU就已经开始运行该机器码了。
5. **查看内存**：这时，在右侧点击**DUMP内存**，可以看到一个有序的数列。QuickSort程序对-9~+9的乱序数组进行了排序，每个数重复了两次。默认的**DUMP内存**不能显示完全，可以将长度设置为100，这样DUMP的字节数量为0x100字节，能看到排序的完整结果。
另外，**USTCRVSoC-tool** 也能查看USER模式下的串口数据。请打开 **io-test/uart_print.S**，汇编并烧写，可以看到右侧的**串口查看**框中不断的打印hello。
现在，你可以尝试运行这些汇编 benchmark，或者自己编写汇编进行测试。**Have fun!**
> 关于**普林斯顿结构**：我们虽然区分了**指令RAM**、**数据RAM**、**显存RAM**，但这写存储器在普林斯顿结构中都没有区别。你可以把指令烧写到**数据RAM**、**显存RAM**中去运行，也可以把变量放在**指令RAM**中。甚至，指令和数据都可以放在**数据RAM**中，只要地址别冲突，程序也能正常运行。但是这样的运行效率就会降低，因为CPU的**指令接口**和**数据接口**会**争抢总线**。
# RTL仿真 # RTL仿真
### 生成Verilog ROM 该仓库提供了 **Vivado** 和 **ModelSim-Altera** 两种仿真环境的仿真工程
USTCRVSoC-tool.exe 除了进行烧写，也可以生成指令ROM的Verilog代码。当你使用“汇编”按钮产生指令流后，可以点击右侧的“保存指令流(Verilog)”按钮，用生成的ROM代码替换 ./RTL/instr_rom.sv
### 进行仿真 ### 进行仿真
生成ROM后请直接使用soc_top_tb.sv文件进行仿真，这个仿真是针对整个SoC的，因此你可以修改ROM程序后进行仿真，观察SoC运行该程序的行为。 * 如果你用 **Vivado** ，请打开工程 **./hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr** ，工程已经选择了 **soc_top_tb.sv** 作为仿真的顶层，可以直接进行**行为仿真**。
* 如果你用 **Quartus** ，请确认你也有 **ModelSim-Altera** 组件。使用 **ModelSim-Altera** 打开 **./hardware/ModelSim/USTCRVSoC.mpf**，编译之后请对**soc_top_tb**进行仿真。
仿真时运行的指令流来自**指令ROM**，如果你还没修改过**指令ROM**，则仿真时可以看到 **uart_tx** 信号出现 **uart** 发送的波形，这是它在打印 **hello**。
> 提示：通常，安装 **Quartus** 时，如果不是刻意的不勾选，都会自动安装上 **ModelSim-Altera**
### 修改指令ROM
如果你想仿真某个指令流，需要对**指令ROM**进行修改。
**USTCRVSoC-tool** 除了进行烧写，也可以用编译后的指令流生成**指令ROM**的Verilog代码。当你使用**汇编**按钮产生指令流后，可以点击右侧的**保存指令流(Verilog)**按钮，保存时替换 **./RTL/instr_rom.sv**，再重新进行仿真即可。

1
USTCRVSoC-tool-VS2012/USTCRVSoC-tool/MainForm.Designer.cs generated
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@ -301,6 +301,7 @@
this.tableLayoutPanel6.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Percent, 50F)); this.tableLayoutPanel6.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Percent, 50F));
this.tableLayoutPanel6.Size = new System.Drawing.Size(232, 44); this.tableLayoutPanel6.Size = new System.Drawing.Size(232, 44);
this.tableLayoutPanel6.TabIndex = 1; this.tableLayoutPanel6.TabIndex = 1;
this.tableLayoutPanel6.Paint += new System.Windows.Forms.PaintEventHandler(this.tableLayoutPanel6_Paint);
// //
// programBtn // programBtn
// //

12
USTCRVSoC-tool-VS2012/USTCRVSoC-tool/MainForm.cs
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@ -408,7 +408,7 @@ namespace USTCRVSoC_tool
if (!refreshSerial()) if (!refreshSerial())
return; return;
if (!serialSessionB("s", "debug")) if (!serialSessionB("s", ""))
return; return;
uint index = 0; uint index = 0;
@ -463,7 +463,8 @@ namespace USTCRVSoC_tool
if (!refreshSerial()) if (!refreshSerial())
return; return;
if (!serialSessionB("s", "debug")) string response = "";
if (!serialSessionB("s", ""))
return; return;
内存内容.Clear(); 内存内容.Clear();
@ -472,7 +473,7 @@ namespace USTCRVSoC_tool
for (index = 0; index < len; index++) for (index = 0; index < len; index++)
{ {
string send_str = String.Format("{0:x8}", start + index * 4); string send_str = String.Format("{0:x8}", start + index * 4);
string response = ""; response = "";
if (!serialSessionA(send_str, ref response)) if (!serialSessionA(send_str, ref response))
return; return;
内存内容.AppendText(String.Format("{0:x8} : {1:S}\r\n", start + index * 4, response.Trim())); 内存内容.AppendText(String.Format("{0:x8} : {1:S}\r\n", start + index * 4, response.Trim()));
@ -549,5 +550,10 @@ namespace USTCRVSoC_tool
} }
} }
#endregion #endregion
private void tableLayoutPanel6_Paint(object sender, PaintEventArgs e)
{
}
} }
} }

20
UartSession-VS2012/UartSession.sln Normal file
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@ -0,0 +1,20 @@

Microsoft Visual Studio Solution File, Format Version 12.00
# Visual Studio 2012
Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "UartSession", "UartSession\UartSession.csproj", "{90E1C916-2A9E-43DC-A0A4-56D029F666C2}"
EndProject
Global
GlobalSection(SolutionConfigurationPlatforms) = preSolution
Debug|Any CPU = Debug|Any CPU
Release|Any CPU = Release|Any CPU
EndGlobalSection
GlobalSection(ProjectConfigurationPlatforms) = postSolution
{90E1C916-2A9E-43DC-A0A4-56D029F666C2}.Debug|Any CPU.ActiveCfg = Debug|Any CPU
{90E1C916-2A9E-43DC-A0A4-56D029F666C2}.Debug|Any CPU.Build.0 = Debug|Any CPU
{90E1C916-2A9E-43DC-A0A4-56D029F666C2}.Release|Any CPU.ActiveCfg = Release|Any CPU
{90E1C916-2A9E-43DC-A0A4-56D029F666C2}.Release|Any CPU.Build.0 = Release|Any CPU
EndGlobalSection
GlobalSection(SolutionProperties) = preSolution
HideSolutionNode = FALSE
EndGlobalSection
EndGlobal

6
UartSession-VS2012/UartSession/App.config Normal file
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@ -0,0 +1,6 @@
<?xml version="1.0" encoding="utf-8" ?>
<configuration>
<startup>
<supportedRuntime version="v4.0" sku=".NETFramework,Version=v4.5" />
</startup>
</configuration>

110
UartSession-VS2012/UartSession/Program.cs Normal file
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@ -0,0 +1,110 @@
using System;
using System.IO.Ports;
namespace UartSession
{
class Program
{
static SerialPort port = new SerialPort();
static void DataReceived(object sender, System.IO.Ports.SerialDataReceivedEventArgs e)
{
SerialPort sp = (SerialPort)sender;
try
{
string recvdata = sp.ReadExisting();
Console.Write(recvdata);
}
catch { }
}
static void Main(string[] args)
{
int index;
string input;
port.BaudRate = 115200;
port.DataBits = 8;
port.Parity = Parity.None;
port.StopBits = StopBits.One;
port.DtrEnable = false;
port.RtsEnable = false;
port.ReadTimeout = 1000;
port.WriteTimeout = 500;
port.DataReceived += new SerialDataReceivedEventHandler(DataReceived);
while (true)
{
int set_baud = -1;
int ser_no = -1;
string[] ser_names = { };
Console.WriteLine("\n\n命令列表:");
try { ser_names = SerialPort.GetPortNames(); }catch { }
for (index = 0; index < ser_names.Length; index++)
Console.WriteLine(" {0:#0} : 打开 {1:S}", index, ser_names[index]);
if(index<=0)
Console.WriteLine(" (* 未找到端口 *)");
Console.WriteLine(" baud [数字] : 设置COM口波特率，例如 baud 9600 表示设置波特率为9600");
Console.WriteLine(" refresh : 刷新COM口列表");
Console.WriteLine(" exit : 退出");
Console.Write("\n当前波特率为{0:D}\n请输入你的命令:", port.BaudRate);
input = Console.ReadLine().Trim();
try { ser_no = Convert.ToInt32(input); } catch {}
try{
string[] tmps = input.Split();
if (tmps.Length == 2 && tmps[0] == "baud")
set_baud = Convert.ToInt32(tmps[1]);
}catch{}
if (input == "exit")
break;
else if (input == "refresh")
{
Console.WriteLine("\n\n");
continue;
}
else if (set_baud>0)
{
try
{
port.BaudRate = set_baud;
}
catch (Exception ex)
{
Console.WriteLine(" *** 错误: {0:S} ***", ex.Message);
continue;
}
}
else if (ser_no >= 0 && ser_no < index)
{
string ser_name = ser_names[ser_no];
try
{
port.PortName = ser_name;
port.Open();
}
catch (Exception ex)
{
Console.WriteLine(" *** 开启串口错误: {0:S} ***", ex.Message);
continue;
}
Console.WriteLine(" 已经打开{0:S}，请输入发送数据，输入exit退出", ser_name);
while (true)
{
input = Console.ReadLine().Trim();
if (input == "exit")
break;
try { port.WriteLine(input); }
catch { }
}
port.Close();
break;
}
else
Console.WriteLine(" *** 格式错误 ***");
}
}
}
}

36
UartSession-VS2012/UartSession/Properties/AssemblyInfo.cs Normal file
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@ -0,0 +1,36 @@
using System.Reflection;
using System.Runtime.CompilerServices;
using System.Runtime.InteropServices;
// 有关程序集的常规信息通过以下
// 特性集控制。更改这些特性值可修改
// 与程序集关联的信息。
[assembly: AssemblyTitle("UartSession")]
[assembly: AssemblyDescription("")]
[assembly: AssemblyConfiguration("")]
[assembly: AssemblyCompany("")]
[assembly: AssemblyProduct("UartSession")]
[assembly: AssemblyCopyright("Copyright © 2019")]
[assembly: AssemblyTrademark("")]
[assembly: AssemblyCulture("")]
// 将 ComVisible 设置为 false 使此程序集中的类型
// 对 COM 组件不可见。如果需要从 COM 访问此程序集中的类型，
// 则将该类型上的 ComVisible 特性设置为 true。
[assembly: ComVisible(false)]
// 如果此项目向 COM 公开，则下列 GUID 用于类型库的 ID
[assembly: Guid("03cfee7d-74be-4491-8eff-8f2b5393d25d")]
// 程序集的版本信息由下面四个值组成:
//
// 主版本
// 次版本
// 生成号
// 修订号
//
// 可以指定所有这些值，也可以使用“生成号”和“修订号”的默认值，
// 方法是按如下所示使用“*”:
// [assembly: AssemblyVersion("1.0.*")]
[assembly: AssemblyVersion("1.0.0.0")]
[assembly: AssemblyFileVersion("1.0.0.0")]

BIN
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64
UartSession-VS2012/UartSession/UartSession.csproj Normal file
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@ -0,0 +1,64 @@
<?xml version="1.0" encoding="utf-8"?>
<Project ToolsVersion="4.0" DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
<Import Project="$(MSBuildExtensionsPath)\$(MSBuildToolsVersion)\Microsoft.Common.props" Condition="Exists('$(MSBuildExtensionsPath)\$(MSBuildToolsVersion)\Microsoft.Common.props')" />
<PropertyGroup>
<Configuration Condition=" '$(Configuration)' == '' ">Debug</Configuration>
<Platform Condition=" '$(Platform)' == '' ">AnyCPU</Platform>
<ProjectGuid>{90E1C916-2A9E-43DC-A0A4-56D029F666C2}</ProjectGuid>
<OutputType>Exe</OutputType>
<AppDesignerFolder>Properties</AppDesignerFolder>
<RootNamespace>UartSession</RootNamespace>
<AssemblyName>UartSession</AssemblyName>
<TargetFrameworkVersion>v4.5</TargetFrameworkVersion>
<FileAlignment>512</FileAlignment>
</PropertyGroup>
<PropertyGroup Condition=" '$(Configuration)|$(Platform)' == 'Debug|AnyCPU' ">
<PlatformTarget>AnyCPU</PlatformTarget>
<DebugSymbols>true</DebugSymbols>
<DebugType>full</DebugType>
<Optimize>false</Optimize>
<OutputPath>bin\Debug\</OutputPath>
<DefineConstants>DEBUG;TRACE</DefineConstants>
<ErrorReport>prompt</ErrorReport>
<WarningLevel>4</WarningLevel>
</PropertyGroup>
<PropertyGroup Condition=" '$(Configuration)|$(Platform)' == 'Release|AnyCPU' ">
<PlatformTarget>AnyCPU</PlatformTarget>
<DebugType>pdbonly</DebugType>
<Optimize>true</Optimize>
<OutputPath>bin\Release\</OutputPath>
<DefineConstants>TRACE</DefineConstants>
<ErrorReport>prompt</ErrorReport>
<WarningLevel>4</WarningLevel>
</PropertyGroup>
<PropertyGroup>
<ApplicationIcon>USB.ico</ApplicationIcon>
</PropertyGroup>
<ItemGroup>
<Reference Include="System" />
<Reference Include="System.Core" />
<Reference Include="System.Xml.Linq" />
<Reference Include="System.Data.DataSetExtensions" />
<Reference Include="Microsoft.CSharp" />
<Reference Include="System.Data" />
<Reference Include="System.Xml" />
</ItemGroup>
<ItemGroup>
<Compile Include="Program.cs" />
<Compile Include="Properties\AssemblyInfo.cs" />
</ItemGroup>
<ItemGroup>
<None Include="App.config" />
</ItemGroup>
<ItemGroup>
<Content Include="USB.ico" />
</ItemGroup>
<Import Project="$(MSBuildToolsPath)\Microsoft.CSharp.targets" />
<!-- To modify your build process, add your task inside one of the targets below and uncomment it.
Other similar extension points exist, see Microsoft.Common.targets.
<Target Name="BeforeBuild">
</Target>
<Target Name="AfterBuild">
</Target>
-->
</Project>

82
hardware/ModelSim/USTCRVSoC.mpf
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@ -448,50 +448,50 @@ Project_Version = 6
Project_DefaultLib = work Project_DefaultLib = work
Project_SortMethod = unused Project_SortMethod = unused
Project_Files_Count = 22 Project_Files_Count = 22
Project_File_0 = ../RTL/dual_read_port_ram_32x32.sv Project_File_0 = ../RTL/vga_char_86x32.sv
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551597268 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551536388 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 20 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = ../RTL/vga_char_86x32.sv Project_File_1 = ../RTL/dual_read_port_ram_32x32.sv
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1551536388 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551597268 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_2 = ../RTL/ram128B.sv Project_File_2 = ../RTL/uart_rx.sv
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1551597237 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1549876350 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = ../RTL/uart_rx.sv Project_File_3 = ../RTL/ram128B.sv
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1549876350 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551597237 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = ../RTL/instr_rom.sv Project_File_4 = ../RTL/instr_rom.sv
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551863110 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1552416592 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_5 = ../RTL/video_ram.sv Project_File_5 = ../RTL/video_ram.sv
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551536461 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551536461 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_6 = ../RTL/soc_top.sv Project_File_6 = ../RTL/soc_top.sv
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551587626 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1552152562 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_7 = ../RTL/core_ex_branch_judge.sv Project_File_7 = ../RTL/ram.sv
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1549876350 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551597245 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_8 = ../RTL/ram.sv Project_File_8 = ../RTL/ram_bus_wrapper.sv
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551597245 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1550846066 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_9 = ../RTL/ram_bus_wrapper.sv Project_File_9 = ../RTL/core_bus_wrapper.sv
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1550846066 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1552153482 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_10 = ../RTL/core_bus_wrapper.sv Project_File_10 = ../RTL/core_alu.sv
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551591033 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1552301004 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_11 = ../RTL/core_alu.sv Project_File_11 = ../RTL/char8x16_rom.sv
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551588536 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551539060 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_12 = ../RTL/char8x16_rom.sv Project_File_12 = ../RTL/core_top.sv
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551539060 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1552364652 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_13 = ../RTL/core_top.sv Project_File_13 = ../RTL/soc_top_tb.sv
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551597558 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551980366 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_14 = ../RTL/soc_top_tb.sv Project_File_14 = ../RTL/user_uart_tx.sv
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551861246 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551512538 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 19 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_15 = ../RTL/user_uart_tx.sv Project_File_15 = ../RTL/uart_tx_line.sv
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551512538 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551092170 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_16 = ../RTL/uart_tx_line.sv Project_File_16 = ../RTL/core_regfile.sv
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1551092170 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551587650 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_17 = ../RTL/core_regfile.sv Project_File_17 = ../RTL/isp_uart.sv
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551587650 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1553085889 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_18 = ../RTL/isp_uart.sv Project_File_18 = ../RTL/core_id_stage.sv
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1551102643 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1552301088 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_19 = ../RTL/core_id_stage.sv Project_File_19 = ../RTL/core_id_segreg.sv
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551588579 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1552291334 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_20 = ../RTL/naive_bus.sv Project_File_20 = ../RTL/naive_bus_router.sv
Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1549876350 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1549876350 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_21 = ../RTL/naive_bus_router.sv Project_File_21 = ../RTL/naive_bus.sv
Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1549876350 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1549876350 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0
Project_Sim_Count = 0 Project_Sim_Count = 0
Project_Folder_Count = 0 Project_Folder_Count = 0
Echo_Compile_Output = 0 Echo_Compile_Output = 0

458
hardware/ModelSim/work/_info
View File

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Z31 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv Z31 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv
L0 1 L0 1
@ -64,7 +64,7 @@ r1
31 31
Z32 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv| Z32 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv|
R12 R12
Z33 !s108 1551863114.765000 Z33 !s108 1553097470.345000
Z34 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv| Z34 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv|
!i10b 1 !i10b 1
!s85 0 !s85 0
@ -91,445 +91,467 @@ Z44 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv|
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
vcore_id_stage vcore_id_segreg
R1 R1
Z45 !s100 @Z4XI5;0Bfzel18A7k<PT0 Z45 !s100 NmNT@]NH@0I`ElC3^a=Lo0
Z46 IMTUT@llRSg7kOM`PLzHjX2 Z46 In63?fN7CjS8LQG3S<]G]A3
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S1 S1
R6 R6
Z49 w1551588579 Z49 w1552291334
Z50 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv Z50 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv
Z51 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv Z51 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv
L0 2
R10
r1
31
Z52 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv|
R12
Z53 !s108 1553097470.416000
Z54 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv|
!i10b 1
!s85 0
!s101 -O0
vcore_id_stage
R1
Z55 !s100 GJfVNLR7z^<kiCg<4L]b^1
Z56 IW2gE_DGf2`B1c4gHVRl[>1
Z57 VndjbGAd]39<]>2=o9ZJ:=1
Z58 !s105 core_id_stage_sv_unit
S1
R6
Z59 w1552301088
Z60 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv
Z61 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv
L0 1 L0 1
R10 R10
r1 r1
31 31
Z52 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv| Z62 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv|
R12 R12
Z53 !s108 1551863114.900000 Z63 !s108 1553097470.490000
Z54 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv| Z64 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv|
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
vcore_regfile vcore_regfile
R1 R1
Z55 !s100 I^YE54Zo0N7Mh6`QiI<Oz3 Z65 !s100 I^YE54Zo0N7Mh6`QiI<Oz3
Z56 IoCmXUMJPHAOdI=TTQ4@AZ1 Z66 IoCmXUMJPHAOdI=TTQ4@AZ1
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Z58 !s105 core_regfile_sv_unit Z68 !s105 core_regfile_sv_unit
S1 S1
R6 R6
Z59 w1551587650 Z69 w1551587650
Z60 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv Z70 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv
Z61 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv Z71 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv
L0 2 L0 2
R10 R10
r1 r1
31 31
Z62 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv| Z72 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv|
R12 R12
Z63 !s108 1551863114.978000 Z73 !s108 1553097470.561000
Z64 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv| Z74 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv|
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
vcore_top vcore_top
R1 R1
Z65 !s100 HMLmk@@aBh3oW3M2oh>5F0 Z75 !s100 Zo9bz^7ThnSCB?@jM>2<z2
Z66 IYX6W^T9h03:[15`LXl06K2 Z76 IHiI>OZW_a7lHo3m1FDmQG2
Z67 Vi7?O@h6m5O3BFF`kIdBUC2 Z77 Vi7?O@h6m5O3BFF`kIdBUC2
Z68 !s105 core_top_sv_unit Z78 !s105 core_top_sv_unit
S1 S1
R6 R6
Z69 w1551597558 Z79 w1552364652
Z70 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv Z80 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv
Z71 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv Z81 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv
L0 1 L0 1
R10 R10
r1 r1
31 31
Z72 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv| Z82 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv|
R12 R12
Z73 !s108 1551863115.052000 Z83 !s108 1553097470.631000
Z74 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv| Z84 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv|
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
vdual_read_port_ram_32x32 vdual_read_port_ram_32x32
R1 R1
!i10b 1 Z85 !s100 fdb;joBRd?Kbjj708`H@K2
Z75 !s100 fdb;joBRd?Kbjj708`H@K2 Z86 IPRWQ3P[Jk_E9z0fS4::gE0
Z76 IPRWQ3P[Jk_E9z0fS4::gE0 Z87 Vl@[MQJH:k3R5DJ2AcgRCH1
Z77 Vl@[MQJH:k3R5DJ2AcgRCH1 Z88 !s105 dual_read_port_ram_32x32_sv_unit
Z78 !s105 dual_read_port_ram_32x32_sv_unit
S1 S1
R6 R6
Z79 w1551597268 Z89 w1551597268
Z80 8E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv Z90 8E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv
Z81 FE:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv Z91 FE:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv
L0 1 L0 1
R10 R10
r1 r1
!s85 0
31 31
!s108 1551863116.221000 Z92 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv|
!s107 E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv|
Z82 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv|
!s101 -O0
R12 R12
Z93 !s108 1553097470.710000
Z94 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv|
!i10b 1
!s85 0
!s101 -O0
vinstr_rom vinstr_rom
R1 R1
Z83 I0[kRSH:VXl_HDnGJiGS5]3 Z95 !s100 Bd]Z1a^3]kD30E<26M`Lm1
Z84 Vg27TzclZ3S3@lBLMlA`?L1 Z96 IOc1Uo_kS08]?1_CKOHHU?0
Z85 !s105 instr_rom_sv_unit Z97 Vg27TzclZ3S3@lBLMlA`?L1
Z98 !s105 instr_rom_sv_unit
S1 S1
R6 R6
Z86 w1551863110 Z99 w1552416592
Z87 8E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv Z100 8E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv
Z88 FE:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv Z101 FE:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv
L0 1 L0 1
R10 R10
r1 r1
31 31
Z89 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv| Z102 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv|
R12 R12
Z90 !s100 m@TEV9E3O2B7:E0R:[VXF3 Z103 !s108 1553097470.788000
Z91 !s108 1551863115.129000 Z104 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv|
Z92 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv|
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
visp_uart visp_uart
R1 R1
Z93 !s100 @dmH];GG>K;lS7PljQ:Am1 Z105 !s100 [9[iR_cBcg;?;bX>dKeaB0
Z94 I_4gBZG2Ib<khkdHbSDz?I0 Z106 ICh9mFzgfo8b@4QmO624@U1
Z95 V@@jZ3Y6;d=WD@H08`7cWF3 Z107 V@@jZ3Y6;d=WD@H08`7cWF3
Z96 !s105 isp_uart_sv_unit Z108 !s105 isp_uart_sv_unit
S1 S1
R6 R6
Z97 w1551102643 Z109 w1553085889
Z98 8E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv Z110 8E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv
Z99 FE:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv Z111 FE:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv
L0 3 L0 3
R10 R10
r1 r1
31 31
Z100 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv| Z112 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv|
R12 R12
Z101 !s108 1551863115.210000 Z113 !s108 1553097470.870000
Z102 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv| Z114 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv|
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
Ynaive_bus Ynaive_bus
R1 R1
Z103 !s100 gFz59kzW]I]nGiaVoSo3O2 Z115 !s100 gFz59kzW]I]nGiaVoSo3O2
Z104 Idj:03TOO?jDHzf[0c?lJ`2 Z116 Idj:03TOO?jDHzf[0c?lJ`2
Z105 VKXR@0<URHIKN=UGzERidm1 Z117 VKXR@0<URHIKN=UGzERidm1
Z106 !s105 naive_bus_sv_unit Z118 !s105 naive_bus_sv_unit
S1 S1
R6 R6
R39 R39
Z107 8E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv Z119 8E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv
Z108 FE:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv Z120 FE:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv
L0 4 L0 4
R10 R10
r1 r1
31 31
Z109 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv| Z121 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv|
R12 R12
Z110 !s108 1551863115.283000 Z122 !s108 1553097470.946000
Z111 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv| Z123 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv|
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
vnaive_bus_router vnaive_bus_router
R1 R1
Z112 !s100 nSRUejF=Q5]HdBmmdfzLA1 Z124 !s100 nSRUejF=Q5]HdBmmdfzLA1
Z113 I^NC0W49]?el6;z^6BojXI2 Z125 I^NC0W49]?el6;z^6BojXI2
Z114 VS<O=OM<>7@f0]AeUc<_5c0 Z126 VS<O=OM<>7@f0]AeUc<_5c0
Z115 !s105 naive_bus_router_sv_unit Z127 !s105 naive_bus_router_sv_unit
S1 S1
R6 R6
R39 R39
Z116 8E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv Z128 8E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv
Z117 FE:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv Z129 FE:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv
L0 1 L0 1
R10 R10
r1 r1
31 31
Z118 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv| Z130 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv|
R12 R12
Z119 !s108 1551863115.349000 Z131 !s108 1553097471.014000
Z120 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv| Z132 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv|
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
vram vram
R1 R1
Z121 !s100 TMn[TG8XXmK^UL@k7`ikC0 Z133 !s100 TMn[TG8XXmK^UL@k7`ikC0
Z122 INIlD0C@nO9Rk96M@_1B?92 Z134 INIlD0C@nO9Rk96M@_1B?92
Z123 VjLloJg4mGdQ3i@ojJbWma2 Z135 VjLloJg4mGdQ3i@ojJbWma2
Z124 !s105 ram_sv_unit Z136 !s105 ram_sv_unit
S1 S1
R6 R6
Z125 w1551597245 Z137 w1551597245
Z126 8E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv Z138 8E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv
Z127 FE:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv Z139 FE:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv
L0 1 L0 1
R10 R10
r1 r1
31 31
Z128 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv| Z140 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv|
R12 R12
Z129 !s108 1551863115.424000 Z141 !s108 1553097471.091000
Z130 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv| Z142 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv|
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
vram128B vram128B
R1 R1
Z131 !s100 fJC_h9DFSL4_5I>=K<7NW1 Z143 !s100 fJC_h9DFSL4_5I>=K<7NW1
Z132 Il^2=EAV5B4zF?@PSE:S;I3 Z144 Il^2=EAV5B4zF?@PSE:S;I3
Z133 V5VITH=L0J_KXn908[zCL23 Z145 V5VITH=L0J_KXn908[zCL23
Z134 !s105 ram128B_sv_unit Z146 !s105 ram128B_sv_unit
S1 S1
R6 R6
Z135 w1551597237 Z147 w1551597237
Z136 8E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv Z148 8E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv
Z137 FE:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv Z149 FE:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv
L0 1 L0 1
R10 R10
r1 r1
31 31
Z138 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv| Z150 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv|
R12 R12
Z139 nram128@b Z151 nram128@b
Z140 !s108 1551863116.071000 Z152 !s108 1553097471.234000
Z141 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv| Z153 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv|
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
vram_bus_wrapper vram_bus_wrapper
R1 R1
Z142 !s100 U?Io3WFYaekAS0T@dW=V43 Z154 !s100 U?Io3WFYaekAS0T@dW=V43
Z143 I?^eTo:Go<IUo<UVJm@aFd0 Z155 I?^eTo:Go<IUo<UVJm@aFd0
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Z145 !s105 ram_bus_wrapper_sv_unit Z157 !s105 ram_bus_wrapper_sv_unit
S1 S1
R6 R6
Z146 w1550846066 Z158 w1550846066
Z147 8E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv Z159 8E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv
Z148 FE:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv Z160 FE:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv
L0 1 L0 1
R10 R10
r1 r1
31 31
Z149 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv| Z161 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv|
R12 R12
Z150 !s108 1551863115.494000 Z162 !s108 1553097471.164000
Z151 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv| Z163 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv|
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
vsoc_top vsoc_top
R1 R1
Z152 !s100 c7@DJ3i4aKznCaD6`OcAf2 Z164 !s100 c7@DJ3i4aKznCaD6`OcAf2
Z153 IY3<DJCiMG<UdHWc8M42J[2 Z165 IY3<DJCiMG<UdHWc8M42J[2
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Z155 !s105 soc_top_sv_unit Z167 !s105 soc_top_sv_unit
S1 S1
R6 R6
Z156 w1551587626 Z168 w1552152562
Z157 8E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv Z169 8E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv
Z158 FE:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv Z170 FE:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv
L0 1 L0 1
R10 R10
r1 r1
31 31
Z159 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv| Z171 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv|
R12 R12
Z160 !s108 1551863115.565000 Z172 !s108 1553097471.329000
Z161 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv| Z173 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv|
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
vsoc_top_tb vsoc_top_tb
R1 R1
Z162 !s100 >5zad59i52f<6jYFNl[UE2 Z174 !s100 >5zad59i52f<6jYFNl[UE2
Z163 I7hf=@mlD?E>:AKDSDL2O]1 Z175 I7hf=@mlD?E>:AKDSDL2O]1
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Z165 !s105 soc_top_tb_sv_unit Z177 !s105 soc_top_tb_sv_unit
S1 S1
R6 R6
Z166 w1551861246 Z178 w1551980366
Z167 8E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv Z179 8E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv
Z168 FE:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv Z180 FE:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv
L0 1 L0 1
R10 R10
r1 r1
31 31
Z169 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv| Z181 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv|
R12 R12
Z170 !s108 1551863115.642000 Z182 !s108 1553097471.403000
Z171 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv| Z183 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv|
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
vuart_rx vuart_rx
R1 R1
Z172 !s100 :`YDkKm;LaUQOjOXmaKB:0 Z184 !s100 :`YDkKm;LaUQOjOXmaKB:0
Z173 IL9Ji^>V6GeZ<;c7I`o3LQ1 Z185 IL9Ji^>V6GeZ<;c7I`o3LQ1
Z174 Vh0;PUSD9VYIXe2P@6jV9;0 Z186 Vh0;PUSD9VYIXe2P@6jV9;0
Z175 !s105 uart_rx_sv_unit Z187 !s105 uart_rx_sv_unit
S1 S1
R6 R6
R39 R39
Z176 8E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv Z188 8E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv
Z177 FE:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv Z189 FE:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv
L0 1 L0 1
R10 R10
r1 r1
31 31
Z178 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv| Z190 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv|
R12 R12
Z179 !s108 1551863115.708000 Z191 !s108 1553097471.473000
Z180 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv| Z192 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv|
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
vuart_tx_line vuart_tx_line
R1 R1
Z181 !s100 WEQ@68?0=RGj1iFdbOOcP2 Z193 !s100 WEQ@68?0=RGj1iFdbOOcP2
Z182 IK1;[1cPPe^6]7LKQ15Lf21 Z194 IK1;[1cPPe^6]7LKQ15Lf21
Z183 VW`_FG<Oo:1]3K5g>fF=@_3 Z195 VW`_FG<Oo:1]3K5g>fF=@_3
Z184 !s105 uart_tx_line_sv_unit Z196 !s105 uart_tx_line_sv_unit
S1 S1
R6 R6
Z185 w1551092170 Z197 w1551092170
Z186 8E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv Z198 8E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv
Z187 FE:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv Z199 FE:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv
L0 2 L0 2
R10 R10
r1 r1
31 31
Z188 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv| Z200 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv|
R12 R12
Z189 !s108 1551863115.776000 Z201 !s108 1553097471.550000
Z190 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv| Z202 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv|
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
vuser_uart_tx vuser_uart_tx
R1 R1
Z191 !s100 YA]KWMS3fOD:CQT@0Y9C83 Z203 !s100 YA]KWMS3fOD:CQT@0Y9C83
Z192 I0JOL7FjkENP;iNc25_jl92 Z204 I0JOL7FjkENP;iNc25_jl92
Z193 V<1FQ0oW1UA`j`9IX[bcdE1 Z205 V<1FQ0oW1UA`j`9IX[bcdE1
Z194 !s105 user_uart_tx_sv_unit Z206 !s105 user_uart_tx_sv_unit
S1 S1
R6 R6
Z195 w1551512538 Z207 w1551512538
Z196 8E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv Z208 8E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv
Z197 FE:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv Z209 FE:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv
L0 2 L0 2
R10 R10
r1 r1
31 31
Z198 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv| Z210 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv|
R12 R12
Z199 !s108 1551863115.848000 Z211 !s108 1553097471.620000
Z200 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv| Z212 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv|
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
vvga vvga
R1 R1
Z201 !s100 9f0>Y=7iSmCK^QMkzVhdz2 Z213 !s100 9f0>Y=7iSmCK^QMkzVhdz2
Z202 IK]n:1gV]8z:A^2D<Og@_H3 Z214 IK]n:1gV]8z:A^2D<Og@_H3
Z203 VR^SlDkaag;z6W]0_6nChW1 Z215 VR^SlDkaag;z6W]0_6nChW1
Z204 !s105 video_ram_sv_unit Z216 !s105 video_ram_sv_unit
S1 S1
R6 R6
Z205 w1551166630 Z217 w1551166630
Z206 8E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv Z218 8E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv
Z207 FE:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv Z219 FE:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv
Z208 L0 147 Z220 L0 147
R10 R10
r1 r1
31 31
Z209 !s108 1551505561.076000 Z221 !s108 1551505561.076000
Z210 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv| Z222 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv|
Z211 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv| Z223 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv|
R12 R12
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
vvga_char_86x32 vvga_char_86x32
R1 R1
Z212 !s100 c>9AM[`i8>D>79]^5c=iL3 Z224 !s100 c>9AM[`i8>D>79]^5c=iL3
Z213 IXCM=P_6km0Hk^IPzU0S0N1 Z225 IXCM=P_6km0Hk^IPzU0S0N1
Z214 VE<z=Jzg_7oWJ0YmQX2]MU3 Z226 VE<z=Jzg_7oWJ0YmQX2]MU3
Z215 !s105 vga_char_86x32_sv_unit Z227 !s105 vga_char_86x32_sv_unit
S1 S1
R6 R6
Z216 w1551536388 Z228 w1551536388
Z217 8E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv Z229 8E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv
Z218 FE:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv Z230 FE:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv
L0 1 L0 1
R10 R10
r1 r1
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Z219 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv| Z231 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv|
R12 R12
!i10b 1 !i10b 1
!s85 0 !s85 0
Z220 !s108 1551863116.142000 Z232 !s108 1553097471.696000
Z221 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv| Z233 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv|
!s101 -O0 !s101 -O0
vvgaChar98x36 vvgaChar98x36
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Z223 IaM^Q2hPSE=jENCH[nQnb^0 Z235 IaM^Q2hPSE=jENCH[nQnb^0
Z224 VkYR^g;?9@>9aFYMNc5Beh0 Z236 VkYR^g;?9@>9aFYMNc5Beh0
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S1 S1
R6 R6
R205 R217
R206 R218
R207 R219
L0 82 L0 82
R10 R10
r1 r1
31 31
R209 R221
R210 R222
R211 R223
R12 R12
Z225 nvga@char98x36 Z237 nvga@char98x36
!i10b 1 !i10b 1
!s85 0 !s85 0
!s101 -O0 !s101 -O0
vvideo_ram vvideo_ram
R1 R1
Z226 !s100 5Km:lJ5=^^Z=H?Vg4dnQM0 !i10b 1
Z227 I8o<maB2Sg[@UYiL96IX_I3 Z238 !s100 5Km:lJ5=^^Z=H?Vg4dnQM0
Z228 V5JnUKWk;WPc^ACUnLK1_E3 Z239 I8o<maB2Sg[@UYiL96IX_I3
R204 Z240 V5JnUKWk;WPc^ACUnLK1_E3
R216
S1 S1
R6 R6
Z229 w1551536461 Z241 w1551536461
R206 R218
R207 R219
L0 1 L0 1
R10 R10
r1 r1
31
R211
R12
Z230 !s108 1551863115.923000
R210
!i10b 1
!s85 0 !s85 0
31
!s108 1553097471.776000
!s107 E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv|
R223
!s101 -O0 !s101 -O0
R12

23
hardware/RTL/isp_uart.sv
View File

@ -112,7 +112,11 @@ always @ (posedge clk)
send_type <= NONE; send_type <= NONE;
tx_data <= "wr done "; tx_data <= "wr done ";
end else if(rx_ready && `E) begin end else if(rx_ready && `E) begin
if(fsm==CMD) begin if(isp_user_sel==1'b0) begin
tx_start<= 1'b1;
send_type <= SELCLOSE;
tx_data <= "\r\ndebug ";
end else if(fsm==CMD) begin
tx_start<= 1'b1; tx_start<= 1'b1;
send_type <= RST; send_type <= RST;
tx_data <= "rst done"; tx_data <= "rst done";
@ -120,10 +124,6 @@ always @ (posedge clk)
tx_start<= 1'b1; tx_start<= 1'b1;
send_type <= SELOPEN; send_type <= SELOPEN;
tx_data <= "user "; tx_data <= "user ";
end else if(fsm==CLOSE) begin
tx_start<= 1'b1;
send_type <= SELCLOSE;
tx_data <= "\r\ndebug ";
end else if(fsm==TRASH) begin end else if(fsm==TRASH) begin
tx_start<= 1'b1; tx_start<= 1'b1;
send_type <= NONE; send_type <= NONE;
@ -143,7 +143,7 @@ always @ (posedge clk)
always @ (posedge clk) always @ (posedge clk)
if(uart_tx_line_fin && (send_type == RST || send_type == SELOPEN) ) if(uart_tx_line_fin && (send_type == RST || send_type == SELOPEN) )
isp_user_sel <= 1'b0; // 切换到USER模式 isp_user_sel <= 1'b0; // 切换到USER模式
else if(rx_ready && `E && (fsm==CLOSE) ) else if(rx_ready && `E )
isp_user_sel <= 1'b1; // 切换到DEBUG模式 isp_user_sel <= 1'b1; // 切换到DEBUG模式
always @ (posedge clk) always @ (posedge clk)
@ -160,8 +160,6 @@ always @ (posedge clk)
wr_data <= 0; wr_data <= 0;
end else if(`OP) begin end else if(`OP) begin
fsm <= OPEN; fsm <= OPEN;
end else if(`CL) begin
fsm <= CLOSE;
end else if(`S || `E) begin end else if(`S || `E) begin
fsm <= NEW; fsm <= NEW;
addr <= 0; addr <= 0;
@ -179,13 +177,6 @@ always @ (posedge clk)
end else begin end else begin
fsm <= TRASH; fsm <= TRASH;
end end
CLOSE : if (`E) begin
fsm <= NEW; // cmd close ok!
end else if(`S) begin
fsm <= CLOSE;
end else begin
fsm <= TRASH;
end
CMD : if (`E) begin CMD : if (`E) begin
o_boot_addr <= {wr_data[31:2],2'b00}; // 设置复位的boot地址，后两位截断(双字对齐) o_boot_addr <= {wr_data[31:2],2'b00}; // 设置复位的boot地址，后两位截断(双字对齐)
fsm <= NEW; // cmd ok! fsm <= NEW; // cmd ok!
@ -194,7 +185,7 @@ always @ (posedge clk)
end else if(`S) begin end else if(`S) begin
fsm <= CMD; fsm <= CMD;
end else if(`N) begin end else if(`N) begin
fsm <= CMD; // r字符后出现数字，说明该复位命令要指定boot地址， fsm <= CMD; // r字符后出现数字，说明该复位命令要指定boot地址<EFBFBD><EFBFBD>?
wr_data <= {wr_data[27:0], rx_binary_l}; // get a data wr_data <= {wr_data[27:0], rx_binary_l}; // get a data
end else begin end else begin
fsm <= TRASH; fsm <= TRASH;

46
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/gui_handlers.wdf
View File

@ -1,8 +1,9 @@
version:1 version:1
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00
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@ -11,10 +12,11 @@ version:1
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6970636f7265766965775f7461626265645f70616e65:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6970636f7265766965775f7461626265645f70616e65:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c6f676d6f6e69746f725f6d6f6e69746f72:34:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c6f676d6f6e69746f725f6d6f6e69746f72:34:00:00
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@ -22,7 +24,7 @@ version:1
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eof:3049335905 eof:529949899

24
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/java_command_handlers.wdf
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hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/project.wpc
View File

@ -1,4 +1,4 @@
version:1 version:1
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eof: eof:

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hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/synthesis.wdf
View File

@ -34,6 +34,6 @@ version:1
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hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/webtalk_pa.xml
View File

@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Tue Mar 12 13:15:08 2019"> <application name="pa" timeStamp="Wed Mar 20 23:49:42 2019">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="802f49394334431ea9abba122e836e9e" type="ProjectID"/> <property name="ProjectID" value="802f49394334431ea9abba122e836e9e" type="ProjectID"/>
<property name="ProjectIteration" value="29" type="ProjectIteration"/> <property name="ProjectIteration" value="33" type="ProjectIteration"/>
</section> </section>
<section name="PlanAhead Usage" visible="true"> <section name="PlanAhead Usage" visible="true">
<item name="Project Data"> <item name="Project Data">
@ -17,31 +17,34 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/> <property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item> </item>
<item name="Java Command Handlers"> <item name="Java Command Handlers">
<property name="AddSources" value="10" type="JavaHandler"/> <property name="AddSources" value="11" type="JavaHandler"/>
<property name="AutoConnectTarget" value="10" type="JavaHandler"/> <property name="AutoConnectTarget" value="12" type="JavaHandler"/>
<property name="CoreView" value="1" type="JavaHandler"/> <property name="CoreView" value="1" type="JavaHandler"/>
<property name="CustomizeCore" value="1" type="JavaHandler"/> <property name="CustomizeCore" value="1" type="JavaHandler"/>
<property name="EditDelete" value="7" type="JavaHandler"/> <property name="EditDelete" value="7" type="JavaHandler"/>
<property name="LaunchProgramFpga" value="20" type="JavaHandler"/> <property name="LaunchProgramFpga" value="26" type="JavaHandler"/>
<property name="NewProject" value="1" type="JavaHandler"/> <property name="NewProject" value="1" type="JavaHandler"/>
<property name="OpenHardwareManager" value="38" type="JavaHandler"/> <property name="OpenHardwareManager" value="47" type="JavaHandler"/>
<property name="OpenRecentTarget" value="11" type="JavaHandler"/> <property name="OpenRecentTarget" value="13" type="JavaHandler"/>
<property name="ProgramDevice" value="21" type="JavaHandler"/> <property name="ProgramDevice" value="27" type="JavaHandler"/>
<property name="ReportUtilization" value="1" type="JavaHandler"/> <property name="ReportUtilization" value="1" type="JavaHandler"/>
<property name="RunBitgen" value="15" type="JavaHandler"/> <property name="RunBitgen" value="17" type="JavaHandler"/>
<property name="RunImplementation" value="13" type="JavaHandler"/> <property name="RunImplementation" value="15" type="JavaHandler"/>
<property name="RunSynthesis" value="17" type="JavaHandler"/> <property name="RunSynthesis" value="20" type="JavaHandler"/>
<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/> <property name="SaveFileProxyHandler" value="1" type="JavaHandler"/>
<property name="SetTopNode" value="2" type="JavaHandler"/> <property name="SetTopNode" value="3" type="JavaHandler"/>
<property name="ShowView" value="10" type="JavaHandler"/> <property name="ShowView" value="10" type="JavaHandler"/>
<property name="SimulationRun" value="1" type="JavaHandler"/>
<property name="SimulationRunForTime" value="9" type="JavaHandler"/>
<property name="UpdateRegId" value="1" type="JavaHandler"/> <property name="UpdateRegId" value="1" type="JavaHandler"/>
<property name="ViewTaskSynthesis" value="2" type="JavaHandler"/> <property name="ViewTaskSynthesis" value="2" type="JavaHandler"/>
</item> </item>
<item name="Gui Handlers"> <item name="Gui Handlers">
<property name="AddSrcWizard_SPECIFY_HDL_NETLIST_BLOCK_DESIGN" value="2" type="GuiHandlerData"/> <property name="AddSrcWizard_SPECIFY_HDL_NETLIST_BLOCK_DESIGN" value="2" type="GuiHandlerData"/>
<property name="AddSrcWizard_SPECIFY_SIMULATION_SPECIFIC_HDL_FILES" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="5" type="GuiHandlerData"/> <property name="BaseDialog_CANCEL" value="5" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="30" type="GuiHandlerData"/> <property name="BaseDialog_OK" value="32" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="1" type="GuiHandlerData"/> <property name="CmdMsgDialog_OK" value="2" type="GuiHandlerData"/>
<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="2" type="GuiHandlerData"/> <property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="2" type="GuiHandlerData"/>
<property name="ConstraintsChooserPanel_ADD_FILES" value="1" type="GuiHandlerData"/> <property name="ConstraintsChooserPanel_ADD_FILES" value="1" type="GuiHandlerData"/>
<property name="ConstraintsChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/> <property name="ConstraintsChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
@ -50,10 +53,11 @@ This means code written to parse this file will need to be revisited each subseq
<property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/> <property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_TYPE" value="1" type="GuiHandlerData"/> <property name="CreateSrcFileDialog_FILE_TYPE" value="1" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/> <property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="183" type="GuiHandlerData"/> <property name="FileSetPanel_FILE_SET_PANEL_TREE" value="193" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="52" type="GuiHandlerData"/> <property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="63" type="GuiHandlerData"/>
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/> <property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="7" type="GuiHandlerData"/> <property name="GraphicalView_ZOOM_OUT" value="13" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="8" type="GuiHandlerData"/>
<property name="IPCoreView_TABBED_PANE" value="2" type="GuiHandlerData"/> <property name="IPCoreView_TABBED_PANE" value="2" type="GuiHandlerData"/>
<property name="LogMonitor_MONITOR" value="4" type="GuiHandlerData"/> <property name="LogMonitor_MONITOR" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/> <property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
@ -61,7 +65,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="MainMenuMgr_TOOLS" value="1" type="GuiHandlerData"/> <property name="MainMenuMgr_TOOLS" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_VIEW" value="2" type="GuiHandlerData"/> <property name="MainMenuMgr_VIEW" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="2" type="GuiHandlerData"/> <property name="MainMenuMgr_WINDOW" value="2" type="GuiHandlerData"/>
<property name="MainToolbarMgr_RUN" value="23" type="GuiHandlerData"/> <property name="MainToolbarMgr_RUN" value="26" type="GuiHandlerData"/>
<property name="MainWinMenuMgr_LAYOUT" value="2" type="GuiHandlerData"/> <property name="MainWinMenuMgr_LAYOUT" value="2" type="GuiHandlerData"/>
<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/> <property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_SEVERITY" value="2" type="GuiHandlerData"/> <property name="MsgTreePanel_MESSAGE_SEVERITY" value="2" type="GuiHandlerData"/>
@ -69,49 +73,53 @@ This means code written to parse this file will need to be revisited each subseq
<property name="MsgView_CRITICAL_WARNINGS" value="6" type="GuiHandlerData"/> <property name="MsgView_CRITICAL_WARNINGS" value="6" type="GuiHandlerData"/>
<property name="MsgView_WARNING_MESSAGES" value="2" type="GuiHandlerData"/> <property name="MsgView_WARNING_MESSAGES" value="2" type="GuiHandlerData"/>
<property name="NetlistTreeView_NETLIST_TREE" value="15" type="GuiHandlerData"/> <property name="NetlistTreeView_NETLIST_TREE" value="15" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_SOURCES" value="10" type="GuiHandlerData"/> <property name="PACommandNames_ADD_SOURCES" value="11" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="10" type="GuiHandlerData"/> <property name="PACommandNames_AUTO_CONNECT_TARGET" value="12" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="15" type="GuiHandlerData"/> <property name="PACommandNames_AUTO_UPDATE_HIER" value="17" type="GuiHandlerData"/>
<property name="PACommandNames_GOTO_NETLIST_DESIGN" value="1" type="GuiHandlerData"/> <property name="PACommandNames_GOTO_NETLIST_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_LICENSE_MANAGE" value="1" type="GuiHandlerData"/> <property name="PACommandNames_LICENSE_MANAGE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_REPORTS_WINDOW" value="1" type="GuiHandlerData"/> <property name="PACommandNames_REPORTS_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_BITGEN" value="16" type="GuiHandlerData"/> <property name="PACommandNames_RUN_BITGEN" value="18" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_IMPLEMENTATION" value="3" type="GuiHandlerData"/> <property name="PACommandNames_RUN_IMPLEMENTATION" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_SYNTHESIS" value="17" type="GuiHandlerData"/> <property name="PACommandNames_RUN_SYNTHESIS" value="20" type="GuiHandlerData"/>
<property name="PACommandNames_SET_AS_TOP" value="2" type="GuiHandlerData"/> <property name="PACommandNames_SET_AS_TOP" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_LIVE_RUN" value="9" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="1" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="11" type="GuiHandlerData"/> <property name="PAViews_CODE" value="11" type="GuiHandlerData"/>
<property name="PAViews_DEVICE" value="2" type="GuiHandlerData"/> <property name="PAViews_DEVICE" value="2" type="GuiHandlerData"/>
<property name="PartChooser_FAMILY_CHOOSER" value="1" type="GuiHandlerData"/> <property name="PartChooser_FAMILY_CHOOSER" value="1" type="GuiHandlerData"/>
<property name="PartChooser_PARTS" value="2" type="GuiHandlerData"/> <property name="PartChooser_PARTS" value="2" type="GuiHandlerData"/>
<property name="ProgramFpgaDialog_PROGRAM" value="18" type="GuiHandlerData"/> <property name="ProgramFpgaDialog_PROGRAM" value="24" type="GuiHandlerData"/>
<property name="ProgramFpgaDialog_SPECIFY_BITSTREAM_FILE" value="1" type="GuiHandlerData"/> <property name="ProgramFpgaDialog_SPECIFY_BITSTREAM_FILE" value="1" type="GuiHandlerData"/>
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/> <property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
<property name="ProgressDialog_CANCEL" value="1" type="GuiHandlerData"/>
<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="1" type="GuiHandlerData"/> <property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="1" type="GuiHandlerData"/>
<property name="ProjectNameChooser_PROJECT_NAME" value="2" type="GuiHandlerData"/> <property name="ProjectNameChooser_PROJECT_NAME" value="2" type="GuiHandlerData"/>
<property name="ProjectSummaryTimingPanel_PROJECT_SUMMARY_TIMING_PANEL_TABBED" value="17" type="GuiHandlerData"/> <property name="ProjectSummaryTimingPanel_PROJECT_SUMMARY_TIMING_PANEL_TABBED" value="17" type="GuiHandlerData"/>
<property name="ProjectSummaryUtilizationGadget_PROJECT_SUMMARY_UTILIZATION_GADGET_TABBED" value="2" type="GuiHandlerData"/> <property name="ProjectSummaryUtilizationGadget_PROJECT_SUMMARY_UTILIZATION_GADGET_TABBED" value="2" type="GuiHandlerData"/>
<property name="ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_PANEL_TABBED" value="5" type="GuiHandlerData"/> <property name="ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_PANEL_TABBED" value="5" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="7" type="GuiHandlerData"/> <property name="RDICommands_DELETE" value="7" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="5" type="GuiHandlerData"/>
<property name="RunGadget_RUN_GADGET_TABBED_PANE" value="1" type="GuiHandlerData"/> <property name="RunGadget_RUN_GADGET_TABBED_PANE" value="1" type="GuiHandlerData"/>
<property name="RunGadget_SHOW_ERROR" value="2" type="GuiHandlerData"/> <property name="RunGadget_SHOW_ERROR" value="2" type="GuiHandlerData"/>
<property name="RunGadget_SHOW_WARNING_AND_ERROR_MESSAGES_IN_MESSAGES" value="1" type="GuiHandlerData"/> <property name="RunGadget_SHOW_WARNING_AND_ERROR_MESSAGES_IN_MESSAGES" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/> <property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="3" type="GuiHandlerData"/> <property name="SaveProjectUtils_SAVE" value="5" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="6" type="GuiHandlerData"/> <property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="7" type="GuiHandlerData"/>
<property name="SrcChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/> <property name="SrcChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="12" type="GuiHandlerData"/> <property name="SrcMenu_IP_HIERARCHY" value="14" type="GuiHandlerData"/>
<property name="SrcMenu_REFRESH_HIERARCHY" value="1" type="GuiHandlerData"/> <property name="SrcMenu_REFRESH_HIERARCHY" value="1" type="GuiHandlerData"/>
<property name="StaleRunDialog_YES" value="1" type="GuiHandlerData"/> <property name="StaleRunDialog_YES" value="1" type="GuiHandlerData"/>
<property name="StateMonitor_RESET_RUN" value="1" type="GuiHandlerData"/> <property name="StateMonitor_RESET_RUN" value="1" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="6" type="GuiHandlerData"/> <property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="9" type="GuiHandlerData"/>
<property name="SyntheticaStateMonitor_CANCEL" value="2" type="GuiHandlerData"/> <property name="SyntheticaStateMonitor_CANCEL" value="3" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="2" type="GuiHandlerData"/> <property name="TaskBanner_CLOSE" value="3" type="GuiHandlerData"/>
<property name="TouchpointSurveyDialog_NO" value="1" type="GuiHandlerData"/> <property name="TouchpointSurveyDialog_NO" value="1" type="GuiHandlerData"/>
</item> </item>
<item name="Other"> <item name="Other">
<property name="GuiMode" value="40" type="GuiMode"/> <property name="GuiMode" value="46" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/> <property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="34" type="TclMode"/> <property name="TclMode" value="40" type="TclMode"/>
</item> </item>
</section> </section>
</application> </application>

4
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/xsim.wdf Normal file
View File

@ -0,0 +1,4 @@
version:1
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eof:241934075

2
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.hw/hw_1/hw.xml
View File

@ -10,7 +10,7 @@
<Properties Property="FULL_PROBES.FILE" value=""/> <Properties Property="FULL_PROBES.FILE" value=""/>
<Properties Property="PROBES.FILE" value=""/> <Properties Property="PROBES.FILE" value=""/>
<Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/Nexys4_USTCRVSoC_top.bit"/> <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/Nexys4_USTCRVSoC_top.bit"/>
<Properties Property="SLR.COUNT" value="1"/> <Properties Property="SLR.COUNT" value="C:/Users/wgg/AppData/Roaming/Xilinx/Vivado/1"/>
</Object> </Object>
</ObjectList> </ObjectList>
<probeset name="hw project" active="false"/> <probeset name="hw project" active="false"/>

25
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/compile.bat Normal file
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@ -0,0 +1,25 @@
@echo off
REM ****************************************************************************
REM Vivado (TM) v2017.4 (64-bit)
REM
REM Filename : compile.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for compiling the simulation design source files
REM
REM Generated by Vivado on Wed Mar 20 23:48:26 +0800 2019
REM SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
REM
REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
REM
REM usage: compile.bat
REM
REM ****************************************************************************
echo "xvlog --incr --relax -L xil_defaultlib -prj soc_top_tb_vlog.prj"
call xvlog --incr --relax -L xil_defaultlib -prj soc_top_tb_vlog.prj -log xvlog.log
call type xvlog.log > compile.log
if "%errorlevel%"=="1" goto END
if "%errorlevel%"=="0" goto SUCCESS
:END
exit 1
:SUCCESS
exit 0

45
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/compile.log Normal file
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@ -0,0 +1,45 @@
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module char8x16_rom
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module core_alu
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module core_bus_wrapper
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module core_id_segreg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module core_id_stage
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module core_regfile
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module core_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module dual_read_port_ram_32x32
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module instr_rom
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module isp_uart
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module naive_bus_router
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ram128B
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ram_bus_wrapper
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module soc_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_rx
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_tx_line
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module user_uart_tx
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module vga_char_86x32
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module video_ram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module soc_top_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl

23
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/elaborate.bat Normal file
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@ -0,0 +1,23 @@
@echo off
REM ****************************************************************************
REM Vivado (TM) v2017.4 (64-bit)
REM
REM Filename : elaborate.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for elaborating the compiled design
REM
REM Generated by Vivado on Wed Mar 20 23:48:30 +0800 2019
REM SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
REM
REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
REM
REM usage: elaborate.bat
REM
REM ****************************************************************************
call xelab -wto ddc8340f1eba4b8bbb076a11b9b82028 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot soc_top_tb_behav xil_defaultlib.soc_top_tb xil_defaultlib.glbl -log elaborate.log
if "%errorlevel%"=="0" goto SUCCESS
if "%errorlevel%"=="1" goto END
:END
exit 1
:SUCCESS
exit 0

34
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/elaborate.log Normal file
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@ -0,0 +1,34 @@
Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto ddc8340f1eba4b8bbb076a11b9b82028 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot soc_top_tb_behav xil_defaultlib.soc_top_tb xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4100] "E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.naive_bus
Compiling module xil_defaultlib.uart_rx
Compiling module xil_defaultlib.uart_tx_line
Compiling module xil_defaultlib.ram
Compiling module xil_defaultlib.user_uart_tx
Compiling module xil_defaultlib.isp_uart_default
Compiling module xil_defaultlib.core_id_segreg
Compiling module xil_defaultlib.core_id_stage
Compiling module xil_defaultlib.dual_read_port_ram_32x32
Compiling module xil_defaultlib.core_regfile
Compiling module xil_defaultlib.core_alu
Compiling module xil_defaultlib.core_bus_wrapper
Compiling module xil_defaultlib.core_top
Compiling module xil_defaultlib.instr_rom
Compiling module xil_defaultlib.ram_bus_wrapper
Compiling module xil_defaultlib.ram128B
Compiling module xil_defaultlib.char8x16_rom
Compiling module xil_defaultlib.vga_char_86x32_default
Compiling module xil_defaultlib.video_ram
Compiling module xil_defaultlib.naive_bus_router(N_MASTER=8'b011...
Compiling module xil_defaultlib.soc_top_default
Compiling module xil_defaultlib.soc_top_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot soc_top_tb_behav

71
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/glbl.v Normal file
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif

23
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/simulate.bat Normal file
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@ -0,0 +1,23 @@
@echo off
REM ****************************************************************************
REM Vivado (TM) v2017.4 (64-bit)
REM
REM Filename : simulate.bat
REM Simulator : Xilinx Vivado Simulator
REM Description : Script for simulating the design by launching the simulator
REM
REM Generated by Vivado on Wed Mar 20 23:48:37 +0800 2019
REM SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
REM
REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
REM
REM usage: simulate.bat
REM
REM ****************************************************************************
call xsim soc_top_tb_behav -key {Behavioral:sim_1:Functional:soc_top_tb} -tclbatch soc_top_tb.tcl -log simulate.log
if "%errorlevel%"=="0" goto SUCCESS
if "%errorlevel%"=="1" goto END
:END
exit 1
:SUCCESS
exit 0

2
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/simulate.log Normal file
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@ -0,0 +1,2 @@
Vivado Simulator 2017.4
Time resolution is 1 ps

11
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/soc_top_tb.tcl Normal file
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@ -0,0 +1,11 @@
set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns

BIN
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/soc_top_tb_behav.wdb Normal file
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Binary file not shown.

30
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/soc_top_tb_vlog.prj Normal file
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# compile verilog/system verilog design source files
sv xil_defaultlib --include "C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include" \
"../../../../../../../RTL/char8x16_rom.sv" \
"../../../../../../../RTL/core_alu.sv" \
"../../../../../../../RTL/core_bus_wrapper.sv" \
"../../../../../../../RTL/core_id_segreg.sv" \
"../../../../../../../RTL/core_id_stage.sv" \
"../../../../../../../RTL/core_regfile.sv" \
"../../../../../../../RTL/core_top.sv" \
"../../../../../../../RTL/dual_read_port_ram_32x32.sv" \
"../../../../../../../RTL/instr_rom.sv" \
"../../../../../../../RTL/isp_uart.sv" \
"../../../../../../../RTL/naive_bus.sv" \
"../../../../../../../RTL/naive_bus_router.sv" \
"../../../../../../../RTL/ram.sv" \
"../../../../../../../RTL/ram128B.sv" \
"../../../../../../../RTL/ram_bus_wrapper.sv" \
"../../../../../../../RTL/soc_top.sv" \
"../../../../../../../RTL/uart_rx.sv" \
"../../../../../../../RTL/uart_tx_line.sv" \
"../../../../../../../RTL/user_uart_tx.sv" \
"../../../../../../../RTL/vga_char_86x32.sv" \
"../../../../../../../RTL/video_ram.sv" \
"../../../../../../../RTL/soc_top_tb.sv" \
# compile glbl module
verilog xil_defaultlib "glbl.v"
# Do not sort compile order
nosort

12
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk.jou Normal file
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#-----------------------------------------------------------
# Webtalk v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Wed Mar 20 23:49:45 2019
# Process ID: 39800
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk.log
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace

13
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk.log Normal file
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@ -0,0 +1,13 @@
#-----------------------------------------------------------
# Webtalk v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Wed Mar 20 23:49:45 2019
# Process ID: 39800
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk.log
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Wed Mar 20 23:49:46 2019...

12
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk_30224.backup.jou Normal file
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#-----------------------------------------------------------
# Webtalk v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Wed Mar 20 23:48:36 2019
# Process ID: 30224
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk.log
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace

13
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk_30224.backup.log Normal file
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@ -0,0 +1,13 @@
#-----------------------------------------------------------
# Webtalk v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Wed Mar 20 23:48:36 2019
# Process ID: 30224
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/webtalk.log
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Wed Mar 20 23:48:37 2019...

BIN
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1
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/Compile_Options.txt Normal file
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@ -0,0 +1 @@
-wto "ddc8340f1eba4b8bbb076a11b9b82028" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "soc_top_tb_behav" "xil_defaultlib.soc_top_tb" "xil_defaultlib.glbl" -log "elaborate.log"

1
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/TempBreakPointFile.txt Normal file
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@ -0,0 +1 @@
Breakpoint File Version 1.0

BIN
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/obj/xsim_0.win64.obj Normal file
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hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/obj/xsim_1.c Normal file
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hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/obj/xsim_1.win64.obj Normal file
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5
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/.xsim_webtallk.info Normal file
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1553096914
1553096984
3
1
ddc8340f1eba4b8bbb076a11b9b82028

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hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/usage_statistics_ext_xsim.html Normal file
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<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>XSIM Usage Report</H3><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
<TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2086221</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Wed Mar 20 23:49:44 2019</TD>
<TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>XSIM v2017.4 (64-bit)</TD>
<TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>ddc8340f1eba4b8bbb076a11b9b82028</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>2</TD>
<TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>96b72edc-7f7f-45e5-88d1-5286a4317325</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>96b72edc-7f7f-45e5-88d1-5286a4317325</TD>
<TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>FALSE</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>not_applicable</TD>
<TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>not_applicable</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>not_applicable</TD>
<TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>not_applicable</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>xsim_vivado</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i7-8750H CPU @ 2.20GHz</TD>
<TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2208 MHz</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Microsoft Windows 8 or later , 64-bit</TD>
<TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release (build 9200)</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>25.000 GB</TD>
<TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>command=xsim</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'> <TD>iteration=5</TD>
<TD>runtime=91 us</TD>
<TD>simulation_memory=10916_KB</TD>
<TD>simulation_time=2.58_sec</TD>
</TR><TR ALIGN='LEFT'> <TD>trace_waveform=true</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
</BODY>
</HTML>

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hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/webtalk/usage_statistics_ext_xsim.xml Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Wed Mar 20 23:49:45 2019'>
<section name="__ROOT__" level="0" order="1" description="">
<section name="software_version_and_target_device" level="1" order="1" description="">
<keyValuePair key="beta" value="FALSE" description="" />
<keyValuePair key="build_version" value="2086221" description="" />
<keyValuePair key="date_generated" value="Wed Mar 20 23:49:44 2019" description="" />
<keyValuePair key="os_platform" value="WIN64" description="" />
<keyValuePair key="product_version" value="XSIM v2017.4 (64-bit)" description="" />
<keyValuePair key="project_id" value="ddc8340f1eba4b8bbb076a11b9b82028" description="" />
<keyValuePair key="project_iteration" value="2" description="" />
<keyValuePair key="random_id" value="96b72edc-7f7f-45e5-88d1-5286a4317325" description="" />
<keyValuePair key="registration_id" value="96b72edc-7f7f-45e5-88d1-5286a4317325" description="" />
<keyValuePair key="route_design" value="FALSE" description="" />
<keyValuePair key="target_device" value="not_applicable" description="" />
<keyValuePair key="target_family" value="not_applicable" description="" />
<keyValuePair key="target_package" value="not_applicable" description="" />
<keyValuePair key="target_speed" value="not_applicable" description="" />
<keyValuePair key="tool_flow" value="xsim_vivado" description="" />
</section>
<section name="user_environment" level="1" order="2" description="">
<keyValuePair key="cpu_name" value="Intel(R) Core(TM) i7-8750H CPU @ 2.20GHz" description="" />
<keyValuePair key="cpu_speed" value="2208 MHz" description="" />
<keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
<keyValuePair key="os_release" value="major release (build 9200)" description="" />
<keyValuePair key="system_ram" value="25.000 GB" description="" />
<keyValuePair key="total_processors" value="1" description="" />
</section>
<section name="vivado_usage" level="1" order="3" description="">
</section>
<section name="xsim" level="1" order="4" description="">
<section name="command_line_options" level="2" order="1" description="">
<keyValuePair key="command" value="xsim" description="" />
</section>
<section name="usage" level="2" order="2" description="">
<keyValuePair key="iteration" value="5" description="" />
<keyValuePair key="runtime" value="91 us" description="" />
<keyValuePair key="simulation_memory" value="10916_KB" description="" />
<keyValuePair key="simulation_time" value="2.58_sec" description="" />
<keyValuePair key="trace_waveform" value="true" description="" />
</section>
</section>
</section>
</webTalkData>

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hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsim.rlx Normal file
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{
crc : 6182122172325740929 ,
ccp_crc : 0 ,
cmdline : " -wto ddc8340f1eba4b8bbb076a11b9b82028 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot soc_top_tb_behav xil_defaultlib.soc_top_tb xil_defaultlib.glbl" ,
buildDate : "Dec 15 2017" ,
buildTime : "21:07:18" ,
linkCmd : "C:\\Xilinx\\Vivado\\2017.4\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/soc_top_tb_behav/xsimk.exe\" \"xsim.dir/soc_top_tb_behav/obj/xsim_0.win64.obj\" \"xsim.dir/soc_top_tb_behav/obj/xsim_1.win64.obj\" \"C:\\Xilinx\\Vivado\\2017.4\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"C:\\Xilinx\\Vivado\\2017.4\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" ,
aggregate_nets :
[
]
}

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hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsimSettings.ini Normal file
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[General]
ARRAY_DISPLAY_LIMIT=1024
RADIX=hex
TIME_UNIT=ns
TRACE_LIMIT=65536
VHDL_ENTITY_SCOPE_FILTER=true
VHDL_PACKAGE_SCOPE_FILTER=false
VHDL_BLOCK_SCOPE_FILTER=true
VHDL_PROCESS_SCOPE_FILTER=false
VERILOG_MODULE_SCOPE_FILTER=true
VERILOG_PACKAGE_SCOPE_FILTER=false
VERILOG_BLOCK_SCOPE_FILTER=false
VERILOG_TASK_SCOPE_FILTER=false
VERILOG_PROCESS_SCOPE_FILTER=false
INPUT_OBJECT_FILTER=true
OUTPUT_OBJECT_FILTER=true
INOUT_OBJECT_FILTER=true
INTERNAL_OBJECT_FILTER=true
CONSTANT_OBJECT_FILTER=true
VARIABLE_OBJECT_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=0
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=0
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=0
OBJECT_NAME_COLUMN_WIDTH=120
OBJECT_VALUE_COLUMN_WIDTH=241
OBJECT_DATA_TYPE_COLUMN_WIDTH=60

29
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsimcrash.log Normal file
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Exception at PC 0x00007FFEAA6FA388
Exception at PC 0x00007FFEAA6FA388
Exception at PC 0x00007FFEAA6FA388
Exception at PC 0x00007FFEAA6FA388
Exception at PC 0x00007FFE118FE132
Attemped to write at address 0x00007FFE655D4AA4
Printing stacktrace...
[0] [0x00007FFE118FE132]
[1] [0x00007FFE118FE132]
[2] [0x00007FFE118FE194]
[3] [0x00007FFE1154D0D7]
[4] [0x00007FFE11432BCA]
[5] [0x00007FFE11432FD1]
[6] [0x00007FFE118FEB2F]
[7] [0x00007FFE117BC19D]
[8] [0x00007FFE117B5942]
[9] [0x00007FFE117B5AB5]
[10] (RtlActivateActivationContextUnsafeFast+0x123) [0x00007FFEAD68B583]
[11] (LdrShutdownProcess+0x125) [0x00007FFEAD697F85]
[12] (RtlExitUserProcess+0xd8) [0x00007FFEAD697E48]
[13] (FatalExit+0xa) [0x00007FFEAC19C80A]
[14] (exit+0x75) [0x00007FFEACAA9CE5]
[15] (initterm_e+0x235) [0x00007FFEACAAA345]
[16] [0x00000000004014CD]
[17] [0x000000000040151B]
[18] (BaseThreadInitThunk+0x14) [0x00007FFEAC193DC4]
[19] (RtlUserThreadStart+0x21) [0x00007FFEAD6C3691]
Done

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hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/xsim.dir/soc_top_tb_behav/xsimkernel.log Normal file
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Running: xsim.dir/soc_top_tb_behav/xsimk.exe -simmode gui -wdb soc_top_tb_behav.wdb -simrunnum 0 -socket 62220
Design successfully loaded
Design Loading Memory Usage: 7024 KB (Peak: 7024 KB)
Design Loading CPU Usage: 15 ms
Simulation completed
Simulation Memory Usage: 10916 KB (Peak: 10916 KB)
Simulation CPU Usage: 2578 ms

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0.6
2017.4
Dec 15 2017
21:07:18
E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv,1551539060,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv,,char8x16_rom,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv,1552301004,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv,,core_alu,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv,1552153482,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv,,core_bus_wrapper,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv,1552291334,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv,,core_id_segreg,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv,1552301088,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv,,core_id_stage,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv,1551587650,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv,,core_regfile,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv,1552364652,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv,,core_top,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv,1551597268,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv,,dual_read_port_ram_32x32,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv,1552416592,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv,,instr_rom,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv,1553085889,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv,,isp_uart,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv,1549876350,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv,,naive_bus,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv,1549876350,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv,,naive_bus_router,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv,1551597245,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv,,ram,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv,1551597237,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv,,ram128B,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv,1550846066,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv,,ram_bus_wrapper,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv,1552152562,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv,,soc_top,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv,1551980366,systemVerilog,,,,soc_top_tb,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv,1549876350,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv,,uart_rx,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv,1551092170,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv,,uart_tx_line,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv,1551512538,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv,,user_uart_tx,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv,1551536388,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv,,vga_char_86x32,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv,1551536461,systemVerilog,,E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv,,video_ram,,xil_defaultlib,C:/Xilinx/Vivado/2017.4/data/xilinx_vip/include,,,,,
E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/glbl.v,1513215259,verilog,,,,glbl,,xil_defaultlib,,,,,,

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xil_defaultlib=xsim.dir/xil_defaultlib
xilinx_vip=C:/Xilinx/Vivado/2017.4/data/xsim/ip/xilinx_vip

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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module char8x16_rom
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module core_alu
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module core_bus_wrapper
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module core_id_segreg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module core_id_stage
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module core_regfile
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module core_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module dual_read_port_ram_32x32
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module instr_rom
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module isp_uart
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module naive_bus_router
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ram128B
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ram_bus_wrapper
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module soc_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_rx
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_tx_line
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module user_uart_tx
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module vga_char_86x32
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module video_ram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module soc_top_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl

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@ -31,7 +31,7 @@
<Option Name="EnableBDX" Val="FALSE"/> <Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/> <Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/> <Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="0"/> <Option Name="WTXSimLaunchSim" Val="1"/>
<Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/>
@ -228,11 +228,17 @@
</FileSet> </FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1"> <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PPRDIR/../../../RTL/soc_top_tb.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config> <Config>
<Option Name="DesignMode" Val="RTL"/> <Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="Nexys4_USTCRVSoC_top"/> <Option Name="TopModule" Val="soc_top_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/> <Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/> <Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/> <Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/> <Option Name="SrcSet" Val="sources_1"/>

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106
software/asm-code/calculation-test/SimpleSprintf.S
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# 概述：实现一个简单的 sprintf 函数，支持 %c %s %u %d 格式化串
# 以 a0 寄存器为目的地址，a1 寄存器为格式字符串地址，a2为起始指针的内存里有待格式化的参数，所有参数以4字节对齐
# Author: WangXuan
#
# 系统要求：1、具有一个大小至少为0x400 Byte的数据RAM （该程序中，其高地址用作栈，低地址用作被排序的数组）
# 2、测试该代码时，不需要初始化DataRam，只需要将指令流烧入InstrRam。因为有一系列指令去准备被排序的数组。
# 3、请根据实际情况将a0设置为你的DataRam的地址，例如我的SoC DataRam起始地址为0x00010000，则第一条指令就是 lui a0, 0x00010
#
.org 0x0
.global _start
_start:
main: # main函数开始，在DataRam里初始化一段数据
lui a0, 0x00020 # 设置DataRam的起始地址为0x00020000，即显存RAM，也用作
lui a2, 0x00010
addi sp, a2 , 0x400 # 设置栈顶指针 = 0x00010400
auipc a1, 0x00000 # 获取当前的PC值，目的是能够推算出以下的.string的起始地址
jal zero, AfterString1 # 跳转到以下.string 之后，因为string是一个指令RAM中的数据，不能被执行
.string "(a2):%s (a2+4):%c\0" # 在指令RAM中实现一个string，该string作为sprintf的格式串，在之后调用sprintf时被使用，为了与C语言sprintf一致，显式规定以\0结尾
.align 4 # 下一条指令以4字节对齐
AfterString1:
addi a1, a1, 0x08 # 将a1+8,以得到真正的.string的起始地址
auipc a3, 0x00000 # 获取当前的PC值，目的是能够推算出以下的.string的起始地址
jal zero, AfterString2 # 跳转到以下.string 之后，因为string是一个指令RAM中的数据，不能被执行
.string "hello!\0" # 在指令RAM中实现另一个string
.align 4 # 下一条指令以4字节对齐
AfterString2:
addi a3, a3 , 0x08 # 将a3+8,以得到真正的.string的起始地址
sw a3, (a2)
ori a3, zero, 'a'
sw a3, 4(a2)
jal ra, SimpleSprintf
infinity_loop:
jal zero, infinity_loop # 死循环
SimpleSprintf:
# 以 a0 寄存器为目的地址，a1 寄存器为格式字符串地址，a2为起始指针的内存里有待格式化的参数，所有参数以4字节对齐
# 在调用该函数时，需要准备a0，a1两个寄存器，并在栈中从后向前的(cdecl调用顺序) push 参数
or t0, zero, zero # t0 清零
SimpleSprintfLoopStart:
or t1, t0, zero # 备份t0到t1
lbu t0, (a1)
sb t0, (a0)
addi a1, a1, 1
addi a0, a0, 1
bne t0, zero, DontReturn # 如果没遇到遇到\0，就跳过函数返回
jalr zero, ra, 0 # 遇到\0，函数返回
DontReturn:
ori t2, zero, '%'
bne t1, t2, SimpleSprintfLoopStart # 如果t1!='%'，说明还没碰到需要格式化打印的情况，跳到函数开始去循环执行
addi a0, a0, -1 # 目的字符串指针回退一步，回到%之后
ori t2, zero, 'c'
bne t0, t2, NotC
lw t2, (a2) # 从a2地址中获得一个参数
addi a2, a2, 4
sb t2, -1(a0) # 向目标字符串中写入
jal zero, SimpleSprintfLoopStart
NotC:
ori t2, zero, 's'
bne t0, t2, NotS
lw t2, (a2) # 从a2地址中获得一个参数
addi a2, a2, 4
StringCopystart:
lbu t3, (t2)
beq t3, zero, SimpleSprintfLoopStart
addi t2, t2, 1
sb t3, -1(a0)
addi a0, a0, 1
jal zero, StringCopystart
NotS:
ori t2, zero, 'd'
bne t0, t2, NotD
lw t2, (a2) # 从a2地址中获得一个参数
addi a2, a2, 4
jal zero, SimpleSprintfLoopStart
NotD:
ori t2, zero, 'u'
bne t0, t2, NotU
lw t2, (a2) # 从a2地址中获得一个参数
addi a2, a2, 4
jal zero, SimpleSprintfLoopStart
NotU:
ori t2, zero, 'x'
bne t0, t2, SimpleSprintfLoopStart
lw t2, (a2) # 从a2地址中获得一个参数
addi a2, a2, 4
jal zero, SimpleSprintfLoopStart

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