mirror of
https://github.com/WangXuan95/USTC-RVSoC.git
synced 2024-12-24 22:58:56 +08:00
优化regfile资源占用
This commit is contained in:
WangXuan95
parent
337027642b
commit
72108ce6b6
@ -1,6 +1,6 @@
|
||||
# USTCRVSoC
|
||||
|
||||
一个用SystemVerilog编写的，基于RISC-V的SoC
|
||||
一个用SystemVerilog编写的，基于RISC-V的，普林斯顿结构的SoC
|
||||
|
||||
# 特点
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
> * 总线仲裁器(naive_bus_router.sv)可修改，以方便拓展外设、多核、DMA等
|
||||
> * 具有交互式UART调试器(isp_uart.sv)，用户可以使用PC上的串口助手、minicom等软件，实现系统复位、上传程序、查看内存等功能
|
||||
> * 全部使用 SystemVerilog 实现，不调用IP核，方便在 Altera、Xilinx、Lattice 等不同FPGA平台上移植，也方便在各种工具中进行仿真
|
||||
> * RAM 符合一定的Verilog写法，自动综合成 Block RAM
|
||||
> * RAM 和 ROM 符合一定的Verilog写法，自动综合成 Block RAM
|
||||
|
||||
# SoC 结构
|
||||
|
||||
@ -98,7 +98,7 @@ TODO
|
||||
| fibonacci_recursive.S | 递归法计算斐波那契数列第7个数并，用用户UART打印结果 |
|
||||
| load_store.S | 完成一些内存读写，没有具体表现，为了观察现象，可以使用UART调试器查看内存 |
|
||||
|
||||
现在我们尝试让SoC运行一个计算斐波那契数列并UART打印的程序。点击“打开...”按钮，浏览到目录./software/asm-code，打开汇编文件 fibonacci_recursive.S。点击右侧的“汇编”按钮，可以看到右方框里出现了一串16进制数，这就是汇编得到的机器码。然后，选择正确的COM口，点击“烧写”，如果下方状态栏里显示“烧写成功”，则CPU就已经开始运行该机器码了。这时，在右侧的“串口查看”框里选中“16进制显示”，可以看到不断显示出15，这说明CPU正确的计算出斐波那契数列的第七个数是0x15，即十进制的21。
|
||||
现在我们尝试让SoC运行一个计算斐波那契数列并UART打印的程序。点击“打开...”按钮，浏览到目录./software/asm-code，打开汇编文件 fibonacci_recursive.S。点击右侧的“汇编”按钮，可以看到右方框里出现了一串16进制数，这就是汇编得到的机器码。然后，选择正确的COM口，点击“烧写”，如果下方状态栏里显示“烧写成功”，则CPU就已经开始运行该机器码了。这时，在右侧的“串口查看”框里选中“16进制显示”，可以看到不断显示出22，这说明CPU正确的计算出斐波那契数列的第七个数是0x22，即十进制的34。
|
||||
|
||||
|
||||
|
||||
|
||||
Binary file not shown.
@ -1,46 +1,130 @@
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv {1 {vlog -work work -sv {E:\work-Lab\USTCRVSoC\hardware\RTL\soc_top_tb.sv}
|
||||
../RTL/dual_read_port_ram_32x32.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module soc_top_tb
|
||||
-- Compiling module dual_read_port_ram_32x32
|
||||
|
||||
Top level modules:
|
||||
soc_top_tb
|
||||
dual_read_port_ram_32x32
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv
|
||||
} {} {}} ../RTL/vga_char_86x32.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling interface naive_bus
|
||||
-- Compiling module vga_char_86x32
|
||||
|
||||
Top level modules:
|
||||
--none--
|
||||
vga_char_86x32
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv
|
||||
} {} {}} ../RTL/ram128B.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module ram128B
|
||||
|
||||
Top level modules:
|
||||
ram128B
|
||||
|
||||
} {} {}} ../RTL/uart_rx.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module uart_rx
|
||||
|
||||
Top level modules:
|
||||
uart_rx
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv
|
||||
} {} {}} ../RTL/instr_rom.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module instr_rom
|
||||
|
||||
Top level modules:
|
||||
instr_rom
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv
|
||||
} {} {}} ../RTL/video_ram.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module video_ram
|
||||
|
||||
Top level modules:
|
||||
video_ram
|
||||
|
||||
} {} {}} ../RTL/soc_top.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module soc_top
|
||||
|
||||
Top level modules:
|
||||
soc_top
|
||||
|
||||
} {} {}} ../RTL/core_ex_branch_judge.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module core_ex_branch_judge
|
||||
|
||||
Top level modules:
|
||||
core_ex_branch_judge
|
||||
|
||||
} {} {}} ../RTL/ram.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module ram
|
||||
|
||||
Top level modules:
|
||||
ram
|
||||
|
||||
} {} {}} ../RTL/ram_bus_wrapper.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module ram_bus_wrapper
|
||||
|
||||
Top level modules:
|
||||
ram_bus_wrapper
|
||||
|
||||
} {} {}} ../RTL/core_alu.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module core_alu
|
||||
|
||||
Top level modules:
|
||||
core_alu
|
||||
|
||||
} {} {}} ../RTL/core_bus_wrapper.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module core_bus_wrapper
|
||||
|
||||
Top level modules:
|
||||
core_bus_wrapper
|
||||
|
||||
} {} {}} ../RTL/char8x16_rom.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module char8x16_rom
|
||||
|
||||
Top level modules:
|
||||
char8x16_rom
|
||||
|
||||
} {} {}} ../RTL/core_top.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module core_top
|
||||
|
||||
Top level modules:
|
||||
core_top
|
||||
|
||||
} {} {}} ../RTL/soc_top_tb.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module soc_top_tb
|
||||
|
||||
Top level modules:
|
||||
soc_top_tb
|
||||
|
||||
} {} {}} ../RTL/user_uart_tx.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module user_uart_tx
|
||||
|
||||
Top level modules:
|
||||
user_uart_tx
|
||||
|
||||
} {} {}} ../RTL/uart_tx_line.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module uart_tx_line
|
||||
|
||||
Top level modules:
|
||||
uart_tx_line
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv
|
||||
} {} {}} ../RTL/core_regfile.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module core_regfile
|
||||
|
||||
Top level modules:
|
||||
core_regfile
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv {2 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv
|
||||
} {} {}} ../RTL/isp_uart.sv {2 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module isp_uart
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv(92): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
@ -51,21 +135,21 @@ Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
Top level modules:
|
||||
isp_uart
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv
|
||||
} {} {}} ../RTL/core_id_stage.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module ram
|
||||
-- Compiling module core_id_stage
|
||||
|
||||
Top level modules:
|
||||
ram
|
||||
core_id_stage
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv
|
||||
} {} {}} ../RTL/naive_bus.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module ram_bus_wrapper
|
||||
-- Compiling interface naive_bus
|
||||
|
||||
Top level modules:
|
||||
ram_bus_wrapper
|
||||
--none--
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv {2 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv
|
||||
} {} {}} ../RTL/naive_bus_router.sv {2 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module naive_bus_router
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(64): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
@ -128,39 +212,4 @@ Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
Top level modules:
|
||||
naive_bus_router
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module core_ex_branch_judge
|
||||
|
||||
Top level modules:
|
||||
core_ex_branch_judge
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module core_id_stage
|
||||
|
||||
Top level modules:
|
||||
core_id_stage
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module core_alu
|
||||
|
||||
Top level modules:
|
||||
core_alu
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module core_bus_wrapper
|
||||
|
||||
Top level modules:
|
||||
core_bus_wrapper
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module core_top
|
||||
|
||||
Top level modules:
|
||||
core_top
|
||||
|
||||
} {} {}}
|
||||
|
||||
@ -447,43 +447,51 @@ ConcurrentFileLimit = 40
|
||||
Project_Version = 6
|
||||
Project_DefaultLib = work
|
||||
Project_SortMethod = unused
|
||||
Project_Files_Count = 18
|
||||
Project_File_0 = E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv
|
||||
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1551505557 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_1 = E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv
|
||||
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_2 = E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv
|
||||
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1551167092 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_3 = E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv
|
||||
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_4 = E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv
|
||||
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551094921 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_5 = E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv
|
||||
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1551166630 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_6 = E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv
|
||||
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551092170 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_7 = E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv
|
||||
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_8 = E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv
|
||||
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551505505 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_9 = E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv
|
||||
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551102643 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_10 = E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv
|
||||
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551090389 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_11 = E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv
|
||||
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1550846066 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_12 = E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv
|
||||
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_13 = E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
|
||||
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_14 = E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv
|
||||
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_15 = E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv
|
||||
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_16 = E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv
|
||||
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_17 = E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv
|
||||
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551169276 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_Files_Count = 22
|
||||
Project_File_0 = ../RTL/dual_read_port_ram_32x32.sv
|
||||
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551597268 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_1 = ../RTL/vga_char_86x32.sv
|
||||
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1551536388 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_2 = ../RTL/ram128B.sv
|
||||
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551597237 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_3 = ../RTL/uart_rx.sv
|
||||
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_4 = ../RTL/instr_rom.sv
|
||||
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551094921 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_5 = ../RTL/video_ram.sv
|
||||
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551536461 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_6 = ../RTL/soc_top.sv
|
||||
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1551587626 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_7 = ../RTL/core_ex_branch_judge.sv
|
||||
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_8 = ../RTL/ram.sv
|
||||
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551597245 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_9 = ../RTL/ram_bus_wrapper.sv
|
||||
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1550846066 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_10 = ../RTL/core_bus_wrapper.sv
|
||||
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551591033 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_11 = ../RTL/core_alu.sv
|
||||
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551588536 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_12 = ../RTL/char8x16_rom.sv
|
||||
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1551539060 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_13 = ../RTL/core_top.sv
|
||||
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1551597558 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_14 = ../RTL/soc_top_tb.sv
|
||||
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551596984 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_15 = ../RTL/user_uart_tx.sv
|
||||
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551512538 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_16 = ../RTL/core_regfile.sv
|
||||
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551587650 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_17 = ../RTL/uart_tx_line.sv
|
||||
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551092170 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_18 = ../RTL/isp_uart.sv
|
||||
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551102643 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_19 = ../RTL/core_id_stage.sv
|
||||
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551588579 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_20 = ../RTL/naive_bus_router.sv
|
||||
Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_21 = ../RTL/naive_bus.sv
|
||||
Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_Sim_Count = 0
|
||||
Project_Folder_Count = 0
|
||||
Echo_Compile_Output = 0
|
||||
|
||||
Binary file not shown.
@ -5,66 +5,66 @@ cModel Technology
|
||||
Z0 dC:\altera\13.1
|
||||
vchar8x16_rom
|
||||
Z1 DXx6 sv_std 3 std 0 22 F[19LRNL:5;XmIFh[XOPn1
|
||||
!i10b 1
|
||||
Z2 !s100 ;IlD4IOMGEYo80>^h^UhK3
|
||||
Z3 I<>FR1OkHc6KV4iK0a<Q?<0
|
||||
Z4 VN2h6;hjMc8b_1gne=2;Q10
|
||||
Z5 !s105 video_ram_sv_unit
|
||||
Z2 !s100 o2f[Z63nVmj1LkXUR2gYV2
|
||||
Z3 IfWD6eSM90m?f<@dU`0I=z1
|
||||
Z4 Va@LVMQ5NRI<^Z9ol70R>72
|
||||
Z5 !s105 char8x16_rom_sv_unit
|
||||
S1
|
||||
Z6 dE:\work-Lab\USTCRVSoC\hardware\ModelSim
|
||||
Z7 w1551166630
|
||||
Z8 8E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv
|
||||
Z9 FE:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv
|
||||
Z10 L0 202
|
||||
Z11 OV;L;10.1d;51
|
||||
Z7 w1551539060
|
||||
Z8 8E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv
|
||||
Z9 FE:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv
|
||||
L0 11
|
||||
Z10 OV;L;10.1d;51
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
Z12 !s108 1551505561.076000
|
||||
Z13 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv|
|
||||
Z14 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv|
|
||||
Z11 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv|
|
||||
Z12 o-work work -sv -O0
|
||||
Z13 !s108 1551598731.645000
|
||||
Z14 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
Z15 o-work work -sv -O0
|
||||
vcore_alu
|
||||
R1
|
||||
Z16 !s100 iCH1]MMmI?;=TKD:>Fe_b2
|
||||
Z17 I?HDS_jndEJ3e84j7B6zi00
|
||||
Z18 VCm9FCj0lB9T7DXWo]1;1f0
|
||||
Z19 !s105 core_alu_sv_unit
|
||||
Z15 !s100 nnc0OZj_1_9^F5XkQaj>j0
|
||||
Z16 I_aRibf4^97SVfB1@^O<JH2
|
||||
Z17 VMiFG0DJ81d;Sd^00RnlPQ2
|
||||
Z18 !s105 core_alu_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z20 w1549876350
|
||||
Z21 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv
|
||||
Z22 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv
|
||||
Z19 w1551588536
|
||||
Z20 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv
|
||||
Z21 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv
|
||||
L0 1
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z23 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv|
|
||||
R15
|
||||
Z24 !s108 1551505559.882000
|
||||
Z25 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv|
|
||||
Z22 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv|
|
||||
R12
|
||||
Z23 !s108 1551598730.368000
|
||||
Z24 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vcore_bus_wrapper
|
||||
R1
|
||||
Z26 !s100 M_`JZE_P3V6d4RWWRY8751
|
||||
Z27 I4k_4?GVX@^QA>lfAA:7Ce3
|
||||
Z28 VmlnoE:bmH;9e3[Jfd^_M=3
|
||||
Z29 !s105 core_bus_wrapper_sv_unit
|
||||
Z25 !s100 QYF_K6H6kLmIn?YK<7`@>3
|
||||
Z26 IUkTB:Q:AMYWJA7fKHo?_O1
|
||||
Z27 VNDHkMe8HeKhI9BUm]55SP0
|
||||
Z28 !s105 core_bus_wrapper_sv_unit
|
||||
S1
|
||||
R6
|
||||
R20
|
||||
Z29 w1551591033
|
||||
Z30 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv
|
||||
Z31 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv
|
||||
L0 1
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z32 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv|
|
||||
R15
|
||||
Z33 !s108 1551505559.961000
|
||||
R12
|
||||
Z33 !s108 1551598730.443000
|
||||
Z34 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
@ -77,392 +77,459 @@ Z37 V@jT?>bnOD2?j_T4=3fkh_3
|
||||
Z38 !s105 core_ex_branch_judge_sv_unit
|
||||
S1
|
||||
R6
|
||||
R20
|
||||
Z39 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
|
||||
Z40 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
|
||||
Z39 w1549876350
|
||||
Z40 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
|
||||
Z41 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
|
||||
L0 1
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z41 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv|
|
||||
R15
|
||||
Z42 !s108 1551505560.045000
|
||||
Z43 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv|
|
||||
Z42 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv|
|
||||
R12
|
||||
Z43 !s108 1551598730.518000
|
||||
Z44 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vcore_id_stage
|
||||
R1
|
||||
Z44 !s100 kRDMIRciCbeOb5=R?37071
|
||||
Z45 Io4GObCTY4;CTKQ<HjO:=V3
|
||||
Z46 Vfo`K`XV=DajZ8Eb]j?gV:3
|
||||
Z47 !s105 core_id_stage_sv_unit
|
||||
Z45 !s100 @Z4XI5;0Bfzel18A7k<PT0
|
||||
Z46 IMTUT@llRSg7kOM`PLzHjX2
|
||||
Z47 Vfo`K`XV=DajZ8Eb]j?gV:3
|
||||
Z48 !s105 core_id_stage_sv_unit
|
||||
S1
|
||||
R6
|
||||
R20
|
||||
Z48 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv
|
||||
Z49 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv
|
||||
Z49 w1551588579
|
||||
Z50 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv
|
||||
Z51 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv
|
||||
L0 1
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z50 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv|
|
||||
R15
|
||||
Z51 !s108 1551505560.109000
|
||||
Z52 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv|
|
||||
Z52 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv|
|
||||
R12
|
||||
Z53 !s108 1551598730.584000
|
||||
Z54 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vcore_regfile
|
||||
R1
|
||||
Z53 !s100 Dna_T_?^^W?K0@1mdN7?P2
|
||||
Z54 ID]n5X]WVRSDO5WE>0hl0]3
|
||||
Z55 VaXLkm<HFE<T[8I`oKbaaA1
|
||||
Z56 !s105 core_regfile_sv_unit
|
||||
Z55 !s100 I^YE54Zo0N7Mh6`QiI<Oz3
|
||||
Z56 IoCmXUMJPHAOdI=TTQ4@AZ1
|
||||
Z57 VYWbXWbbKF]m<1R3jXPAMb3
|
||||
Z58 !s105 core_regfile_sv_unit
|
||||
S1
|
||||
R6
|
||||
R20
|
||||
Z57 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv
|
||||
Z58 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv
|
||||
Z59 w1551587650
|
||||
Z60 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv
|
||||
Z61 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv
|
||||
L0 2
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z59 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv|
|
||||
R15
|
||||
Z60 !s108 1551505560.178000
|
||||
Z61 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv|
|
||||
Z62 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv|
|
||||
R12
|
||||
Z63 !s108 1551598730.656000
|
||||
Z64 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vcore_top
|
||||
R1
|
||||
Z62 !s100 O2VJO7S?RbR=^Rj:fN=0`2
|
||||
Z63 I8?0idhHn?IYLgTaS3djD>3
|
||||
Z64 Vi7?O@h6m5O3BFF`kIdBUC2
|
||||
Z65 !s105 core_top_sv_unit
|
||||
Z65 !s100 HMLmk@@aBh3oW3M2oh>5F0
|
||||
Z66 IYX6W^T9h03:[15`LXl06K2
|
||||
Z67 Vi7?O@h6m5O3BFF`kIdBUC2
|
||||
Z68 !s105 core_top_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z66 w1551169276
|
||||
Z67 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv
|
||||
Z68 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv
|
||||
Z69 w1551597558
|
||||
Z70 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv
|
||||
Z71 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv
|
||||
L0 1
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z69 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv|
|
||||
R15
|
||||
Z70 !s108 1551505560.245000
|
||||
Z71 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv|
|
||||
Z72 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv|
|
||||
R12
|
||||
Z73 !s108 1551598730.728000
|
||||
Z74 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vinstr_rom
|
||||
vdual_read_port_ram_32x32
|
||||
R1
|
||||
Z72 !s100 Bd]Z1a^3]kD30E<26M`Lm1
|
||||
Z73 IOc1Uo_kS08]?1_CKOHHU?0
|
||||
Z74 Vg27TzclZ3S3@lBLMlA`?L1
|
||||
Z75 !s105 instr_rom_sv_unit
|
||||
!i10b 1
|
||||
Z75 !s100 fdb;joBRd?Kbjj708`H@K2
|
||||
Z76 IPRWQ3P[Jk_E9z0fS4::gE0
|
||||
Z77 Vl@[MQJH:k3R5DJ2AcgRCH1
|
||||
Z78 !s105 dual_read_port_ram_32x32_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z76 w1551094921
|
||||
Z77 8E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv
|
||||
Z78 FE:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv
|
||||
Z79 w1551597268
|
||||
Z80 8E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv
|
||||
Z81 FE:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv
|
||||
L0 1
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
!s108 1551598731.874000
|
||||
!s107 E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv|
|
||||
Z82 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv|
|
||||
!s101 -O0
|
||||
R12
|
||||
vinstr_rom
|
||||
R1
|
||||
Z83 !s100 Bd]Z1a^3]kD30E<26M`Lm1
|
||||
Z84 IOc1Uo_kS08]?1_CKOHHU?0
|
||||
Z85 Vg27TzclZ3S3@lBLMlA`?L1
|
||||
Z86 !s105 instr_rom_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z87 w1551094921
|
||||
Z88 8E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv
|
||||
Z89 FE:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z79 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv|
|
||||
R15
|
||||
Z80 !s108 1551505560.314000
|
||||
Z81 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv|
|
||||
Z90 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv|
|
||||
R12
|
||||
Z91 !s108 1551598730.803000
|
||||
Z92 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
visp_uart
|
||||
R1
|
||||
Z82 !s100 @dmH];GG>K;lS7PljQ:Am1
|
||||
Z83 I_4gBZG2Ib<khkdHbSDz?I0
|
||||
Z84 V@@jZ3Y6;d=WD@H08`7cWF3
|
||||
Z85 !s105 isp_uart_sv_unit
|
||||
Z93 !s100 @dmH];GG>K;lS7PljQ:Am1
|
||||
Z94 I_4gBZG2Ib<khkdHbSDz?I0
|
||||
Z95 V@@jZ3Y6;d=WD@H08`7cWF3
|
||||
Z96 !s105 isp_uart_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z86 w1551102643
|
||||
Z87 8E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv
|
||||
Z88 FE:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv
|
||||
Z97 w1551102643
|
||||
Z98 8E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv
|
||||
Z99 FE:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv
|
||||
L0 3
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z89 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv|
|
||||
R15
|
||||
Z90 !s108 1551505560.388000
|
||||
Z91 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv|
|
||||
Z100 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv|
|
||||
R12
|
||||
Z101 !s108 1551598730.873000
|
||||
Z102 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
Ynaive_bus
|
||||
R1
|
||||
Z92 !s100 gFz59kzW]I]nGiaVoSo3O2
|
||||
Z93 Idj:03TOO?jDHzf[0c?lJ`2
|
||||
Z94 VKXR@0<URHIKN=UGzERidm1
|
||||
Z95 !s105 naive_bus_sv_unit
|
||||
Z103 !s100 gFz59kzW]I]nGiaVoSo3O2
|
||||
Z104 Idj:03TOO?jDHzf[0c?lJ`2
|
||||
Z105 VKXR@0<URHIKN=UGzERidm1
|
||||
Z106 !s105 naive_bus_sv_unit
|
||||
S1
|
||||
R6
|
||||
R20
|
||||
Z96 8E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv
|
||||
Z97 FE:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv
|
||||
R39
|
||||
Z107 8E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv
|
||||
Z108 FE:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv
|
||||
L0 4
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z98 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv|
|
||||
R15
|
||||
Z99 !s108 1551505560.458000
|
||||
Z100 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv|
|
||||
Z109 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv|
|
||||
R12
|
||||
Z110 !s108 1551598730.944000
|
||||
Z111 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vnaive_bus_router
|
||||
R1
|
||||
Z101 !s100 nSRUejF=Q5]HdBmmdfzLA1
|
||||
Z102 I^NC0W49]?el6;z^6BojXI2
|
||||
Z103 VS<O=OM<>7@f0]AeUc<_5c0
|
||||
Z104 !s105 naive_bus_router_sv_unit
|
||||
Z112 !s100 nSRUejF=Q5]HdBmmdfzLA1
|
||||
Z113 I^NC0W49]?el6;z^6BojXI2
|
||||
Z114 VS<O=OM<>7@f0]AeUc<_5c0
|
||||
Z115 !s105 naive_bus_router_sv_unit
|
||||
S1
|
||||
R6
|
||||
R20
|
||||
Z105 8E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv
|
||||
Z106 FE:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv
|
||||
R39
|
||||
Z116 8E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv
|
||||
Z117 FE:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv
|
||||
L0 1
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z107 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv|
|
||||
R15
|
||||
Z108 !s108 1551505560.524000
|
||||
Z109 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv|
|
||||
Z118 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv|
|
||||
R12
|
||||
Z119 !s108 1551598731.012000
|
||||
Z120 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vram
|
||||
R1
|
||||
Z110 !s100 TMn[TG8XXmK^UL@k7`ikC0
|
||||
Z111 INIlD0C@nO9Rk96M@_1B?92
|
||||
Z112 VjLloJg4mGdQ3i@ojJbWma2
|
||||
Z113 !s105 ram_sv_unit
|
||||
Z121 !s100 TMn[TG8XXmK^UL@k7`ikC0
|
||||
Z122 INIlD0C@nO9Rk96M@_1B?92
|
||||
Z123 VjLloJg4mGdQ3i@ojJbWma2
|
||||
Z124 !s105 ram_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z114 w1551090389
|
||||
Z115 8E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv
|
||||
Z116 FE:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv
|
||||
Z125 w1551597245
|
||||
Z126 8E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv
|
||||
Z127 FE:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv
|
||||
L0 1
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z117 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv|
|
||||
R15
|
||||
Z118 !s108 1551505560.595000
|
||||
Z119 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv|
|
||||
Z128 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv|
|
||||
R12
|
||||
Z129 !s108 1551598731.088000
|
||||
Z130 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vram128B
|
||||
R1
|
||||
Z131 !s100 fJC_h9DFSL4_5I>=K<7NW1
|
||||
Z132 Il^2=EAV5B4zF?@PSE:S;I3
|
||||
Z133 V5VITH=L0J_KXn908[zCL23
|
||||
Z134 !s105 ram128B_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z135 w1551597237
|
||||
Z136 8E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv
|
||||
Z137 FE:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z138 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv|
|
||||
R12
|
||||
Z139 nram128@b
|
||||
Z140 !s108 1551598731.726000
|
||||
Z141 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vram_bus_wrapper
|
||||
R1
|
||||
Z120 !s100 U?Io3WFYaekAS0T@dW=V43
|
||||
Z121 I?^eTo:Go<IUo<UVJm@aFd0
|
||||
Z122 V^7VeTGko3:7B>^H5Y:FP:1
|
||||
Z123 !s105 ram_bus_wrapper_sv_unit
|
||||
Z142 !s100 U?Io3WFYaekAS0T@dW=V43
|
||||
Z143 I?^eTo:Go<IUo<UVJm@aFd0
|
||||
Z144 V^7VeTGko3:7B>^H5Y:FP:1
|
||||
Z145 !s105 ram_bus_wrapper_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z124 w1550846066
|
||||
Z125 8E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv
|
||||
Z126 FE:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv
|
||||
Z146 w1550846066
|
||||
Z147 8E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv
|
||||
Z148 FE:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv
|
||||
L0 1
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z127 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv|
|
||||
R15
|
||||
Z128 !s108 1551505560.660000
|
||||
Z129 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv|
|
||||
Z149 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv|
|
||||
R12
|
||||
Z150 !s108 1551598731.153000
|
||||
Z151 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vsoc_top
|
||||
R1
|
||||
Z130 IX85mf[[9oQ]V7eK[]II;01
|
||||
Z131 VQ=e`6`fzTCbZ78O>KAKe>2
|
||||
Z132 !s105 soc_top_sv_unit
|
||||
Z152 !s100 c7@DJ3i4aKznCaD6`OcAf2
|
||||
Z153 IY3<DJCiMG<UdHWc8M42J[2
|
||||
Z154 VNE4E5g0B?BmQN]T>5NoOT3
|
||||
Z155 !s105 soc_top_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z133 w1551505505
|
||||
Z134 8E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv
|
||||
Z135 FE:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv
|
||||
Z156 w1551587626
|
||||
Z157 8E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv
|
||||
Z158 FE:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv
|
||||
L0 1
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z136 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv|
|
||||
R15
|
||||
Z137 !s100 LMhfd9`0AH32SARk[<Z470
|
||||
Z138 !s108 1551505560.725000
|
||||
Z139 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv|
|
||||
Z159 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv|
|
||||
R12
|
||||
Z160 !s108 1551598731.221000
|
||||
Z161 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vsoc_top_tb
|
||||
R1
|
||||
Z140 I3jM5<::]YSG=2?]>]:L;L3
|
||||
Z141 VkLTgIQbfzI]@>Jm[T?T@F0
|
||||
Z142 !s105 soc_top_tb_sv_unit
|
||||
Z162 !s100 G9Pel<l=O4Oz@X88_5eEM3
|
||||
Z163 IhjEOPR=KWz2o1@C<oA1jN0
|
||||
Z164 VkLTgIQbfzI]@>Jm[T?T@F0
|
||||
Z165 !s105 soc_top_tb_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z143 w1551505557
|
||||
Z144 8E:\work-Lab\USTCRVSoC\hardware\RTL\soc_top_tb.sv
|
||||
Z145 FE:\work-Lab\USTCRVSoC\hardware\RTL\soc_top_tb.sv
|
||||
Z166 w1551596984
|
||||
Z167 8E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv
|
||||
Z168 FE:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv
|
||||
L0 1
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
31
|
||||
R15
|
||||
Z146 !s100 [cOSC1Uh3BK?X?_L=Pb:d1
|
||||
Z147 !s108 1551505560.791000
|
||||
Z148 !s107 E:\work-Lab\USTCRVSoC\hardware\RTL\soc_top_tb.sv|
|
||||
Z149 !s90 -reportprogress|300|-work|work|-sv|E:\work-Lab\USTCRVSoC\hardware\RTL\soc_top_tb.sv|
|
||||
Z169 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv|
|
||||
R12
|
||||
Z170 !s108 1551598731.290000
|
||||
Z171 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vuart_rx
|
||||
R1
|
||||
Z150 !s100 :`YDkKm;LaUQOjOXmaKB:0
|
||||
Z151 IL9Ji^>V6GeZ<;c7I`o3LQ1
|
||||
Z152 Vh0;PUSD9VYIXe2P@6jV9;0
|
||||
Z153 !s105 uart_rx_sv_unit
|
||||
Z172 !s100 :`YDkKm;LaUQOjOXmaKB:0
|
||||
Z173 IL9Ji^>V6GeZ<;c7I`o3LQ1
|
||||
Z174 Vh0;PUSD9VYIXe2P@6jV9;0
|
||||
Z175 !s105 uart_rx_sv_unit
|
||||
S1
|
||||
R6
|
||||
R20
|
||||
Z154 8E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv
|
||||
Z155 FE:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv
|
||||
R39
|
||||
Z176 8E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv
|
||||
Z177 FE:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv
|
||||
L0 1
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z156 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv|
|
||||
R15
|
||||
Z157 !s108 1551505560.871000
|
||||
Z158 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv|
|
||||
Z178 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv|
|
||||
R12
|
||||
Z179 !s108 1551598731.362000
|
||||
Z180 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vuart_tx_line
|
||||
R1
|
||||
Z159 !s100 WEQ@68?0=RGj1iFdbOOcP2
|
||||
Z160 IK1;[1cPPe^6]7LKQ15Lf21
|
||||
Z161 VW`_FG<Oo:1]3K5g>fF=@_3
|
||||
Z162 !s105 uart_tx_line_sv_unit
|
||||
Z181 !s100 WEQ@68?0=RGj1iFdbOOcP2
|
||||
Z182 IK1;[1cPPe^6]7LKQ15Lf21
|
||||
Z183 VW`_FG<Oo:1]3K5g>fF=@_3
|
||||
Z184 !s105 uart_tx_line_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z163 w1551092170
|
||||
Z164 8E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv
|
||||
Z165 FE:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv
|
||||
Z185 w1551092170
|
||||
Z186 8E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv
|
||||
Z187 FE:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv
|
||||
L0 2
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z166 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv|
|
||||
R15
|
||||
Z167 !s108 1551505560.944000
|
||||
Z168 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv|
|
||||
Z188 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv|
|
||||
R12
|
||||
Z189 !s108 1551598731.432000
|
||||
Z190 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vuser_uart_tx
|
||||
R1
|
||||
Z169 !s100 YA]KWMS3fOD:CQT@0Y9C83
|
||||
Z170 I0JOL7FjkENP;iNc25_jl92
|
||||
Z171 V<1FQ0oW1UA`j`9IX[bcdE1
|
||||
Z172 !s105 user_uart_tx_sv_unit
|
||||
Z191 !s100 YA]KWMS3fOD:CQT@0Y9C83
|
||||
Z192 I0JOL7FjkENP;iNc25_jl92
|
||||
Z193 V<1FQ0oW1UA`j`9IX[bcdE1
|
||||
Z194 !s105 user_uart_tx_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z173 w1551167092
|
||||
Z174 8E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv
|
||||
Z175 FE:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv
|
||||
Z195 w1551512538
|
||||
Z196 8E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv
|
||||
Z197 FE:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv
|
||||
L0 2
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z176 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv|
|
||||
R15
|
||||
Z198 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv|
|
||||
R12
|
||||
Z199 !s108 1551598731.505000
|
||||
Z200 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
Z177 !s108 1551505561.010000
|
||||
Z178 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv|
|
||||
!s101 -O0
|
||||
vvga
|
||||
R1
|
||||
!i10b 1
|
||||
Z179 !s100 9f0>Y=7iSmCK^QMkzVhdz2
|
||||
Z180 IK]n:1gV]8z:A^2D<Og@_H3
|
||||
Z181 VR^SlDkaag;z6W]0_6nChW1
|
||||
R5
|
||||
Z201 !s100 9f0>Y=7iSmCK^QMkzVhdz2
|
||||
Z202 IK]n:1gV]8z:A^2D<Og@_H3
|
||||
Z203 VR^SlDkaag;z6W]0_6nChW1
|
||||
Z204 !s105 video_ram_sv_unit
|
||||
S1
|
||||
R6
|
||||
R7
|
||||
R8
|
||||
R9
|
||||
Z182 L0 147
|
||||
R11
|
||||
Z205 w1551166630
|
||||
Z206 8E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv
|
||||
Z207 FE:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv
|
||||
Z208 L0 147
|
||||
R10
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
Z209 !s108 1551505561.076000
|
||||
Z210 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv|
|
||||
Z211 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv|
|
||||
R12
|
||||
R13
|
||||
R14
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vvga_char_86x32
|
||||
R1
|
||||
Z212 !s100 c>9AM[`i8>D>79]^5c=iL3
|
||||
Z213 IXCM=P_6km0Hk^IPzU0S0N1
|
||||
Z214 VE<z=Jzg_7oWJ0YmQX2]MU3
|
||||
Z215 !s105 vga_char_86x32_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z216 w1551536388
|
||||
Z217 8E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv
|
||||
Z218 FE:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z219 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv|
|
||||
R12
|
||||
!i10b 1
|
||||
!s85 0
|
||||
Z220 !s108 1551598731.797000
|
||||
Z221 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv|
|
||||
!s101 -O0
|
||||
R15
|
||||
vvgaChar98x36
|
||||
R1
|
||||
!i10b 1
|
||||
Z183 !s100 3ih;Pko8X4XgOhl5e4_Gh0
|
||||
Z184 IaM^Q2hPSE=jENCH[nQnb^0
|
||||
Z185 VkYR^g;?9@>9aFYMNc5Beh0
|
||||
R5
|
||||
Z222 !s100 3ih;Pko8X4XgOhl5e4_Gh0
|
||||
Z223 IaM^Q2hPSE=jENCH[nQnb^0
|
||||
Z224 VkYR^g;?9@>9aFYMNc5Beh0
|
||||
R204
|
||||
S1
|
||||
R6
|
||||
R7
|
||||
R8
|
||||
R9
|
||||
R205
|
||||
R206
|
||||
R207
|
||||
L0 82
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R209
|
||||
R210
|
||||
R211
|
||||
R12
|
||||
R13
|
||||
R14
|
||||
Z225 nvga@char98x36
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
R15
|
||||
Z186 nvga@char98x36
|
||||
vvideo_ram
|
||||
R1
|
||||
!i10b 1
|
||||
Z187 !s100 `YSFQF4S?^]MHPKnUlGj:2
|
||||
Z188 IPVzCYEAl]UFiSXzJTNDQT3
|
||||
Z189 Vl^[jWF`OTazg>MX7@1zUi2
|
||||
R5
|
||||
Z226 !s100 5Km:lJ5=^^Z=H?Vg4dnQM0
|
||||
Z227 I8o<maB2Sg[@UYiL96IX_I3
|
||||
Z228 V5JnUKWk;WPc^ACUnLK1_E3
|
||||
R204
|
||||
S1
|
||||
R6
|
||||
R7
|
||||
R8
|
||||
R9
|
||||
Z229 w1551536461
|
||||
R206
|
||||
R207
|
||||
L0 1
|
||||
R11
|
||||
R10
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R211
|
||||
R12
|
||||
R13
|
||||
R14
|
||||
Z230 !s108 1551598731.574000
|
||||
R210
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
R15
|
||||
|
||||
BIN
hardware/ModelSim/work/_temp/vlog05b651
Normal file
BIN
hardware/ModelSim/work/_temp/vlog05b651
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/_temp/vlog0ejb58
Normal file
BIN
hardware/ModelSim/work/_temp/vlog0ejb58
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/_temp/vloghe6dgq
Normal file
BIN
hardware/ModelSim/work/_temp/vloghe6dgq
Normal file
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -3,10 +3,7 @@ use verilog.vl_types.all;
|
||||
entity char8x16_rom is
|
||||
port(
|
||||
clk : in vl_logic;
|
||||
rst_n : in vl_logic;
|
||||
ascii : in vl_logic_vector(7 downto 0);
|
||||
x : in vl_logic_vector(2 downto 0);
|
||||
y : in vl_logic_vector(3 downto 0);
|
||||
b : out vl_logic
|
||||
addr : in vl_logic_vector(11 downto 0);
|
||||
data : out vl_logic_vector(7 downto 0)
|
||||
);
|
||||
end char8x16_rom;
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -8,6 +8,7 @@ entity core_alu is
|
||||
i_num1u : in vl_logic_vector(31 downto 0);
|
||||
i_num2u : in vl_logic_vector(31 downto 0);
|
||||
i_immu : in vl_logic_vector(31 downto 0);
|
||||
i_pc_immu : in vl_logic_vector(31 downto 0);
|
||||
o_res : out vl_logic_vector(31 downto 0)
|
||||
);
|
||||
end core_alu;
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -4,6 +4,7 @@ entity core_bus_wrapper is
|
||||
port(
|
||||
clk : in vl_logic;
|
||||
rst_n : in vl_logic;
|
||||
i_en_n : in vl_logic;
|
||||
i_re : in vl_logic;
|
||||
i_we : in vl_logic;
|
||||
o_conflict : out vl_logic;
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -11,14 +11,14 @@ entity core_regfile is
|
||||
i_re2 : in vl_logic;
|
||||
i_raddr2 : in vl_logic_vector(4 downto 0);
|
||||
o_rdata2 : out vl_logic_vector(31 downto 0);
|
||||
i_we1 : in vl_logic;
|
||||
i_waddr1 : in vl_logic_vector(4 downto 0);
|
||||
i_wdata1 : in vl_logic_vector(31 downto 0);
|
||||
i_we2 : in vl_logic;
|
||||
i_waddr2 : in vl_logic_vector(4 downto 0);
|
||||
i_wdata2 : in vl_logic_vector(31 downto 0);
|
||||
i_we3 : in vl_logic;
|
||||
i_waddr3 : in vl_logic_vector(4 downto 0);
|
||||
i_wdata3 : in vl_logic_vector(31 downto 0)
|
||||
i_forward1 : in vl_logic;
|
||||
i_faddr1 : in vl_logic_vector(4 downto 0);
|
||||
i_fdata1 : in vl_logic_vector(31 downto 0);
|
||||
i_forward2 : in vl_logic;
|
||||
i_faddr2 : in vl_logic_vector(4 downto 0);
|
||||
i_fdata2 : in vl_logic_vector(31 downto 0);
|
||||
i_we : in vl_logic;
|
||||
i_waddr : in vl_logic_vector(4 downto 0);
|
||||
i_wdata : in vl_logic_vector(31 downto 0)
|
||||
);
|
||||
end core_regfile;
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -3,7 +3,8 @@ use verilog.vl_types.all;
|
||||
entity soc_top is
|
||||
generic(
|
||||
UART_RX_CLK_DIV : integer := 108;
|
||||
UART_TX_CLK_DIV : integer := 434
|
||||
UART_TX_CLK_DIV : integer := 434;
|
||||
VGA_CLK_DIV : integer := 1
|
||||
);
|
||||
port(
|
||||
clk : in vl_logic;
|
||||
@ -11,9 +12,12 @@ entity soc_top is
|
||||
isp_uart_tx : out vl_logic;
|
||||
vga_hsync : out vl_logic;
|
||||
vga_vsync : out vl_logic;
|
||||
vga_pixel : out vl_logic_vector(15 downto 0)
|
||||
vga_red : out vl_logic;
|
||||
vga_green : out vl_logic;
|
||||
vga_blue : out vl_logic
|
||||
);
|
||||
attribute mti_svvh_generic_type : integer;
|
||||
attribute mti_svvh_generic_type of UART_RX_CLK_DIV : constant is 1;
|
||||
attribute mti_svvh_generic_type of UART_TX_CLK_DIV : constant is 1;
|
||||
attribute mti_svvh_generic_type of VGA_CLK_DIV : constant is 1;
|
||||
end soc_top;
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1,11 +1,18 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity video_ram is
|
||||
generic(
|
||||
VGA_CLK_DIV : integer := 1
|
||||
);
|
||||
port(
|
||||
clk : in vl_logic;
|
||||
rst_n : in vl_logic;
|
||||
o_hsync : out vl_logic;
|
||||
o_vsync : out vl_logic;
|
||||
o_pixel : out vl_logic_vector(15 downto 0)
|
||||
o_red : out vl_logic;
|
||||
o_green : out vl_logic;
|
||||
o_blue : out vl_logic
|
||||
);
|
||||
attribute mti_svvh_generic_type : integer;
|
||||
attribute mti_svvh_generic_type of VGA_CLK_DIV : constant is 1;
|
||||
end video_ram;
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@ -254,9 +254,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE DE0Nano_USTCRVSoC_top.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/naive_bus.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/naive_bus_router.sv
|
||||
@ -278,4 +275,8 @@ set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_id_stage.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_alu.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_ex_branch_judge.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_bus_wrapper.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/dual_read_port_ram_32x32.sv
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@ -1,4 +1,4 @@
|
||||
/* Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version */
|
||||
/* Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version */
|
||||
JedecChain;
|
||||
FileRevision(JESD32A);
|
||||
DefaultMfr(6E);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="99887a9137618fe33d7a"/>
|
||||
<hash md5_digest_80b="e089878c50e17aa84bc1"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="EP4CE22F17C6" path="DE0Nano_USTCRVSoC.sof" usercode="0xFFFFFFFF"/>
|
||||
|
||||
Binary file not shown.
@ -1,7 +1,7 @@
|
||||
module core_alu(
|
||||
input logic [ 6:0] i_opcode, i_funct7,
|
||||
input logic [ 2:0] i_funct3,
|
||||
input logic [31:0] i_num1u, i_num2u, i_immu,
|
||||
input logic [31:0] i_num1u, i_num2u, i_immu, i_pc_immu,
|
||||
output logic [31:0] o_res
|
||||
);
|
||||
|
||||
@ -17,12 +17,14 @@ assign i_imms = i_immu;
|
||||
|
||||
always_comb
|
||||
casex({i_funct7,i_funct3,i_opcode})
|
||||
// LUI类
|
||||
17'bxxxxxxx_xxx_0110111 : o_res <= i_immu; // LUI
|
||||
// AUIPC类
|
||||
17'bxxxxxxx_xxx_0010111 : o_res <= i_pc_immu; // AUIPC
|
||||
// 算术类
|
||||
17'b0000000_000_0110011 : o_res <= i_num1u + i_num2u; // ADD
|
||||
17'bxxxxxxx_000_0010011 : o_res <= i_num1u + i_immu ; // ADDI
|
||||
17'b0100000_000_0110011 : o_res <= i_num1u - i_num2u; // SUB
|
||||
// LUI类
|
||||
17'bxxxxxxx_xxx_0110111 : o_res <= i_immu; // LUI
|
||||
// 逻辑类
|
||||
17'b0000000_100_0110011 : o_res <= i_num1u ^ i_num2u; // XOR
|
||||
17'bxxxxxxx_100_0010011 : o_res <= i_num1u ^ i_immu ; // XORI
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
module core_bus_wrapper(
|
||||
input logic clk, rst_n,
|
||||
input logic i_en_n,
|
||||
input logic i_re, i_we,
|
||||
output logic o_conflict, o_conflict_latch,
|
||||
input logic [ 2:0] i_funct3,
|
||||
@ -70,10 +71,10 @@ always @ (posedge clk or negedge rst_n)
|
||||
o_conflict_latch <= 1'b0;
|
||||
rdata_latch <= 0;
|
||||
end else begin
|
||||
i_re_latch <= i_re;
|
||||
i_re_latch <= i_re & ~i_en_n;
|
||||
rd_addr_lsb <= addr_lsb;
|
||||
rd_funct3 <= i_funct3;
|
||||
o_conflict_latch <= o_conflict;
|
||||
o_conflict_latch <= o_conflict | i_en_n;
|
||||
rdata_latch <= o_rdata;
|
||||
end
|
||||
|
||||
|
||||
@ -17,7 +17,7 @@ logic [31:0] instr;
|
||||
|
||||
enum {UKNOWN_TYPE, R_TYPE, I_TYPE, IZ_TYPE, S_TYPE, B_TYPE, U_TYPE, J_TYPE} instr_type;
|
||||
|
||||
localparam OPCODE_AUIPC = 7'b0010111, // rd=pc+4, pc= pc+imm
|
||||
localparam OPCODE_AUIPC = 7'b0010111, // rd=pc+imm
|
||||
OPCODE_JAL = 7'b1101111, // rd=pc+4, pc= pc+imm*2,
|
||||
OPCODE_JALR = 7'b1100111, // rd=pc+4, pc= rs1+imm
|
||||
OPCODE_BXXX = 7'b1100011, // conditional branch, pc= pc+imm*2,
|
||||
@ -32,11 +32,11 @@ assign o_next_pc = i_pc + 4;
|
||||
assign o_pc_plus_imm = i_pc + o_imm;
|
||||
assign {o_funct7, o_rs2_addr, o_rs1_addr, o_funct3, o_dst_reg_addr, o_opcode} = instr;
|
||||
|
||||
assign o_jal = (o_opcode == OPCODE_JAL || o_opcode == OPCODE_AUIPC );
|
||||
assign o_jal = (o_opcode == OPCODE_JAL );
|
||||
assign o_jalr = (o_opcode == OPCODE_JALR );
|
||||
assign o_branch_may = (o_opcode == OPCODE_BXXX );
|
||||
assign o_nextpc2reg = (o_opcode == OPCODE_JAL || o_opcode == OPCODE_AUIPC || o_opcode == OPCODE_JALR );
|
||||
assign o_alures2reg = (o_opcode == OPCODE_LUI || o_opcode == OPCODE_ALI || o_opcode == OPCODE_ALR);
|
||||
assign o_nextpc2reg = (o_opcode == OPCODE_JAL || o_opcode == OPCODE_JALR );
|
||||
assign o_alures2reg = (o_opcode == OPCODE_LUI || o_opcode == OPCODE_AUIPC || o_opcode == OPCODE_ALI || o_opcode == OPCODE_ALR);
|
||||
assign o_memory2reg = (o_opcode == OPCODE_LOAD );
|
||||
assign o_mem_write = (o_opcode == OPCODE_STORE);
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
// Priority : Write Port 1 > Write Port 2 > Write Port 3
|
||||
|
||||
module core_regfile(
|
||||
input logic clk, rst_n,
|
||||
input logic rd_latch,
|
||||
@ -11,70 +11,87 @@ module core_regfile(
|
||||
input logic [4:0] i_raddr2,
|
||||
output logic [31:0] o_rdata2,
|
||||
// forward port 1
|
||||
input logic i_we1,
|
||||
input logic [4:0] i_waddr1,
|
||||
input logic [31:0] i_wdata1,
|
||||
input logic i_forward1,
|
||||
input logic [4:0] i_faddr1,
|
||||
input logic [31:0] i_fdata1,
|
||||
// forward port 2
|
||||
input logic i_we2,
|
||||
input logic [4:0] i_waddr2,
|
||||
input logic [31:0] i_wdata2,
|
||||
input logic i_forward2,
|
||||
input logic [4:0] i_faddr2,
|
||||
input logic [31:0] i_fdata2,
|
||||
// Write port
|
||||
input logic i_we,
|
||||
input logic [4:0] i_waddr,
|
||||
input logic [31:0] i_wdata
|
||||
);
|
||||
|
||||
logic [31:1] [31:0] reg_file_cell = 992'h0;
|
||||
logic [31:0] reg_rdata1, reg_rdata2;
|
||||
logic [31:0] forward_data1, forward_data2;
|
||||
logic from_fw1, from_fw2;
|
||||
|
||||
// handle regwrite
|
||||
always @ (posedge clk or negedge rst_n) begin
|
||||
if(~rst_n)
|
||||
reg_file_cell <= 992'h0;
|
||||
else begin
|
||||
if(i_we && i_waddr!=5'h0)
|
||||
reg_file_cell[i_waddr] <= i_wdata;
|
||||
end
|
||||
end
|
||||
assign o_rdata1 = from_fw1 ? forward_data1 : reg_rdata1;
|
||||
assign o_rdata2 = from_fw2 ? forward_data2 : reg_rdata2;
|
||||
|
||||
|
||||
always @ (posedge clk or negedge rst_n) begin
|
||||
if(~rst_n)
|
||||
o_rdata1 <= 0;
|
||||
else begin
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if(~rst_n) begin
|
||||
from_fw1 <= 1'b0;
|
||||
forward_data1 <= 0;
|
||||
end else begin
|
||||
if(rd_latch) begin
|
||||
o_rdata1 <= o_rdata1;
|
||||
end else if(i_re1 && i_raddr1!=5'h0) begin
|
||||
if (i_we1 && i_raddr1==i_waddr1)
|
||||
o_rdata1 <= i_wdata1;
|
||||
else if(i_we2 && i_raddr1==i_waddr2)
|
||||
o_rdata1 <= i_wdata2;
|
||||
else if(i_we && i_raddr1==i_waddr)
|
||||
o_rdata1 <= i_wdata;
|
||||
else
|
||||
o_rdata1 <= reg_file_cell[i_raddr1];
|
||||
end else
|
||||
o_rdata1 <= 0;
|
||||
from_fw1 <= 1'b1;
|
||||
forward_data1 <= o_rdata1;
|
||||
end else if((~i_re1) || i_raddr1==5'h0 ) begin
|
||||
from_fw1 <= 1'b1;
|
||||
forward_data1 <= 0;
|
||||
end else if(i_forward1 && i_faddr1==i_raddr1) begin
|
||||
from_fw1 <= 1'b1;
|
||||
forward_data1 <= i_fdata1;
|
||||
end else if(i_forward2 && i_faddr2==i_raddr1) begin
|
||||
from_fw1 <= 1'b1;
|
||||
forward_data1 <= i_fdata2;
|
||||
end else if(i_we && i_waddr ==i_raddr1) begin
|
||||
from_fw1 <= 1'b1;
|
||||
forward_data1 <= i_wdata;
|
||||
end else begin
|
||||
from_fw1 <= 1'b0;
|
||||
forward_data1 <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge clk or negedge rst_n) begin
|
||||
if(~rst_n)
|
||||
o_rdata2 <= 0;
|
||||
else begin
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if(~rst_n) begin
|
||||
from_fw2 <= 1'b0;
|
||||
forward_data2 <= 0;
|
||||
end else begin
|
||||
if(rd_latch) begin
|
||||
o_rdata2 <= o_rdata2;
|
||||
end else if(i_re2 && i_raddr2!=5'h0) begin
|
||||
if (i_we1 && i_raddr2==i_waddr1)
|
||||
o_rdata2 <= i_wdata1;
|
||||
else if(i_we2 && i_raddr2==i_waddr2)
|
||||
o_rdata2 <= i_wdata2;
|
||||
else if(i_we && i_raddr2==i_waddr)
|
||||
o_rdata2 <= i_wdata;
|
||||
else
|
||||
o_rdata2 <= reg_file_cell[i_raddr2];
|
||||
end else
|
||||
o_rdata2 <= 0;
|
||||
from_fw2 <= 1'b1;
|
||||
forward_data2 <= o_rdata2;
|
||||
end else if((~i_re2) || i_raddr2==5'h0 ) begin
|
||||
from_fw2 <= 1'b1;
|
||||
forward_data2 <= 0;
|
||||
end else if(i_forward1 && i_faddr1==i_raddr2) begin
|
||||
from_fw2 <= 1'b1;
|
||||
forward_data2 <= i_fdata1;
|
||||
end else if(i_forward2 && i_faddr2==i_raddr2) begin
|
||||
from_fw2 <= 1'b1;
|
||||
forward_data2 <= i_fdata2;
|
||||
end else if(i_we && i_waddr ==i_raddr2) begin
|
||||
from_fw2 <= 1'b1;
|
||||
forward_data2 <= i_wdata;
|
||||
end else begin
|
||||
from_fw2 <= 1'b0;
|
||||
forward_data2 <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
dual_read_port_ram_32x32 dual_read_port_ram_32x32_for_regfile( // 32bit*32addr
|
||||
.clk ( clk ),
|
||||
.i_we ( i_we ),
|
||||
.i_waddr ( i_waddr ),
|
||||
.i_wdata ( i_wdata ),
|
||||
.i_raddr1 ( i_raddr1 ),
|
||||
.o_rdata1 ( reg_rdata1 ),
|
||||
.i_raddr2 ( i_raddr2 ),
|
||||
.o_rdata2 ( reg_rdata2 )
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -49,7 +49,7 @@ logic id_data_bus_conflict, mem_data_bus_conflict;
|
||||
// -------------------------------------------------------------------------------
|
||||
// conflict - comb logic
|
||||
// -------------------------------------------------------------------------------
|
||||
assign pc_stall = id_stall | id_data_bus_conflict;
|
||||
assign pc_stall = wreg_conflict | id_data_bus_conflict;
|
||||
assign id_stall = wreg_conflict;
|
||||
assign ex_stall = mem_data_bus_conflict;
|
||||
assign mem_stall = mem_data_bus_conflict;
|
||||
@ -85,21 +85,22 @@ always_comb
|
||||
// IF-ID stage - timing logic
|
||||
// -------------------------------------------------------------------------------
|
||||
core_bus_wrapper inst_bus_wrap_inst(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
.i_re ( ~id_stall ),
|
||||
.i_we ( 1'b0 ),
|
||||
.o_conflict_latch ( id_data_bus_conflict ),
|
||||
.i_funct3 ( 3'b010 ),
|
||||
.i_addr ( if_pc ),
|
||||
.i_wdata ( 0 ),
|
||||
.o_rdata ( id_instr ),
|
||||
.bus_master ( instr_master )
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
.i_en_n ( mem_data_bus_conflict ),
|
||||
.i_re ( ~id_stall ),
|
||||
.i_we ( 1'b0 ),
|
||||
.o_conflict_latch ( id_data_bus_conflict ),
|
||||
.i_funct3 ( 3'b010 ),
|
||||
.i_addr ( if_pc ),
|
||||
.i_wdata ( 0 ),
|
||||
.o_rdata ( id_instr ),
|
||||
.bus_master ( instr_master )
|
||||
);
|
||||
always @ (posedge clk)
|
||||
if(~rst_n)
|
||||
id_pc <= {i_boot_addr[31:2],2'b00} - 4;
|
||||
else
|
||||
else if(~mem_data_bus_conflict)
|
||||
id_pc <= if_pc;
|
||||
|
||||
|
||||
@ -134,29 +135,30 @@ core_id_stage core_id_stage_inst(
|
||||
// ID-EX stage - timing logic
|
||||
// -------------------------------------------------------------------------------
|
||||
core_regfile core_regfile_inst(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
.rd_latch ( ex_stall ),
|
||||
.i_re1 ( id_rs1_en ),
|
||||
.i_raddr1 ( id_rs1_addr ),
|
||||
.o_rdata1 ( ex_s1 ),
|
||||
.i_re2 ( id_rs2_en ),
|
||||
.i_raddr2 ( id_rs2_addr ),
|
||||
.o_rdata2 ( ex_s2 ),
|
||||
.i_we1 ( ex_nextpc2reg ),
|
||||
.i_waddr1 ( ex_dst_reg_addr),
|
||||
.i_wdata1 ( ex_next_pc ),
|
||||
.i_we2 ( mem_alures_or_nextpc2reg ),
|
||||
.i_waddr2 (mem_dst_reg_addr),
|
||||
.i_wdata2 ( mem_2regdata ),
|
||||
.i_we ( wb_2reg ),
|
||||
.i_waddr ( wb_dst_reg_addr),
|
||||
.i_wdata ( wb_reg_wdata )
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
.rd_latch ( ex_stall ),
|
||||
.i_re1 ( id_rs1_en ),
|
||||
.i_raddr1 ( id_rs1_addr ),
|
||||
.o_rdata1 ( ex_s1 ),
|
||||
.i_re2 ( id_rs2_en ),
|
||||
.i_raddr2 ( id_rs2_addr ),
|
||||
.o_rdata2 ( ex_s2 ),
|
||||
.i_forward1 ( ex_nextpc2reg ),
|
||||
.i_faddr1 ( ex_dst_reg_addr ),
|
||||
.i_fdata1 ( ex_next_pc ),
|
||||
.i_forward2 ( mem_alures_or_nextpc2reg ),
|
||||
.i_faddr2 ( mem_dst_reg_addr ),
|
||||
.i_fdata2 ( mem_2regdata ),
|
||||
.i_we ( wb_2reg ),
|
||||
.i_waddr ( wb_dst_reg_addr ),
|
||||
.i_wdata ( wb_reg_wdata )
|
||||
);
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if(~rst_n) begin
|
||||
ex_jalr <= 1'b0;
|
||||
ex_branch_may <= 1'b0;
|
||||
ex_pc_plus_imm <= 0;
|
||||
ex_nextpc2reg <= 1'b0;
|
||||
ex_alures2reg <= 1'b0;
|
||||
ex_memory2reg <= 1'b0;
|
||||
@ -188,13 +190,14 @@ always @ (posedge clk or negedge rst_n)
|
||||
// EX stage - comb logic
|
||||
// -------------------------------------------------------------------------------
|
||||
core_alu core_alu_inst(
|
||||
.i_opcode ( ex_opcode ),
|
||||
.i_funct7 ( ex_funct7 ),
|
||||
.i_funct3 ( ex_funct3 ),
|
||||
.i_num1u ( ex_s1 ),
|
||||
.i_num2u ( ex_s2 ),
|
||||
.i_immu ( ex_imm ),
|
||||
.o_res ( ex_alu_res )
|
||||
.i_opcode ( ex_opcode ),
|
||||
.i_funct7 ( ex_funct7 ),
|
||||
.i_funct3 ( ex_funct3 ),
|
||||
.i_num1u ( ex_s1 ),
|
||||
.i_num2u ( ex_s2 ),
|
||||
.i_immu ( ex_imm ),
|
||||
.i_pc_immu ( ex_pc_plus_imm ),
|
||||
.o_res ( ex_alu_res )
|
||||
);
|
||||
core_ex_branch_judge core_ex_branch_judge_inst(
|
||||
.i_branch ( ex_branch_may ),
|
||||
@ -243,6 +246,7 @@ assign mem_2regdata = mem_alures2reg ? mem_alu_res : mem_next_pc;
|
||||
core_bus_wrapper core_bus_wrapper_inst(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
.i_en_n ( 1'b0 ),
|
||||
.i_re ( mem_memory2reg ),
|
||||
.i_we ( mem_memwrite ),
|
||||
.o_conflict ( mem_data_bus_conflict ),
|
||||
|
||||
25
hardware/RTL/dual_read_port_ram_32x32.sv
Normal file
25
hardware/RTL/dual_read_port_ram_32x32.sv
Normal file
@ -0,0 +1,25 @@
|
||||
module dual_read_port_ram_32x32( // 32bit*32addr
|
||||
input logic clk,
|
||||
input logic i_we,
|
||||
input logic [ 4:0] i_waddr,
|
||||
input logic [31:0] i_wdata,
|
||||
input logic [ 4:0] i_raddr1,
|
||||
output logic [31:0] o_rdata1,
|
||||
input logic [ 4:0] i_raddr2,
|
||||
output logic [31:0] o_rdata2
|
||||
);
|
||||
initial begin o_rdata1 = 0; o_rdata2 = 0; end
|
||||
|
||||
logic [31:0] data_ram_cell [0:31];
|
||||
|
||||
always @ (posedge clk)
|
||||
o_rdata1 <= data_ram_cell[i_raddr1];
|
||||
|
||||
always @ (posedge clk)
|
||||
o_rdata2 <= data_ram_cell[i_raddr2];
|
||||
|
||||
always @ (posedge clk)
|
||||
if(i_we)
|
||||
data_ram_cell[i_waddr] <= i_wdata;
|
||||
|
||||
endmodule
|
||||
@ -7,7 +7,7 @@ module ram( // 1024B
|
||||
);
|
||||
initial o_rdata = 8'h0;
|
||||
|
||||
logic [7:0] data_ram_cell [0:1023] ;
|
||||
logic [7:0] data_ram_cell [0:1023];
|
||||
|
||||
always @ (posedge clk)
|
||||
o_rdata <= data_ram_cell[i_raddr];
|
||||
|
||||
@ -7,7 +7,7 @@ module ram128B( // 128B
|
||||
);
|
||||
initial o_rdata = 8'h0;
|
||||
|
||||
logic [7:0] data_ram_cell [0:127] ;
|
||||
logic [7:0] data_ram_cell [0:127];
|
||||
|
||||
always @ (posedge clk)
|
||||
o_rdata <= data_ram_cell[i_addr];
|
||||
|
||||
@ -28,7 +28,7 @@ isp_uart #(
|
||||
.o_uart_tx ( isp_uart_tx ),
|
||||
.o_rst_n ( rst_n ),
|
||||
.o_boot_addr ( boot_addr ),
|
||||
.bus ( bus_masters[1] ),
|
||||
.bus ( bus_masters[0] ),
|
||||
.user_uart_bus ( bus_slaves[4] )
|
||||
);
|
||||
|
||||
@ -38,7 +38,7 @@ core_top core_top_inst(
|
||||
.rst_n ( rst_n ),
|
||||
.i_boot_addr ( boot_addr ),
|
||||
.instr_master ( bus_masters[2] ),
|
||||
.data_master ( bus_masters[0] )
|
||||
.data_master ( bus_masters[1] )
|
||||
);
|
||||
|
||||
// 指令ROM
|
||||
|
||||
@ -4,16 +4,20 @@ logic clk;
|
||||
initial clk = 1'b1;
|
||||
always #1 clk = ~clk;
|
||||
|
||||
wire vga_vsync, vga_hsync, isp_uart_tx;
|
||||
wire [15:0] vga_pixel;
|
||||
wire isp_uart_tx, vga_hsync, vga_vsync;
|
||||
wire [ 2:0] vga_pixel;
|
||||
|
||||
soc_top soc_inst(
|
||||
.clk ( clk ),
|
||||
.isp_uart_rx ( 1'b1 ),
|
||||
.isp_uart_tx ( isp_uart_tx ),
|
||||
.vga_hsync ( vga_hsync ),
|
||||
.vga_vsync ( vga_vsync ),
|
||||
.vga_pixel ( vga_pixel )
|
||||
.clk ( clk ),
|
||||
.isp_uart_rx ( 1'b1 ),
|
||||
.isp_uart_tx ( isp_uart_tx ),
|
||||
.vga_hsync ( vga_hsync ),
|
||||
.vga_vsync ( vga_vsync ),
|
||||
.vga_red ( vga_pixel[2] ),
|
||||
.vga_green ( vga_pixel[1] ),
|
||||
.vga_blue ( vga_pixel[0] )
|
||||
);
|
||||
|
||||
initial #10000 $stop;
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3231:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00
|
||||
@ -9,57 +9,61 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:637265617465636f6e73747261696e747366696c6570616e656c5f66696c655f6e616d65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f74797065:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:313037:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3231:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:313336:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6970636f7265766965775f7461626265645f70616e65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c6f676d6f6e69746f725f6d6f6e69746f72:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c6f676d6f6e69746f725f6d6f6e69746f72:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f68656c70:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746f6f6c73:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f76696577:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f77696e646f77:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e746f6f6c6261726d67725f72756e:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e746f6f6c6261726d67725f72756e:3136:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e77696e6d656e756d67725f6c61796f7574:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d657373616765776974686f7074696f6e6469616c6f675f646f6e745f73686f775f746869735f6469616c6f675f616761696e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f7365766572697479:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:3431:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:3537:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f637269746963616c5f7761726e696e6773:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f7761726e696e675f6d65737361676573:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e65746c69737474726565766965775f6e65746c6973745f74726565:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:3133:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e65746c69737474726565766965775f6e65746c6973745f74726565:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:3134:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f676f746f5f6e65746c6973745f64657369676e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6c6963656e73655f6d616e616765:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7265706f7274735f77696e646f77:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f62697467656e:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f73796e746865736973:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f62697467656e:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f696d706c656d656e746174696f6e:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f73796e746865736973:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7365745f61735f746f70:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f646576696365:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061727463686f6f7365725f66616d696c795f63686f6f736572:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061727463686f6f7365725f7061727473:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f737065636966795f62697473747265616d5f66696c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f63686f6f73655f70726f6a6563745f6c6f636174696f6e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d61727974696d696e6770616e656c5f70726f6a6563745f73756d6d6172795f74696d696e675f70616e656c5f746162626564:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d61727974696d696e6770616e656c5f70726f6a6563745f73756d6d6172795f74696d696e675f70616e656c5f746162626564:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d6172797574696c697a6174696f6e6761646765745f70726f6a6563745f73756d6d6172795f7574696c697a6174696f6e5f6761646765745f746162626564:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d6172797574696c697a6174696f6e70616e656c5f70726f6a6563745f73756d6d6172795f7574696c697a6174696f6e5f70616e656c5f746162626564:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d6172797574696c697a6174696f6e70616e656c5f70726f6a6563745f73756d6d6172795f7574696c697a6174696f6e5f70616e656c5f746162626564:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f72756e5f6761646765745f7461626265645f70616e65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f73686f775f6572726f72:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f73686f775f7761726e696e675f616e645f6572726f725f6d657373616765735f696e5f6d65737361676573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f63616e63656c:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f726566726573685f686965726172636879:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7374616c6572756e6469616c6f675f796573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73746174656d6f6e69746f725f72657365745f72756e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:746f756368706f696e747375727665796469616c6f675f6e6f:31:00:00
|
||||
eof:1806825388
|
||||
eof:835461017
|
||||
|
||||
@ -1,21 +1,21 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f726576696577:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:3136:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265706f72747574696c697a6174696f6e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766566696c6570726f787968616e646c6572:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574746f706e6f6465:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7570646174657265676964:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b73796e746865736973:31:00:00
|
||||
eof:3437607480
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b73796e746865736973:32:00:00
|
||||
eof:1797919527
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
version:1
|
||||
57656254616c6b5472616e736d697373696f6e417474656d70746564:5
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:7
|
||||
57656254616c6b5472616e736d697373696f6e417474656d70746564:7
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:9
|
||||
eof:
|
||||
|
||||
@ -33,7 +33,7 @@ version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a333273:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313137312e3836334d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3838332e3431304d42:00:00
|
||||
eof:3042997517
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a333073:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313036372e3932324d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3737382e3639394d42:00:00
|
||||
eof:3866055585
|
||||
|
||||
@ -3,10 +3,10 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Fri Mar 1 00:26:47 2019">
|
||||
<application name="pa" timeStamp="Sun Mar 3 15:54:28 2019">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="802f49394334431ea9abba122e836e9e" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="14" type="ProjectIteration"/>
|
||||
<property name="ProjectIteration" value="20" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
@ -17,30 +17,30 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddSources" value="6" type="JavaHandler"/>
|
||||
<property name="AutoConnectTarget" value="4" type="JavaHandler"/>
|
||||
<property name="AddSources" value="7" type="JavaHandler"/>
|
||||
<property name="AutoConnectTarget" value="6" type="JavaHandler"/>
|
||||
<property name="CoreView" value="1" type="JavaHandler"/>
|
||||
<property name="CustomizeCore" value="1" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="4" type="JavaHandler"/>
|
||||
<property name="LaunchProgramFpga" value="4" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="5" type="JavaHandler"/>
|
||||
<property name="LaunchProgramFpga" value="6" type="JavaHandler"/>
|
||||
<property name="NewProject" value="1" type="JavaHandler"/>
|
||||
<property name="OpenHardwareManager" value="11" type="JavaHandler"/>
|
||||
<property name="OpenRecentTarget" value="5" type="JavaHandler"/>
|
||||
<property name="ProgramDevice" value="4" type="JavaHandler"/>
|
||||
<property name="OpenHardwareManager" value="16" type="JavaHandler"/>
|
||||
<property name="OpenRecentTarget" value="7" type="JavaHandler"/>
|
||||
<property name="ProgramDevice" value="6" type="JavaHandler"/>
|
||||
<property name="ReportUtilization" value="1" type="JavaHandler"/>
|
||||
<property name="RunBitgen" value="9" type="JavaHandler"/>
|
||||
<property name="RunImplementation" value="4" type="JavaHandler"/>
|
||||
<property name="RunSynthesis" value="7" type="JavaHandler"/>
|
||||
<property name="RunBitgen" value="11" type="JavaHandler"/>
|
||||
<property name="RunImplementation" value="8" type="JavaHandler"/>
|
||||
<property name="RunSynthesis" value="11" type="JavaHandler"/>
|
||||
<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/>
|
||||
<property name="SetTopNode" value="2" type="JavaHandler"/>
|
||||
<property name="ShowView" value="7" type="JavaHandler"/>
|
||||
<property name="ShowView" value="8" type="JavaHandler"/>
|
||||
<property name="UpdateRegId" value="1" type="JavaHandler"/>
|
||||
<property name="ViewTaskSynthesis" value="1" type="JavaHandler"/>
|
||||
<property name="ViewTaskSynthesis" value="2" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="AddSrcWizard_SPECIFY_HDL_NETLIST_BLOCK_DESIGN" value="2" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CANCEL" value="4" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="17" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CANCEL" value="5" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="21" type="GuiHandlerData"/>
|
||||
<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="2" type="GuiHandlerData"/>
|
||||
<property name="ConstraintsChooserPanel_ADD_FILES" value="1" type="GuiHandlerData"/>
|
||||
<property name="ConstraintsChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
|
||||
@ -48,60 +48,69 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="CreateConstraintsFilePanel_FILE_NAME" value="2" type="GuiHandlerData"/>
|
||||
<property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="CreateSrcFileDialog_FILE_TYPE" value="1" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="107" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="21" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="136" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="28" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="7" type="GuiHandlerData"/>
|
||||
<property name="IPCoreView_TABBED_PANE" value="2" type="GuiHandlerData"/>
|
||||
<property name="LogMonitor_MONITOR" value="3" type="GuiHandlerData"/>
|
||||
<property name="LogMonitor_MONITOR" value="4" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_HELP" value="4" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_TOOLS" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_VIEW" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_WINDOW" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainToolbarMgr_RUN" value="9" type="GuiHandlerData"/>
|
||||
<property name="MainToolbarMgr_RUN" value="16" type="GuiHandlerData"/>
|
||||
<property name="MainWinMenuMgr_LAYOUT" value="2" type="GuiHandlerData"/>
|
||||
<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_SEVERITY" value="2" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="41" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="57" type="GuiHandlerData"/>
|
||||
<property name="MsgView_CRITICAL_WARNINGS" value="5" type="GuiHandlerData"/>
|
||||
<property name="MsgView_WARNING_MESSAGES" value="2" type="GuiHandlerData"/>
|
||||
<property name="NetlistTreeView_NETLIST_TREE" value="11" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_SOURCES" value="6" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="4" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_UPDATE_HIER" value="13" type="GuiHandlerData"/>
|
||||
<property name="NetlistTreeView_NETLIST_TREE" value="15" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_SOURCES" value="7" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="6" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_UPDATE_HIER" value="14" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GOTO_NETLIST_DESIGN" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_LICENSE_MANAGE" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_REPORTS_WINDOW" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_BITGEN" value="9" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_SYNTHESIS" value="7" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_BITGEN" value="11" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_IMPLEMENTATION" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_SYNTHESIS" value="11" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SET_AS_TOP" value="2" type="GuiHandlerData"/>
|
||||
<property name="PAViews_CODE" value="8" type="GuiHandlerData"/>
|
||||
<property name="PAViews_CODE" value="11" type="GuiHandlerData"/>
|
||||
<property name="PAViews_DEVICE" value="2" type="GuiHandlerData"/>
|
||||
<property name="PartChooser_FAMILY_CHOOSER" value="1" type="GuiHandlerData"/>
|
||||
<property name="PartChooser_PARTS" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProgramFpgaDialog_PROGRAM" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProgramFpgaDialog_PROGRAM" value="4" type="GuiHandlerData"/>
|
||||
<property name="ProgramFpgaDialog_SPECIFY_BITSTREAM_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_PROJECT_NAME" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProjectSummaryTimingPanel_PROJECT_SUMMARY_TIMING_PANEL_TABBED" value="11" type="GuiHandlerData"/>
|
||||
<property name="ProjectSummaryTimingPanel_PROJECT_SUMMARY_TIMING_PANEL_TABBED" value="17" type="GuiHandlerData"/>
|
||||
<property name="ProjectSummaryUtilizationGadget_PROJECT_SUMMARY_UTILIZATION_GADGET_TABBED" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_PANEL_TABBED" value="2" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_DELETE" value="4" type="GuiHandlerData"/>
|
||||
<property name="ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_PANEL_TABBED" value="4" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_DELETE" value="5" type="GuiHandlerData"/>
|
||||
<property name="RunGadget_RUN_GADGET_TABBED_PANE" value="1" type="GuiHandlerData"/>
|
||||
<property name="RunGadget_SHOW_ERROR" value="2" type="GuiHandlerData"/>
|
||||
<property name="RunGadget_SHOW_WARNING_AND_ERROR_MESSAGES_IN_MESSAGES" value="1" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_SAVE" value="2" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="3" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="4" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_HIERARCHY" value="11" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_REFRESH_HIERARCHY" value="1" type="GuiHandlerData"/>
|
||||
<property name="StaleRunDialog_YES" value="1" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="3" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="StateMonitor_RESET_RUN" value="1" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="4" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaStateMonitor_CANCEL" value="2" type="GuiHandlerData"/>
|
||||
<property name="TaskBanner_CLOSE" value="1" type="GuiHandlerData"/>
|
||||
<property name="TouchpointSurveyDialog_NO" value="1" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="22" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="20" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
|
||||
@ -9,20 +9,22 @@ module Nexys4_USTCRVSoC_top(
|
||||
output logic [3:0] VGA_R, VGA_G, VGA_B
|
||||
);
|
||||
|
||||
logic clk = 1'b0;
|
||||
logic rst_n;
|
||||
logic vga_red, vga_green, vga_blue;
|
||||
assign {VGA_R, VGA_G, VGA_B} = {{4{vga_red}}, {4{vga_green}}, {4{vga_blue}}};
|
||||
|
||||
always @ (posedge CLK100MHZ)
|
||||
clk <= ~clk;
|
||||
|
||||
soc_top soc_inst (
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
soc_top #(
|
||||
.UART_RX_CLK_DIV ( 217 ),
|
||||
.UART_TX_CLK_DIV ( 868 ),
|
||||
.VGA_CLK_DIV ( 2 )
|
||||
)soc_inst (
|
||||
.clk ( CLK100MHZ ),
|
||||
.isp_uart_rx ( UART_TXD_IN ),
|
||||
.isp_uart_tx ( UART_RXD_OUT ),
|
||||
.vga_hsync ( VGA_HS ),
|
||||
.vga_vsync ( VGA_VS ),
|
||||
.vga_pixel ( {VGA_R, VGA_G, VGA_B} )
|
||||
.vga_red ( vga_red ),
|
||||
.vga_green ( vga_green ),
|
||||
.vga_blue ( vga_blue )
|
||||
);
|
||||
|
||||
// <20>ڿ<EFBFBD><DABF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>LED<45><44><EFBFBD><EFBFBD>ʾISP-UART<52>ķ<EFBFBD><C4B7>͵ƺͽ<C6BA><CDBD>յ<EFBFBD>
|
||||
@ -31,11 +33,7 @@ assign LED[15:14] = ~{UART_TXD_IN, UART_RXD_OUT};
|
||||
// <20><>ˮ<EFBFBD>ƣ<EFBFBD>ָʾSoC<6F><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
reg [21:0] cnt = 22'h0;
|
||||
reg [ 7:0] flow = 7'h0;
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if(~rst_n) begin
|
||||
cnt <= 22'h0;
|
||||
flow <= 7'h0;
|
||||
end else begin
|
||||
always @ (posedge CLK100MHZ) begin
|
||||
cnt <= cnt + 22'h1;
|
||||
if(cnt==22'h0)
|
||||
flow <= {flow[6:0], ~flow[7]};
|
||||
|
||||
@ -55,6 +55,13 @@
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../../RTL/char8x16_rom.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_alu.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@ -97,6 +104,13 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/dual_read_port_ram_32x32.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/instr_rom.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@ -132,6 +146,13 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/ram128B.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/ram_bus_wrapper.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@ -167,6 +188,13 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/vga_char_86x32.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/video_ram.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
|
||||
@ -2,18 +2,36 @@
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Tue Feb 26 19:48:38 2019
|
||||
# Process ID: 11396
|
||||
# Start of session at: Sun Mar 3 14:15:36 2019
|
||||
# Process ID: 16476
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18496 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent10728 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
update_compile_order -fileset sources_1
|
||||
add_files -norecurse {E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv}
|
||||
update_compile_order -fileset sources_1
|
||||
export_ip_user_files -of_objects [get_files E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv] -no_script -reset -force -quiet
|
||||
remove_files E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 8
|
||||
wait_on_run synth_1
|
||||
reset_run impl_1
|
||||
open_run synth_1 -name synth_1
|
||||
launch_runs impl_1 -jobs 8
|
||||
wait_on_run impl_1
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
wait_on_run impl_1
|
||||
open_hw
|
||||
connect_hw_server
|
||||
open_hw_target
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
current_hw_device [get_hw_devices xc7a100t_0]
|
||||
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
program_hw_devices [get_hw_devices xc7a100t_0]
|
||||
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
|
||||
@ -0,0 +1,19 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Tue Feb 26 19:48:38 2019
|
||||
# Process ID: 11396
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18496 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
update_compile_order -fileset sources_1
|
||||
launch_runs synth_1 -jobs 8
|
||||
wait_on_run synth_1
|
||||
reset_run impl_1
|
||||
launch_runs impl_1 -jobs 8
|
||||
wait_on_run impl_1
|
||||
@ -2,11 +2,11 @@
|
||||
.global _start
|
||||
_start:
|
||||
|
||||
lui sp, 0x00010
|
||||
lui sp, 0x00020
|
||||
ori sp, sp, 0x400 # stack pointer=0x400, stack size = 256 dwords
|
||||
|
||||
xori t0, zero, 7 # t0 = 7
|
||||
jal ra, fibonacci_recursive # fib(7) = 21 = 0x15
|
||||
xori t0, zero, 8 # t0 = 8
|
||||
jal ra, fibonacci_recursive # fib(8) = 34 = 0x22
|
||||
|
||||
jal zero, print_result # 跳到死循环打印程序，循环打印斐波那契计算结果，应该打印的是0x15
|
||||
|
||||
@ -31,8 +31,9 @@ tag:
|
||||
jal ra, fibonacci_recursive # fibonacci_recursive n-1
|
||||
|
||||
lw t0, 0(sp) # t0=mem[sp] # pop t0 from stack
|
||||
addi sp, sp, 4 # sp+=4
|
||||
addi t0, t0, -1 # t0-=1
|
||||
addi sp, sp, 4 # sp+=4
|
||||
|
||||
|
||||
addi sp, sp, -4 # sp-=4 # push t1 to stack
|
||||
sw t1, (sp) # mem[sp] = t1
|
||||
@ -54,5 +55,5 @@ print_result: # 延时循环打印斐波那契计算结果
|
||||
big_loop:
|
||||
addi t2, t2, -1 # t2 = t2-1
|
||||
bne t2, zero, big_loop # if t2!=0, jmp to big_loop
|
||||
jal zero, print_result # 大循环结束，跳到print_result，重复打印
|
||||
jal zero, _start # 大循环结束，跳到开头t，重复计算
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
.org 0x0
|
||||
.global _start
|
||||
_start:
|
||||
lui a0, 0x00010
|
||||
ori a0, a0, 0x100
|
||||
lui a0, 0x00020
|
||||
ori a0, a0, 0x0a0
|
||||
addi a1, zero, 0xc8
|
||||
addi a2, zero, 0x56
|
||||
addi a3, zero, 0xa4
|
||||
|
||||
13
software/asm-code/test_auipc.S
Normal file
13
software/asm-code/test_auipc.S
Normal file
@ -0,0 +1,13 @@
|
||||
.org 0x0
|
||||
.global _start
|
||||
_start:
|
||||
lui a0, 0x00010
|
||||
auipc a1, 0x00010
|
||||
sw a1, 0(a0)
|
||||
auipc a1, 0x20000
|
||||
sw a1, 4(a0)
|
||||
auipc a1, 0x03000
|
||||
sw a1, 8(a0)
|
||||
auipc a1, 0x00a00
|
||||
sw a1, 12(a0)
|
||||
here: jal zero, here
|
||||
Loading…
x
Reference in New Issue
Block a user