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合并ISP-UART和USER-UART，添加Nexys4开发板工程

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38
README.md
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@ -33,12 +33,11 @@
> * **多主多从总线仲裁器(naive_bus_router.sv)**：为每个从设备划分地址空间，将主设备的总线读写请求路由到从设备。当多个主设备同时访问一个从设备时，还能进行访问冲突控制。
> * **RV32I Core(core_top.sv)**：包括两个主接口。一个用于取指令，一个用于读写数据
> * **UART调试器(isp_uart.sv)**：包括一个主接口。它接收用户从UART发来的命令，对总线进行读写。它可以用于在线烧写、在线调试。
> * **UART调试器(isp_uart.sv)**：包括一个主接口和一个从接口。它接收用户从UART发来的命令，对总线进行读写。它可以用于在线烧写、在线调试。也可以接收CPU的命令去发送数据。
> * **指令ROM(instr_rom.sv)**：CPU默认从这里开始取指令，多用于仿真
> * **指令RAM(ram_bus_wrapper.sv)**：用户在线烧写程序到这里。
> * **数据RAM(ram_bus_wrapper.sv)**：存放运行时的数据。
> * **显存RAM(vedio_ram.sv)**：在屏幕上显示98列*36行=3528个字符，显存RAM的前3528B对应的ASCII码值就决定了每个字符是什么
> * **用户UART(user_uart_tx)**：暂时只有发送功能，向其中写一个字节相当于把该字节放入发送缓冲区FIFO，缓冲区大小256B，缓冲区的数据会尽快发送。
# RV32I CPU 结构
@ -46,7 +45,7 @@
TODO
# 在DE0-Nano 开发板上运行SoC
# 在开发板上运行SoC
我们提供了两种方式运行代码：
@ -54,31 +53,31 @@ TODO
2、**使用指令RAM**：使用UART调试器在线上传程序到指令RAM。
### 部署电路到DE0-Nano FPGA
### 部署电路到FPGA
目前，我们提供了Xilinx的Nexys4板子和Altera的DE0-Nano板子的工程。
1、**Nexys4硬件连接**：Nexys4开发板上有一个USB口既可以用于FPGA烧录，也可以用于UART通信，我们需要连接该USB口到电脑。另外，VGA的连接是可选的，你可以把它连接到屏幕上。
![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/DE0-Nano.png)
1、**硬件连接**：DE0-Nano上的接口的意义如上图。你至少需要一个USB转UART的模块，将ISP-UART的TX和RX引脚连接上去，使之能与电脑通信，如下图：
2、**DE0-Nano硬件连接**：DE0-Nano开发板上既没有串口转USB，也没有VGA接口。因此都需要以来外部模块。我们使用DE0-Nano上的两排GPIO作为外接模块的引脚，接口意义如上图。你至少需要一个USB转UART的模块，将ISP-UART的TX和RX引脚连接上去，使之能与电脑通信，如下图：
![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/connection.png)
![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/usb_uart.png)
2、**综合、烧写FPGA**：用Quartus软件打开./Quartus/DE0_Nano/DE0_Nano.qpf，综合并烧写到DE0-Nano。
3、**综合、烧写FPGA**：如果你用的是Nexys4板子，请用Vivado打开./hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr。如果你用的是DE0-Nano板子，请用Quartus打开./hardware/Quartus/DE0_Nano/DE0_Nano.qpf。综合并烧写到开发板。
3、**尝试读取总线**：在电脑上的串口终端软件（超级终端、串口助手、minicom）中，使用格式(115200,n,8,1)发送00000000\n，如果看到收到一个8位16进制数，那么恭喜你SoC部署成功，该数代表SoC数据总线的地址0x00000000处的读取数据。如果没有收到数据，以下是可能的原因：
4、**HelloWorld**：烧录FPGA后，在电脑上的串口终端软件（超级终端、串口助手、minicom）中，使用格式(115200,n,8,1)打开串口，如果看到不断收到"hello\n"，那么恭喜你SoC部署成功，因为SoC的instr_rom里的程序就是循环打印hello的程序。
> * **硬件连接问题**：例如TX/RX接反，杜邦线接触不良等
> * **共地问题**：要求电脑的地与板子的地连接，如果DE0-Nano上的USB口与电脑连接，则已经共地，否则请额外使用杜邦线将USB转UART的地与DE0-Nano的地连接。
> * **COM口号选错**：如果不能确定USB转UART是哪个COM口，请将它拔下来，看哪个COM口消失了，再重新插入，就能确定COM号
> * **串口通信格式错误**：必须是115200波特率、8个数据位、1个停止位、无校验位。
> * **发送数据不对**：每个命令后必须有一个\n或\r，必须使用ASCII格式（很多串口助手软件提供十六进制发送功能，我们不需要，UART调试接口会自动将收到的ASCII变为十六进制）
5、**尝试读取总线**：下面让我们尝试UART的调试功能，首先发送"s\n"进入调试模式，可以看到对方发来"debug\n"，说明进入调试模式成功。然后，发送"00000000\n"，会看到对方发来一个8位16进制数。该数代表SoC数据总线的地址0x00000000处的读取数据。
4、上一步我们尝试了UART调试器的读总线命令，下表显示了它的所有3种命令。
6、上一步我们尝试了UART调试器的读总线命令，下表显示了它的所有3种命令。
![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/commands.png)
> * 注意：无论是发送还是接受，所有命令都以\n或\r结尾
> * 注意：无论是发送还是接受，所有命令都以\n或\r或\r\n结尾
根据这些命令，不难猜出，在线上传程序的流程是：
@ -86,11 +85,9 @@ TODO
> 2、使用复位命令r00008000，将CPU复位并从指令RAM种BOOT
### 使用工具：USTCRVSoC-tool
### 使用工具：USTCRVSoC-tool （该软件有所改动，文档稍后补充）
./USTCRVSoC-tool/USTCRVSoC-tool.exe 是一个能汇编和烧写的小工具，相当于一个汇编语言的IDE。界面如下图。
![Image text](https://github.com/WangXuan95/USTCRVSoC/blob/master/images/USTCRVSoC-tool-image.png)
./USTCRVSoC-tool/USTCRVSoC-tool.exe 是一个能汇编和烧写的小工具，相当于一个汇编语言的IDE。
我们提供了几个汇编小程序如下表。
@ -101,9 +98,8 @@ TODO
| fibonacci_recursive.S | 递归法计算斐波那契数列第7个数并，用用户UART打印结果 |
| load_store.S | 完成一些内存读写，没有具体表现，为了观察现象，可以使用UART调试器查看内存 |
现在我们尝试让SoC运行一个UART打印的程序。点击“打开...”按钮，浏览到目录./software/asm-code，打开汇编文件uart_print.S。点击右侧的“汇编”按钮，可以看到右下方框里出现了一串16进制数，这就是汇编得到的机器码。然后，选择正确的COM口，点击“烧写”，如果下方状态栏里显示“烧写成功”，则CPU就已经开始运行该机器码了。这是一个使用用户UART循环打印“hello!”的程序，
现在我们尝试让SoC运行一个计算斐波那契数列并UART打印的程序。点击“打开...”按钮，浏览到目录./software/asm-code，打开汇编文件uart_print.S。点击右侧的“汇编”按钮，可以看到右方框里出现了一串16进制数，这就是汇编得到的机器码。然后，选择正确的COM口，点击“烧写”，如果下方状态栏里显示“烧写成功”，则CPU就已经开始运行该机器码了。这时，在右侧的“串口查看”框里选中“16进制显示”，可以看到不断显示出15，这说明CPU正确的计算出斐波那契数列的第七个数是15。
> 注：用户UART与UART调试器不是同一个UART。为了观察现象，可以将UART调试器的杜邦线拔下来插在用户UART上，或者使用两个USB转UART模块。通信格式依然是(115200,n,8,1)。
# RTL仿真
@ -116,4 +112,4 @@ USTCRVSoC-tool.exe 除了进行烧写，也可以生成指令ROM的Verilog代码
生成ROM后请直接使用soc_top_tb.sv文件进行仿真，这个仿真是针对整个SoC的，因此你可以修改ROM程序后进行仿真，观察SoC运行该程序的行为。
> 注：这里没有提供仿真工程的示例，你可以新建Modelsim工程或Vivado工程进行仿真。仿真时请将./RTL/目录里的所有.sv文件都加入工程里。

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USTCRVSoC-tool-VS2012/USTCRVSoC-tool.v11.suo
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23
USTCRVSoC-tool-VS2012/USTCRVSoC-tool/MainForm.Designer.cs generated
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@ -56,11 +56,9 @@
this.tableLayoutPanel8 = new System.Windows.Forms.TableLayoutPanel();
this.userPortClearBtn = new System.Windows.Forms.Button();
this.userPortOpenCloseBtn = new System.Windows.Forms.Button();
this.userPortSelectionBox = new System.Windows.Forms.ComboBox();
this.userPortShowHex = new System.Windows.Forms.CheckBox();
this.UserPortRecvCountLabel = new System.Windows.Forms.Label();
this.serialPort = new System.IO.Ports.SerialPort(this.components);
this.UserSerialPort = new System.IO.Ports.SerialPort(this.components);
this.compileGroup.SuspendLayout();
this.tableLayoutPanel3.SuspendLayout();
this.HexStreamGroup.SuspendLayout();
@ -424,7 +422,6 @@
this.tableLayoutPanel8.ColumnStyles.Add(new System.Windows.Forms.ColumnStyle(System.Windows.Forms.SizeType.Percent, 25F));
this.tableLayoutPanel8.Controls.Add(this.userPortClearBtn, 1, 1);
this.tableLayoutPanel8.Controls.Add(this.userPortOpenCloseBtn, 1, 0);
this.tableLayoutPanel8.Controls.Add(this.userPortSelectionBox, 0, 0);
this.tableLayoutPanel8.Controls.Add(this.userPortShowHex, 0, 1);
this.tableLayoutPanel8.Dock = System.Windows.Forms.DockStyle.Fill;
this.tableLayoutPanel8.Location = new System.Drawing.Point(3, 3);
@ -459,18 +456,6 @@
this.userPortOpenCloseBtn.UseVisualStyleBackColor = true;
this.userPortOpenCloseBtn.Click += new System.EventHandler(this.userPortOpenCloseBtn_Click);
//
// userPortSelectionBox
//
this.userPortSelectionBox.Dock = System.Windows.Forms.DockStyle.Fill;
this.userPortSelectionBox.DropDownStyle = System.Windows.Forms.ComboBoxStyle.DropDownList;
this.userPortSelectionBox.Font = new System.Drawing.Font("宋体", 12F, System.Drawing.FontStyle.Regular, System.Drawing.GraphicsUnit.Point, ((byte)(134)));
this.userPortSelectionBox.FormattingEnabled = true;
this.userPortSelectionBox.Location = new System.Drawing.Point(3, 3);
this.userPortSelectionBox.Name = "userPortSelectionBox";
this.userPortSelectionBox.Size = new System.Drawing.Size(182, 28);
this.userPortSelectionBox.TabIndex = 0;
this.userPortSelectionBox.DropDown += new System.EventHandler(this.InitializeUserPort);
//
// userPortShowHex
//
this.userPortShowHex.AutoSize = true;
@ -498,11 +483,7 @@
this.serialPort.BaudRate = 115200;
this.serialPort.ReadTimeout = 50;
this.serialPort.WriteTimeout = 300;
//
// UserSerialPort
//
this.UserSerialPort.BaudRate = 115200;
this.UserSerialPort.DataReceived += new System.IO.Ports.SerialDataReceivedEventHandler(this.UserSerialPort_DataReceived);
this.serialPort.DataReceived += new System.IO.Ports.SerialDataReceivedEventHandler(this.serialPort_DataReceived);
//
// MainForm
//
@ -562,11 +543,9 @@
private System.Windows.Forms.TableLayoutPanel tableLayoutPanel7;
private System.Windows.Forms.TableLayoutPanel tableLayoutPanel8;
private System.Windows.Forms.Button userPortOpenCloseBtn;
private System.Windows.Forms.ComboBox userPortSelectionBox;
private System.Windows.Forms.TextBox userPortTextBox;
private System.Windows.Forms.Button userPortClearBtn;
private System.Windows.Forms.CheckBox userPortShowHex;
private System.IO.Ports.SerialPort UserSerialPort;
private System.Windows.Forms.Label UserPortRecvCountLabel;
}

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USTCRVSoC-tool-VS2012/USTCRVSoC-tool/MainForm.cs
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@ -29,7 +29,7 @@ namespace USTCRVSoC_tool
set
{
_userPortCount = value;
changeCountText( String.Format("接收: {0:D} B", _userPortCount) );
changeCountText(String.Format("接收: {0:D} B", _userPortCount));
}
}
@ -37,7 +37,6 @@ namespace USTCRVSoC_tool
{
InitializeComponent();
InitializeCurrentPort(null, null);
InitializeUserPort(null, null);
}
private void InitializeCurrentPort(object sender, EventArgs e)
@ -55,21 +54,6 @@ namespace USTCRVSoC_tool
}
}
private void InitializeUserPort(object sender, EventArgs e)
{
string[] ports = SerialPort.GetPortNames();
userPortSelectionBox.Items.Clear();
userPortSelectionBox.Items.AddRange(ports);
if (userPortSelectionBox.Items.Count > 0)
{
userPortSelectionBox.SelectedIndex = 0;
}
else
{
compilePromptText.Text = "未找到串口，请插入设备，或者检查串口驱动是否安装";
}
}
private void fileSelectionBtn_Click(object sender, EventArgs e)
{
OpenFileDialog openFileDialog = new OpenFileDialog();
@ -247,12 +231,17 @@ namespace USTCRVSoC_tool
{
StringBuilder strBuilder = new StringBuilder();
int index = 0;
foreach (string line in binText.Text.Split())
string[] lines = binText.Text.Trim().Split();
for (int idx = 0; idx < lines.Length; idx++)
{
string line = lines[idx];
string hex_num = line.Trim();
if (hex_num.Length <= 0)
continue;
strBuilder.Append(String.Format(" 32'h{1:S}, // 0x{0:x8}\n", index * 4, hex_num));
if (idx < lines.Length - 2)
strBuilder.Append(String.Format(" 32'h{1:S}, // 0x{0:x8}\n", index * 4, hex_num));
else
strBuilder.Append(String.Format(" 32'h{1:S} // 0x{0:x8}\n", index * 4, hex_num));
index += 1;
}
strBuilder.Insert(0, VerilogMid);
@ -297,39 +286,50 @@ namespace USTCRVSoC_tool
private bool serialSessionTry(string send, ref string response, string respectResponse, int try_time = 3)
{
for (int i = 0; i < try_time; i++)
if (serialSession(send, ref response, respectResponse))
return true;
if (serialSend(send))
if (serialRead(ref response, respectResponse))
return true;
compilePromptText.AppendText(" *** 串口调试多次尝试失败 ***\r\n");
return false;
}
private bool serialSession(string send, ref string response, string respectResponse)
private bool serialSend(string send)
{
compilePromptText.AppendText("send: " + send);
try
{
serialPort.Write(send + "\n");
response = serialPort.ReadLine().Trim();
}
catch (Exception ex)
{
compilePromptText.AppendText(" " + ex.Message + "\r\n");
return false;
}
if (response.Length > 0)
return true;
}
private bool serialRead(ref string response, string respectResponse)
{
try
{
bool is_respect = respectResponse.Equals("") || respectResponse.Equals(response);
if (is_respect)
compilePromptText.AppendText(" response: " + response + "\r\n");
else
compilePromptText.AppendText(" response: " + response + " (***不合预期***)\r\n");
return is_respect;
for (int i = 0; i < 8; i++)
{
response = serialPort.ReadLine().Trim();
bool is_respect = respectResponse.Equals("") || respectResponse.Equals(response);
if (is_respect)
{
compilePromptText.AppendText(" response: " + response + "\r\n");
return true;
}
}
}
else
catch (Exception ex)
{
compilePromptText.AppendText(" response: *** 超时 ***\r\n" + response);
compilePromptText.AppendText(" " + ex.Message + "\r\n");
return false;
}
compilePromptText.AppendText(" response: *** 超时 ***\r\n" + response);
return false;
}
private uint getBootAddr()
@ -352,17 +352,24 @@ namespace USTCRVSoC_tool
return;
}
if (serialPort.IsOpen)
serialPort.Close();
serialPort.PortName = portSelectionBox.Text;
try
if (!serialPort.IsOpen)
{
serialPort.Open();
serialPort.PortName = portSelectionBox.Text;
try
{
serialPort.Open();
}
catch (Exception ex)
{
compilePromptText.AppendText(" *** 打开串口出错 ***\r\n " + ex.Message);
refreshPortStatus();
return;
}
}
catch (Exception ex)
refreshPortStatus();
if (!serialSessionB("s", "debug"))
{
compilePromptText.AppendText(" *** 打开串口出错 ***\r\n " + ex.Message);
return;
}
@ -377,40 +384,43 @@ namespace USTCRVSoC_tool
if (!serialSessionB(send_str, "wr done"))
{
serialPort.Close();
return;
}
}
if (!serialSessionB(string.Format("r{0:x8}", boot_addr), "rst done"))
{
serialPort.Close();
return;
}
compilePromptText.AppendText(" *** 烧录成功 ***\r\n");
serialPort.Close();
}
private void userPortOpenCloseBtn_Click(object sender, EventArgs e)
{
if (UserSerialPort.IsOpen)
UserSerialPort.Close();
if (userPortOpenCloseBtn.Text == "打开")
{
UserSerialPort.PortName = userPortSelectionBox.Text;
serialPort.PortName = portSelectionBox.Text;
try
{
UserSerialPort.Open();
serialPort.Open();
userPortCount = 0;
}
catch (Exception ex)
{
compilePromptText.AppendText(" *** 打开串口出错 ***\r\n " + ex.Message);
return;
}
}
if (UserSerialPort.IsOpen)
else
{
serialPort.Close();
}
refreshPortStatus();
}
private void refreshPortStatus()
{
if (serialPort.IsOpen)
userPortOpenCloseBtn.Text = "关闭";
else
userPortOpenCloseBtn.Text = "打开";
@ -418,30 +428,6 @@ namespace USTCRVSoC_tool
public delegate void changeTextHandler(object str);
private void UserSerialPort_DataReceived(object sender, SerialDataReceivedEventArgs e)
{
SerialPort sp = (SerialPort)sender;
try
{
string recvdata = sp.ReadExisting();
if (userPortShowHex.Checked)
{
StringBuilder sb = new StringBuilder();
foreach (byte ch in recvdata)
{
sb.Append(String.Format("{0:X2} ", ch));
}
appendUserPortText(sb.ToString());
}
else
{
appendUserPortText(recvdata);
}
userPortCount += (uint)recvdata.Length;
}
catch{}
}
private void appendUserPortText(object str)
{
if (userPortTextBox.InvokeRequired == true)
@ -473,5 +459,29 @@ namespace USTCRVSoC_tool
{
userPortTextBox.Clear();
}
private void serialPort_DataReceived(object sender, System.IO.Ports.SerialDataReceivedEventArgs e)
{
SerialPort sp = (SerialPort)sender;
try
{
string recvdata = sp.ReadExisting();
if (userPortShowHex.Checked)
{
StringBuilder sb = new StringBuilder();
foreach (byte ch in recvdata)
{
sb.Append(String.Format("{0:X2} ", ch));
}
appendUserPortText(sb.ToString());
}
else
{
appendUserPortText(recvdata);
}
userPortCount += (uint)recvdata.Length;
}
catch { }
}
}
}

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USTCRVSoC-tool-VS2012/USTCRVSoC-tool/MainForm.resx
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@ -120,7 +120,4 @@
<metadata name="serialPort.TrayLocation" type="System.Drawing.Point, System.Drawing, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b03f5f7f11d50a3a">
<value>17, 17</value>
</metadata>
<metadata name="UserSerialPort.TrayLocation" type="System.Drawing.Point, System.Drawing, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b03f5f7f11d50a3a">
<value>139, 17</value>
</metadata>
</root>

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hardware/Quartus/DE0_Nano/DE0_Nano.qpf Normal file
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@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
# Date created = 10:11:55 February 10, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "10:11:55 February 10, 2019"
# Revisions
PROJECT_REVISION = "DE0_Nano"

275
hardware/Quartus/DE0_Nano/DE0_Nano.qsf Normal file
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@ -0,0 +1,275 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
# Date created = 10:11:56 February 10, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# DE0_Nano_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
#============================================================
# CLOCK
#============================================================
set_location_assignment PIN_R8 -to CLOCK_50
#============================================================
# LED
#============================================================
set_location_assignment PIN_A15 -to LED[0]
set_location_assignment PIN_A13 -to LED[1]
set_location_assignment PIN_B13 -to LED[2]
set_location_assignment PIN_A11 -to LED[3]
set_location_assignment PIN_D1 -to LED[4]
set_location_assignment PIN_F3 -to LED[5]
set_location_assignment PIN_B1 -to LED[6]
set_location_assignment PIN_L3 -to LED[7]
#============================================================
# KEY
#============================================================
set_location_assignment PIN_J15 -to KEY[0]
set_location_assignment PIN_E1 -to KEY[1]
#============================================================
# SW
#============================================================
set_location_assignment PIN_M1 -to SW[0]
set_location_assignment PIN_T8 -to SW[1]
set_location_assignment PIN_B9 -to SW[2]
set_location_assignment PIN_M15 -to SW[3]
#============================================================
# SDRAM
#============================================================
set_location_assignment PIN_M7 -to DRAM_BA[0]
set_location_assignment PIN_M6 -to DRAM_BA[1]
set_location_assignment PIN_R6 -to DRAM_DQM[0]
set_location_assignment PIN_T5 -to DRAM_DQM[1]
set_location_assignment PIN_L2 -to DRAM_RAS_N
set_location_assignment PIN_L1 -to DRAM_CAS_N
set_location_assignment PIN_L7 -to DRAM_CKE
set_location_assignment PIN_R4 -to DRAM_CLK
set_location_assignment PIN_C2 -to DRAM_WE_N
set_location_assignment PIN_P6 -to DRAM_CS_N
set_location_assignment PIN_G2 -to DRAM_DQ[0]
set_location_assignment PIN_G1 -to DRAM_DQ[1]
set_location_assignment PIN_L8 -to DRAM_DQ[2]
set_location_assignment PIN_K5 -to DRAM_DQ[3]
set_location_assignment PIN_K2 -to DRAM_DQ[4]
set_location_assignment PIN_J2 -to DRAM_DQ[5]
set_location_assignment PIN_J1 -to DRAM_DQ[6]
set_location_assignment PIN_R7 -to DRAM_DQ[7]
set_location_assignment PIN_T4 -to DRAM_DQ[8]
set_location_assignment PIN_T2 -to DRAM_DQ[9]
set_location_assignment PIN_T3 -to DRAM_DQ[10]
set_location_assignment PIN_R3 -to DRAM_DQ[11]
set_location_assignment PIN_R5 -to DRAM_DQ[12]
set_location_assignment PIN_P3 -to DRAM_DQ[13]
set_location_assignment PIN_N3 -to DRAM_DQ[14]
set_location_assignment PIN_K1 -to DRAM_DQ[15]
set_location_assignment PIN_P2 -to DRAM_ADDR[0]
set_location_assignment PIN_N5 -to DRAM_ADDR[1]
set_location_assignment PIN_N6 -to DRAM_ADDR[2]
set_location_assignment PIN_M8 -to DRAM_ADDR[3]
set_location_assignment PIN_P8 -to DRAM_ADDR[4]
set_location_assignment PIN_T7 -to DRAM_ADDR[5]
set_location_assignment PIN_N8 -to DRAM_ADDR[6]
set_location_assignment PIN_T6 -to DRAM_ADDR[7]
set_location_assignment PIN_R1 -to DRAM_ADDR[8]
set_location_assignment PIN_P1 -to DRAM_ADDR[9]
set_location_assignment PIN_N2 -to DRAM_ADDR[10]
set_location_assignment PIN_N1 -to DRAM_ADDR[11]
set_location_assignment PIN_L4 -to DRAM_ADDR[12]
#============================================================
# Accelerometer and EEPROM
#============================================================
set_location_assignment PIN_F2 -to I2C_SCLK
set_location_assignment PIN_F1 -to I2C_SDAT
set_location_assignment PIN_G5 -to G_SENSOR_CS_N
set_location_assignment PIN_M2 -to G_SENSOR_INT
#============================================================
# ADC
#============================================================
set_location_assignment PIN_A10 -to ADC_CS_N
set_location_assignment PIN_B10 -to ADC_SADDR
set_location_assignment PIN_B14 -to ADC_SCLK
set_location_assignment PIN_A9 -to ADC_SDAT
#============================================================
# 2x13 GPIO Header
#============================================================
set_location_assignment PIN_A14 -to GPIO_2[0]
set_location_assignment PIN_B16 -to GPIO_2[1]
set_location_assignment PIN_C14 -to GPIO_2[2]
set_location_assignment PIN_C16 -to GPIO_2[3]
set_location_assignment PIN_C15 -to GPIO_2[4]
set_location_assignment PIN_D16 -to GPIO_2[5]
set_location_assignment PIN_D15 -to GPIO_2[6]
set_location_assignment PIN_D14 -to GPIO_2[7]
set_location_assignment PIN_F15 -to GPIO_2[8]
set_location_assignment PIN_F16 -to GPIO_2[9]
set_location_assignment PIN_F14 -to GPIO_2[10]
set_location_assignment PIN_G16 -to GPIO_2[11]
set_location_assignment PIN_G15 -to GPIO_2[12]
set_location_assignment PIN_E15 -to GPIO_2_IN[0]
set_location_assignment PIN_E16 -to GPIO_2_IN[1]
set_location_assignment PIN_M16 -to GPIO_2_IN[2]
#============================================================
# GPIO_0, GPIO_0 connect to GPIO Default
#============================================================
set_location_assignment PIN_A8 -to GPIO_0_IN[0]
set_location_assignment PIN_D3 -to GPIO_0[0]
set_location_assignment PIN_B8 -to GPIO_0_IN[1]
set_location_assignment PIN_C3 -to GPIO_0[1]
set_location_assignment PIN_A2 -to GPIO_0[2]
set_location_assignment PIN_A3 -to GPIO_0[3]
set_location_assignment PIN_B3 -to GPIO_0[4]
set_location_assignment PIN_B4 -to GPIO_0[5]
set_location_assignment PIN_A4 -to GPIO_0[6]
set_location_assignment PIN_B5 -to GPIO_0[7]
set_location_assignment PIN_A5 -to GPIO_0[8]
set_location_assignment PIN_D5 -to GPIO_0[9]
set_location_assignment PIN_B6 -to GPIO_0[10]
set_location_assignment PIN_A6 -to GPIO_0[11]
set_location_assignment PIN_B7 -to GPIO_0[12]
set_location_assignment PIN_D6 -to GPIO_0[13]
set_location_assignment PIN_A7 -to GPIO_0[14]
set_location_assignment PIN_C6 -to GPIO_0[15]
set_location_assignment PIN_C8 -to GPIO_0[16]
set_location_assignment PIN_E6 -to GPIO_0[17]
set_location_assignment PIN_E7 -to GPIO_0[18]
set_location_assignment PIN_D8 -to GPIO_0[19]
set_location_assignment PIN_E8 -to GPIO_0[20]
set_location_assignment PIN_F8 -to GPIO_0[21]
set_location_assignment PIN_F9 -to GPIO_0[22]
set_location_assignment PIN_E9 -to GPIO_0[23]
set_location_assignment PIN_C9 -to GPIO_0[24]
set_location_assignment PIN_D9 -to GPIO_0[25]
set_location_assignment PIN_E11 -to GPIO_0[26]
set_location_assignment PIN_E10 -to GPIO_0[27]
set_location_assignment PIN_C11 -to GPIO_0[28]
set_location_assignment PIN_B11 -to GPIO_0[29]
set_location_assignment PIN_A12 -to GPIO_0[30]
set_location_assignment PIN_D11 -to GPIO_0[31]
set_location_assignment PIN_D12 -to GPIO_0[32]
set_location_assignment PIN_B12 -to GPIO_0[33]
#============================================================
# GPIO_1, GPIO_1 connect to GPIO Default
#============================================================
set_location_assignment PIN_T9 -to GPIO_1_IN[0]
set_location_assignment PIN_F13 -to GPIO_1[0]
set_location_assignment PIN_R9 -to GPIO_1_IN[1]
set_location_assignment PIN_T15 -to GPIO_1[1]
set_location_assignment PIN_T14 -to GPIO_1[2]
set_location_assignment PIN_T13 -to GPIO_1[3]
set_location_assignment PIN_R13 -to GPIO_1[4]
set_location_assignment PIN_T12 -to GPIO_1[5]
set_location_assignment PIN_R12 -to GPIO_1[6]
set_location_assignment PIN_T11 -to GPIO_1[7]
set_location_assignment PIN_T10 -to GPIO_1[8]
set_location_assignment PIN_R11 -to GPIO_1[9]
set_location_assignment PIN_P11 -to GPIO_1[10]
set_location_assignment PIN_R10 -to GPIO_1[11]
set_location_assignment PIN_N12 -to GPIO_1[12]
set_location_assignment PIN_P9 -to GPIO_1[13]
set_location_assignment PIN_N9 -to GPIO_1[14]
set_location_assignment PIN_N11 -to GPIO_1[15]
set_location_assignment PIN_L16 -to GPIO_1[16]
set_location_assignment PIN_K16 -to GPIO_1[17]
set_location_assignment PIN_R16 -to GPIO_1[18]
set_location_assignment PIN_L15 -to GPIO_1[19]
set_location_assignment PIN_P15 -to GPIO_1[20]
set_location_assignment PIN_P16 -to GPIO_1[21]
set_location_assignment PIN_R14 -to GPIO_1[22]
set_location_assignment PIN_N16 -to GPIO_1[23]
set_location_assignment PIN_N15 -to GPIO_1[24]
set_location_assignment PIN_P14 -to GPIO_1[25]
set_location_assignment PIN_L14 -to GPIO_1[26]
set_location_assignment PIN_N14 -to GPIO_1[27]
set_location_assignment PIN_M10 -to GPIO_1[28]
set_location_assignment PIN_L13 -to GPIO_1[29]
set_location_assignment PIN_J16 -to GPIO_1[30]
set_location_assignment PIN_K15 -to GPIO_1[31]
set_location_assignment PIN_J13 -to GPIO_1[32]
set_location_assignment PIN_J14 -to GPIO_1[33]
#============================================================
# End of pin assignments by Terasic System Builder
#============================================================
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C6
set_global_assignment -name TOP_LEVEL_ENTITY DE0_Nano_USTCRVSoC_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:11:55 FEBRUARY 10, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name SYSTEMVERILOG_FILE DE0_Nano_USTCRVSoC_top.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/soc_top.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/soc_top_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/naive_bus.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/naive_bus_router.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_top.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_regfile.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_id_stage.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_ex_branch_judge.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_bus_wrapper.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_alu.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/isp_uart.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/uart_tx_line.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/uart_rx.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/user_uart_tx.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/instr_rom.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/video_ram.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/ram_bus_wrapper.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/ram.sv
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

46
hardware/Quartus/DE0_Nano/DE0_Nano_USTCRVSoC_top.sv Normal file
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module DE0_Nano_USTCRVSoC_top(
//////////// CLOCK //////////
input CLOCK_50,
//////////// LED, KEY, Switch //////////
output [7:0] LED,
//////////// GPIO Header 1 //////////
input [1:0] GPIO_0_IN,
inout [33:0] GPIO_0,
input [1:0] GPIO_1_IN,
inout [33:0] GPIO_1
);
logic rst_n;
soc_top soc_inst(
.clk ( CLOCK_50 ),
.rst_n ( rst_n ),
.isp_uart_rx ( GPIO_1_IN[0] ),
.isp_uart_tx ( GPIO_1[0] ),
.vga_hsync ( GPIO_0[33] ),
.vga_vsync ( GPIO_0[32] ),
.vga_pixel ( GPIO_0[31:16] )
);
// 在开发板的LED上显示ISP-UART和USER-UART的发送灯和接收灯
assign LED[7:6] = ~{GPIO_1_IN[0],GPIO_1[0]};
// VGA GND
assign GPIO_0[12] = 1'b0;
// 流水灯，指示SoC在运行
reg [21:0] cnt = 22'h0;
reg [ 5:0] flow = 6'h0;
always @ (posedge CLOCK_50 or negedge rst_n)
if(~rst_n) begin
cnt <= 22'h0;
flow <= 6'h0;
end else begin
cnt <= cnt + 22'h1;
if(cnt==22'h0)
flow <= {flow[4:0], ~flow[5]};
end
assign LED[5:0] = flow;
endmodule

13
hardware/Quartus/DE0_Nano/output_files/DE0_Nano.cdf Normal file
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/* Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EP4CE22F17) Path("E:/work-Lab/USTCRVSoC/Quartus/DE0_Nano/output_files/") File("DE0_Nano.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

8
hardware/Quartus/DE0_Nano/output_files/DE0_Nano.jdi Normal file
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<sld_project_info>
<project>
<hash md5_digest_80b="82eae8375d05167e9fc9"/>
</project>
<file_info>
<file device="EP4CE22F17C6" path="DE0_Nano.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>

BIN
hardware/Quartus/DE0_Nano/output_files/DE0_Nano.jic Normal file
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Binary file not shown.

BIN
hardware/Quartus/DE0_Nano/output_files/DE0_Nano.sof Normal file
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Binary file not shown.

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hardware/RTL/core_alu.sv Normal file
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module core_alu(
input logic [ 6:0] i_opcode, i_funct7,
input logic [ 2:0] i_funct3,
input logic [31:0] i_num1u, i_num2u, i_immu,
output logic [31:0] o_res
);
logic [4:0] shamt_rs, shamt_imm;
logic [31:0] shifted;
logic signed [31:0] i_num1s, i_num2s, i_imms;
assign shamt_imm = i_immu[4:0];
assign shamt_rs = i_num2u[4:0];
assign i_num1s = i_num1u;
assign i_num2s = i_num2u;
assign i_imms = i_immu;
always_comb
casex({i_funct7,i_funct3,i_opcode})
// 算术类
17'b0000000_000_0110011 : o_res <= i_num1u + i_num2u; // ADD
17'bxxxxxxx_000_0010011 : o_res <= i_num1u + i_immu ; // ADDI
17'b0100000_000_0110011 : o_res <= i_num1u - i_num2u; // SUB
// LUI类
17'bxxxxxxx_xxx_0110111 : o_res <= i_immu; // LUI
// 逻辑类
17'b0000000_100_0110011 : o_res <= i_num1u ^ i_num2u; // XOR
17'bxxxxxxx_100_0010011 : o_res <= i_num1u ^ i_immu ; // XORI
17'b0000000_110_0110011 : o_res <= i_num1u | i_num2u; // OR
17'bxxxxxxx_110_0010011 : o_res <= i_num1u | i_immu ; // ORI
17'b0000000_111_0110011 : o_res <= i_num1u & i_num2u; // AND
17'bxxxxxxx_111_0010011 : o_res <= i_num1u & i_immu ; // ANDI
// 位移类
17'b0000000_001_0110011 : o_res <= i_num1u << shamt_rs ; // SLL
17'b0000000_001_0010011 : o_res <= i_num1u << shamt_imm; // SLLI
17'b0000000_101_0110011 : o_res <= i_num1u >> shamt_rs ; // SRL
17'b0000000_101_0010011 : o_res <= i_num1u >> shamt_imm; // SRL
17'b0100000_101_0110011 : o_res <= i_num1s >> shamt_rs ; // SRA
17'b0100000_101_0010011 : o_res <= i_num1s >> shamt_imm; // SRAI
// 比较类
17'b0000000_010_0110011 : o_res <= (i_num1s < i_num2s) ? 1 : 0; // SLT
17'bxxxxxxx_010_0010011 : o_res <= (i_num1s < i_imms ) ? 1 : 0; // SLTI
17'b0000000_011_0110011 : o_res <= (i_num1u < i_num2u) ? 1 : 0; // SLTU
17'bxxxxxxx_011_0010011 : o_res <= (i_num1u < i_immu ) ? 1 : 0; // SLTIU
// 无操作
default : o_res <= 0;
endcase
endmodule

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hardware/RTL/core_bus_wrapper.sv Normal file
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module core_bus_wrapper(
input logic clk, rst_n,
input logic i_re, i_we,
output logic o_conflict, o_conflict_latch,
input logic [ 2:0] i_funct3,
input logic [31:0] i_addr,
input logic [31:0] i_wdata,
output logic [31:0] o_rdata,
naive_bus.master bus_master
);
logic i_re_latch;
logic [1:0] addr_lsb, rd_addr_lsb;
logic [31:0] addr_bus, wdata, rdata, rdata_latch;
logic [2:0] rd_funct3;
logic [3:0] byte_enable;
assign addr_bus = {i_addr[31:2], 2'b0};
assign addr_lsb = i_addr[1:0];
assign o_conflict = (bus_master.rd_req & ~bus_master.rd_gnt) | (bus_master.wr_req & ~bus_master.wr_gnt);
assign bus_master.rd_req = i_re;
assign bus_master.rd_be = i_re ? byte_enable : 4'h0;
assign bus_master.rd_addr = i_re ? addr_bus : 0;
assign rdata = bus_master.rd_data;
assign bus_master.wr_req = i_we;
assign bus_master.wr_be = i_we ? byte_enable : 4'h0;
assign bus_master.wr_addr = i_we ? addr_bus : 0;
assign bus_master.wr_data = i_we ? wdata : 0;
always_comb
casex(i_funct3)
3'bx00 : if (addr_lsb==2'b00) byte_enable <= 4'b0001;
else if(addr_lsb==2'b01) byte_enable <= 4'b0010;
else if(addr_lsb==2'b10) byte_enable <= 4'b0100;
else byte_enable <= 4'b1000;
3'bx01 : if (addr_lsb==2'b00) byte_enable <= 4'b0011;
else if(addr_lsb==2'b10) byte_enable <= 4'b1100;
else byte_enable <= 4'b0000;
3'b010 : if (addr_lsb==2'b00) byte_enable <= 4'b1111;
else byte_enable <= 4'b0000;
default : byte_enable <= 4'b0000;
endcase
always_comb
case(i_funct3)
3'b000 : if (addr_lsb==2'b00) wdata <= {24'b0, i_wdata[7:0]};
else if(addr_lsb==2'b01) wdata <= {16'b0, i_wdata[7:0], 8'b0};
else if(addr_lsb==2'b10) wdata <= {8'b0, i_wdata[7:0], 16'b0};
else wdata <= {i_wdata[7:0], 24'b0};
3'b001 : if (addr_lsb==2'b00) wdata <= {16'b0, i_wdata[15:0]};
else if(addr_lsb==2'b10) wdata <= {i_wdata[15:0], 16'b0};
else wdata <= 0;
3'b010 : if (addr_lsb==2'b00) wdata <= i_wdata;
else wdata <= 0;
default : wdata <= 0;
endcase
always @ (posedge clk or negedge rst_n)
if(~rst_n) begin
i_re_latch <= 1'b0;
rd_addr_lsb <= 2'b0;
rd_funct3 <= 3'b0;
o_conflict_latch <= 1'b0;
rdata_latch <= 0;
end else begin
i_re_latch <= i_re;
rd_addr_lsb <= addr_lsb;
rd_funct3 <= i_funct3;
o_conflict_latch <= o_conflict;
rdata_latch <= o_rdata;
end
// assign o_rdata
always_comb
if(i_re_latch) begin
if(~o_conflict_latch)
case(rd_funct3)
3'b000 : if (rd_addr_lsb==2'b00) o_rdata <= {{24{rdata[ 7]}}, rdata[ 7: 0]};
else if(rd_addr_lsb==2'b01) o_rdata <= {{24{rdata[15]}}, rdata[15: 8]};
else if(rd_addr_lsb==2'b10) o_rdata <= {{24{rdata[23]}}, rdata[23:16]};
else o_rdata <= {{24{rdata[31]}}, rdata[31:24]};
3'b100 : if (rd_addr_lsb==2'b00) o_rdata <= { 24'b0, rdata[ 7: 0]};
else if(rd_addr_lsb==2'b01) o_rdata <= { 24'b0, rdata[15: 8]};
else if(rd_addr_lsb==2'b10) o_rdata <= { 24'b0, rdata[23:16]};
else o_rdata <= { 24'b0, rdata[31:24]};
3'b001 : if (rd_addr_lsb==2'b00) o_rdata <= {{16{rdata[15]}}, rdata[15: 0]};
else if(rd_addr_lsb==2'b10) o_rdata <= {{16{rdata[31]}}, rdata[31:16]};
else o_rdata <= 0;
3'b101 : if (rd_addr_lsb==2'b00) o_rdata <= { 16'b0, rdata[15: 0]};
else if(rd_addr_lsb==2'b10) o_rdata <= { 16'b0, rdata[31:16]};
else o_rdata <= 0;
3'b010 : if (rd_addr_lsb==2'b00) o_rdata <= rdata;
else o_rdata <= 0;
default : o_rdata <= 0;
endcase
else
o_rdata <= 0;
end else begin
o_rdata <= rdata_latch;
end
endmodule

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hardware/RTL/core_ex_branch_judge.sv Normal file
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module core_ex_branch_judge(
input logic i_branch,
input logic [31:0] i_num1u, i_num2u,
input logic [ 2:0] i_funct3,
output logic o_branch
);
logic branch_judge_res;
assign o_branch = i_branch & branch_judge_res;
logic signed [31:0] i_num1s, i_num2s;
assign i_num1s = i_num1u;
assign i_num2s = i_num2u;
always_comb
case(i_funct3)
3'b000 : branch_judge_res <= (i_num1u == i_num2u); // BEQ
3'b001 : branch_judge_res <= (i_num1u != i_num2u); // BNE
3'b100 : branch_judge_res <= (i_num1s < i_num2s); // BLT
3'b101 : branch_judge_res <= (i_num1s >= i_num2s); // BGE
3'b110 : branch_judge_res <= (i_num1u < i_num2u); // BLTU
3'b111 : branch_judge_res <= (i_num1u >= i_num2u); // BGEU
default: branch_judge_res <= 1'b0;
endcase
endmodule

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module core_id_stage(
input logic [31:0] i_instr,
input logic [31:0] i_pc,
output logic [ 4:0] o_rs1_addr, o_rs2_addr,
output logic o_rs1_en, o_rs2_en,
output logic o_jal, o_jalr, o_branch_may,
output logic o_nextpc2reg, o_alures2reg, o_memory2reg,
output logic o_mem_write,
output logic [31:0] o_pc_plus_imm, o_imm,
output logic [4:0] o_dst_reg_addr,
output logic [6:0] o_opcode, o_funct7,
output logic [2:0] o_funct3,
output logic [31:0] o_next_pc
);
logic [31:0] instr;
enum {UKNOWN_TYPE, R_TYPE, I_TYPE, IZ_TYPE, S_TYPE, B_TYPE, U_TYPE, J_TYPE} instr_type;
localparam OPCODE_JAL = 7'b1101111, // rd=pc+4, pc= pc+imm*2,
OPCODE_JALR = 7'b1100111, // rd=pc+4, pc= rs1+imm
OPCODE_BXXX = 7'b1100011, // conditional branch, pc= pc+imm*2,
OPCODE_LUI = 7'b0110111, // rd = imm;
OPCODE_ALI = 7'b0010011, // arithmetic and logical I-TYPE, rd=alu_res
OPCODE_ALR = 7'b0110011, // arithmetic and logical R-TYPE, rd=alu_res
OPCODE_LOAD = 7'b0000011, // load
OPCODE_STORE = 7'b0100011; // store
assign instr = i_instr;
assign o_next_pc = i_pc + 4;
assign o_pc_plus_imm = i_pc + o_imm;
assign {o_funct7, o_rs2_addr, o_rs1_addr, o_funct3, o_dst_reg_addr, o_opcode} = instr;
assign o_jal = (o_opcode == OPCODE_JAL );
assign o_jalr = (o_opcode == OPCODE_JALR );
assign o_branch_may = (o_opcode == OPCODE_BXXX );
assign o_nextpc2reg = (o_opcode == OPCODE_JAL || o_opcode == OPCODE_JALR );
assign o_alures2reg = (o_opcode == OPCODE_LUI || o_opcode == OPCODE_ALI || o_opcode == OPCODE_ALR);
assign o_memory2reg = (o_opcode == OPCODE_LOAD );
assign o_mem_write = (o_opcode == OPCODE_STORE);
// calculate instruction type
always_comb
case(o_opcode)
OPCODE_JAL : instr_type <= J_TYPE;
OPCODE_JALR : instr_type <= I_TYPE;
OPCODE_BXXX : instr_type <= B_TYPE;
OPCODE_LUI : instr_type <= U_TYPE;
OPCODE_ALI : instr_type <= (o_funct3==3'b011) ? IZ_TYPE : I_TYPE;
OPCODE_ALR : instr_type <= R_TYPE;
OPCODE_LOAD : instr_type <= I_TYPE;
OPCODE_STORE: instr_type <= S_TYPE;
default : instr_type <= UKNOWN_TYPE;
endcase
always_comb
case(instr_type)
I_TYPE : o_imm <= {{20{instr[31]}} , instr[31:20]};
IZ_TYPE: o_imm <= { 20'h0 , instr[31:20]};
S_TYPE : o_imm <= {{20{instr[31]}} , instr[31:25], instr[11:7]};
B_TYPE : o_imm <= {{20{instr[31]}} , instr[7], instr[30:25], instr[11:8], 1'b0};
U_TYPE : o_imm <= { instr[31:12] , 12'h0 };
J_TYPE : o_imm <= {{12{instr[31]}} , instr[19:12], instr[20], instr[30:21], 1'b0};
default: o_imm <= 0;
endcase
always_comb
case(instr_type)
R_TYPE : {o_rs2_en, o_rs1_en} <= 2'b11;
I_TYPE : {o_rs2_en, o_rs1_en} <= 2'b01;
IZ_TYPE: {o_rs2_en, o_rs1_en} <= 2'b01;
S_TYPE : {o_rs2_en, o_rs1_en} <= 2'b11;
B_TYPE : {o_rs2_en, o_rs1_en} <= 2'b11;
U_TYPE : {o_rs2_en, o_rs1_en} <= 2'b00;
J_TYPE : {o_rs2_en, o_rs1_en} <= 2'b00;
default: {o_rs2_en, o_rs1_en} <= 2'b00;
endcase
endmodule

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// Priority : Write Port 1 > Write Port 2 > Write Port 3
module core_regfile(
input logic clk, rst_n,
input logic rd_latch,
// Read port 1
input logic i_re1,
input logic [4:0] i_raddr1,
output logic [31:0] o_rdata1,
// Read port 2
input logic i_re2,
input logic [4:0] i_raddr2,
output logic [31:0] o_rdata2,
// Write port 1
input logic i_we1,
input logic [4:0] i_waddr1,
input logic [31:0] i_wdata1,
// Write port 2
input logic i_we2,
input logic [4:0] i_waddr2,
input logic [31:0] i_wdata2,
// Write port 3
input logic i_we3,
input logic [4:0] i_waddr3,
input logic [31:0] i_wdata3
);
logic [31:1] [31:0] reg_file_cell = 992'h0;
// handle regwrite
always @ (posedge clk or negedge rst_n) begin
if(~rst_n)
reg_file_cell <= 992'h0;
else begin
if(i_we3 && i_waddr3!=5'h0 && ~(i_we1 && i_waddr1==i_waddr3) && ~(i_we2 && i_waddr2==i_waddr3) )
reg_file_cell[i_waddr3] <= i_wdata3;
if(i_we2 && i_waddr2!=5'h0 && ~(i_we1 && i_waddr1==i_waddr2) )
reg_file_cell[i_waddr2] <= i_wdata2;
if(i_we1 && i_waddr1!=5'h0 )
reg_file_cell[i_waddr1] <= i_wdata1;
end
end
always @ (posedge clk or negedge rst_n) begin
if(~rst_n)
o_rdata1 <= 0;
else begin
if(rd_latch) begin
o_rdata1 <= o_rdata1;
end else if(i_re1 && i_raddr1!=5'h0) begin
if (i_we1 && i_raddr1==i_waddr1)
o_rdata1 <= i_wdata1;
else if(i_we2 && i_raddr1==i_waddr2)
o_rdata1 <= i_wdata2;
else if(i_we3 && i_raddr1==i_waddr3)
o_rdata1 <= i_wdata3;
else
o_rdata1 <= reg_file_cell[i_raddr1];
end else
o_rdata1 <= 0;
end
end
always @ (posedge clk or negedge rst_n) begin
if(~rst_n)
o_rdata2 <= 0;
else begin
if(rd_latch) begin
o_rdata2 <= o_rdata2;
end else if(i_re2 && i_raddr2!=5'h0) begin
if (i_we1 && i_raddr2==i_waddr1)
o_rdata2 <= i_wdata1;
else if(i_we2 && i_raddr2==i_waddr2)
o_rdata2 <= i_wdata2;
else if(i_we3 && i_raddr2==i_waddr3)
o_rdata2 <= i_wdata3;
else
o_rdata2 <= reg_file_cell[i_raddr2];
end else
o_rdata2 <= 0;
end
end
endmodule

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module core_top(
input logic clk, rst_n,
input logic [31:0] i_boot_addr,
naive_bus.master instr_master, data_master
);
// IF stage out
logic [31:0] if_pc;
// ID stage
logic [31:0] id_instr, id_pc;
logic id_rs1_en, id_rs2_en;
logic [4:0] id_rs1_addr, id_rs2_addr, id_dst_reg_addr;
logic [31:0] id_next_pc;
logic id_jal, id_jalr, id_branch_may;
logic id_nextpc2reg, id_alures2reg, id_memory2reg;
logic id_memwrite;
logic [6:0] id_opcode, id_funct7;
logic [2:0] id_funct3;
logic [31:0] id_pc_plus_imm, id_imm;
// EX stage
logic ex_jalr, ex_branch_may, ex_branch;
logic ex_nextpc2reg, ex_alures2reg, ex_memory2reg;
logic ex_memwrite;
logic [31:0] ex_s1, ex_s2;
logic [6:0] ex_opcode, ex_funct7;
logic [2:0] ex_funct3;
logic [31:0] ex_imm, ex_alu_res;
logic [4:0] ex_dst_reg_addr;
logic [31:0] ex_s1_plus_imm, ex_next_pc, ex_pc_plus_imm;
// MEM stage
logic [2:0] mem_funct3;
logic mem_memory2reg, mem_alures2reg, mem_memwrite;
logic [31:0] mem_alu_res, mem_mem_wdata, mem_s1_plus_imm;
logic [4:0] mem_dst_reg_addr;
// WB stage
logic wb_memory2reg;
logic [31:0] wb_reg_wdata;
logic [4:0] wb_dst_reg_addr;
// write regfile conflict signal
logic launch_nop, pc_stall, id_stall, ex_stall, mem_stall, wreg_conflict;
logic id_data_bus_conflict, mem_data_bus_conflict;
// -------------------------------------------------------------------------------
// conflict - comb logic
// -------------------------------------------------------------------------------
assign pc_stall = id_stall | id_data_bus_conflict;
assign id_stall = wreg_conflict;// | mem_data_bus_conflict;
assign ex_stall = mem_data_bus_conflict;
assign mem_stall = mem_data_bus_conflict;
assign launch_nop = ex_branch | ex_jalr | wreg_conflict;
assign wreg_conflict =
(id_rs1_en & ex_alures2reg & (id_rs1_addr== ex_dst_reg_addr) ) |
(id_rs2_en & ex_alures2reg & (id_rs2_addr== ex_dst_reg_addr) ) |
(id_rs1_en & ex_memory2reg & (id_rs1_addr== ex_dst_reg_addr) ) |
(id_rs2_en & ex_memory2reg & (id_rs2_addr== ex_dst_reg_addr) ) |
(id_rs1_en &mem_memory2reg & (id_rs1_addr==mem_dst_reg_addr) ) |
(id_rs2_en &mem_memory2reg & (id_rs2_addr==mem_dst_reg_addr) ) ;
// -------------------------------------------------------------------------------
// IF stage - comb logic
// -------------------------------------------------------------------------------
always_comb
if(ex_branch)
if_pc <= ex_pc_plus_imm;
else if(ex_jalr)
if_pc <= ex_s1_plus_imm;
else if(id_jal)
if_pc <= id_pc_plus_imm;
else if(pc_stall)
if_pc <= id_pc;
else
if_pc <= id_next_pc;
// -------------------------------------------------------------------------------
// IF-ID stage - timing logic
// -------------------------------------------------------------------------------
core_bus_wrapper inst_bus_wrap_inst(
.clk ( clk ),
.rst_n ( rst_n ),
.i_re ( ~id_stall ),
.i_we ( 1'b0 ),
.o_conflict_latch ( id_data_bus_conflict ),
.i_funct3 ( 3'b010 ),
.i_addr ( if_pc ),
.i_wdata ( 0 ),
.o_rdata ( id_instr ),
.bus_master ( instr_master )
);
always @ (posedge clk)
if(~rst_n)
id_pc <= {i_boot_addr[31:2],2'b00} - 4;
else
id_pc <= if_pc;
// -------------------------------------------------------------------------------
// ID stage - comb logic
// -------------------------------------------------------------------------------
core_id_stage core_id_stage_inst(
.i_instr ( id_instr ),
.i_pc ( id_pc ),
.o_rs1_addr ( id_rs1_addr ),
.o_rs2_addr ( id_rs2_addr ),
.o_rs1_en ( id_rs1_en ),
.o_rs2_en ( id_rs2_en ),
.o_jal ( id_jal ),
.o_jalr ( id_jalr ),
.o_branch_may ( id_branch_may ),
.o_nextpc2reg ( id_nextpc2reg ),
.o_alures2reg ( id_alures2reg ),
.o_memory2reg ( id_memory2reg ),
.o_mem_write ( id_memwrite ),
.o_pc_plus_imm ( id_pc_plus_imm ),
.o_imm ( id_imm ),
.o_dst_reg_addr ( id_dst_reg_addr),
.o_opcode ( id_opcode ),
.o_funct7 ( id_funct7 ),
.o_funct3 ( id_funct3 ),
.o_next_pc ( id_next_pc )
);
// -------------------------------------------------------------------------------
// ID-EX stage - timing logic
// -------------------------------------------------------------------------------
core_regfile core_regfile_inst(
.clk ( clk ),
.rst_n ( rst_n ),
.rd_latch ( ex_stall ),
.i_re1 ( id_rs1_en ),
.i_raddr1 ( id_rs1_addr ),
.o_rdata1 ( ex_s1 ),
.i_re2 ( id_rs2_en ),
.i_raddr2 ( id_rs2_addr ),
.o_rdata2 ( ex_s2 ),
.i_we1 ( ex_nextpc2reg ),
.i_waddr1 ( ex_dst_reg_addr),
.i_wdata1 ( ex_next_pc ),
.i_we2 ( mem_alures2reg ),
.i_waddr2 (mem_dst_reg_addr),
.i_wdata2 ( mem_alu_res ),
.i_we3 ( wb_memory2reg ),
.i_waddr3 ( wb_dst_reg_addr),
.i_wdata3 ( wb_reg_wdata )
);
always @ (posedge clk or negedge rst_n)
if(~rst_n) begin
ex_jalr <= 1'b0;
ex_branch_may <= 1'b0;
ex_nextpc2reg <= 1'b0;
ex_alures2reg <= 1'b0;
ex_memory2reg <= 1'b0;
ex_memwrite <= 1'b0;
ex_dst_reg_addr <= 5'h0;
ex_imm <= 0;
ex_opcode <= 7'h0;
ex_funct3 <= 3'h0;
ex_funct7 <= 7'h0;
ex_next_pc <= 0;
end else if(~ex_stall) begin
ex_jalr <= launch_nop ? 1'b0 : id_jalr;
ex_branch_may <= launch_nop ? 1'b0 : id_branch_may;
ex_pc_plus_imm <= id_pc_plus_imm;
ex_nextpc2reg <= launch_nop ? 1'b0 : id_nextpc2reg;
ex_alures2reg <= launch_nop ? 1'b0 : id_alures2reg;
ex_memory2reg <= launch_nop ? 1'b0 : id_memory2reg;
ex_memwrite <= launch_nop ? 1'b0 : id_memwrite;
ex_dst_reg_addr <= id_dst_reg_addr;
ex_imm <= id_imm;
ex_opcode <= id_opcode;
ex_funct3 <= id_funct3;
ex_funct7 <= id_funct7;
ex_next_pc <= id_next_pc;
end
// -------------------------------------------------------------------------------
// EX stage - comb logic
// -------------------------------------------------------------------------------
core_alu core_alu_inst(
.i_opcode ( ex_opcode ),
.i_funct7 ( ex_funct7 ),
.i_funct3 ( ex_funct3 ),
.i_num1u ( ex_s1 ),
.i_num2u ( ex_s2 ),
.i_immu ( ex_imm ),
.o_res ( ex_alu_res )
);
core_ex_branch_judge core_ex_branch_judge_inst(
.i_branch ( ex_branch_may ),
.i_num1u ( ex_s1 ),
.i_num2u ( ex_s2 ),
.i_funct3 ( ex_funct3 ),
.o_branch ( ex_branch )
);
assign ex_s1_plus_imm = ex_s1 + ex_imm;
// -------------------------------------------------------------------------------
// EX-MEM stage - timing logic
// -------------------------------------------------------------------------------
always @ (posedge clk or negedge rst_n)
if(~rst_n) begin
mem_memory2reg <= 1'b0;
mem_alures2reg <= 1'b0;
mem_alu_res <= 0;
mem_dst_reg_addr<= 5'h0;
mem_memwrite <= 1'b0;
mem_mem_wdata <= 0;
mem_s1_plus_imm <= 0;
mem_funct3 <= 3'b0;
end else if(~mem_stall) begin
mem_memory2reg <= ex_memory2reg;
mem_alures2reg <= ex_alures2reg;
mem_alu_res <= ex_alu_res;
mem_dst_reg_addr<= ex_dst_reg_addr;
mem_memwrite <= ex_memwrite;
mem_mem_wdata <= ex_s2;
mem_s1_plus_imm <= ex_s1_plus_imm;
mem_funct3 <= ex_funct3;
end
// -------------------------------------------------------------------------------
// MEM-WB stage - timing logic
// -------------------------------------------------------------------------------
core_bus_wrapper core_bus_wrapper_inst(
.clk ( clk ),
.rst_n ( rst_n ),
.i_re ( mem_memory2reg ),
.i_we ( mem_memwrite ),
.o_conflict ( mem_data_bus_conflict ),
.i_funct3 ( mem_funct3 ),
.i_addr ( mem_s1_plus_imm ),
.i_wdata ( mem_mem_wdata ),
.o_rdata ( wb_reg_wdata ),
.bus_master ( data_master )
);
always @ (posedge clk or negedge rst_n)
if(~rst_n) begin
wb_memory2reg <= 1'b0;
wb_dst_reg_addr <= 5'h0;
end else begin
wb_memory2reg <= mem_memory2reg;
wb_dst_reg_addr <= mem_dst_reg_addr;
end
endmodule

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module instr_rom(
input logic clk, rst_n,
naive_bus.slave bus
);
localparam INSTR_CNT = 30'd18;
wire [0:INSTR_CNT-1] [31:0] instr_rom_cell = {
32'h000062b3, // 0x00000000
32'h000302b7, // 0x00000004
32'h06806313, // 0x00000008
32'h00628023, // 0x0000000c
32'h06506313, // 0x00000010
32'h00628023, // 0x00000014
32'h06c06313, // 0x00000018
32'h00628023, // 0x0000001c
32'h06c06313, // 0x00000020
32'h00628023, // 0x00000024
32'h06f06313, // 0x00000028
32'h00628023, // 0x0000002c
32'h00a06313, // 0x00000030
32'h00628023, // 0x00000034
32'h00c003b7, // 0x00000038
32'hfff38393, // 0x0000003c
32'hfe039ee3, // 0x00000040
32'hfc5ff06f // 0x00000044
};
logic [29:0] cell_rd_addr;
assign bus.rd_gnt = bus.rd_req;
assign bus.wr_gnt = bus.wr_req;
assign cell_rd_addr = bus.rd_addr[31:2];
always @ (posedge clk or negedge rst_n)
if(~rst_n)
bus.rd_data <= 0;
else begin
if(bus.rd_req)
bus.rd_data <= (cell_rd_addr>=INSTR_CNT) ? 0 : instr_rom_cell[cell_rd_addr];
else
bus.rd_data <= 0;
end
endmodule

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// UART调试器
module isp_uart #(
parameter UART_RX_CLK_DIV = 108, // 50MHz/4/115200Hz=108
parameter UART_TX_CLK_DIV = 434 // 50MHz/1/115200Hz=434
)(
input logic clk,
input logic i_uart_rx,
output logic o_uart_tx,
output logic o_rst_n,
output logic [31:0] o_boot_addr,
naive_bus.master bus
);
logic [ 3:0] rst_chain = 4'b0;
logic rx_ready, rd_ok=1'b0, wr_ok=1'b0, tx_start=1'b0;
logic [ 7:0] rx_data, rx_binary;
logic [ 3:0] rx_binary_l;
logic [31:0] addr=0, wr_data=0;
logic [ 7:0][ 7:0] rd_data_ascii;
logic [ 7:0][ 7:0] tx_data = 64'h0;
enum {NEW, CMD, GETBOOTADDR, SETBOOTADDR, ADDR, EQUAL, DATA, FINAL, TRASH} fsm = NEW;
`define C (rx_data=="r")
`define S (rx_data==" " || rx_data=="\t" )
`define E (rx_data=="\n" || rx_data=="\r" )
`define N ( (rx_data>="0" && rx_data<="9" ) || (rx_data>="a" && rx_data<="f" ) )
initial o_boot_addr = 0;
assign o_rst_n = &rst_chain;
initial begin bus.rd_req = 1'b0; bus.wr_req = 1'b0; bus.rd_addr = 0; bus.wr_addr = 0; bus.wr_data = 0; end
assign bus.rd_be = 4'hf;
assign bus.wr_be = 4'hf;
assign rx_binary_l = rx_binary[3:0];
always_comb
if(rx_data>="0" && rx_data<="9" ) begin
rx_binary = rx_data - "0";
end else if(rx_data>="a" && rx_data<="f" ) begin
rx_binary = rx_data - "a" + 8'd10;
end else begin
rx_binary = 8'h0;
end
uart_rx #(
.UART_RX_CLK_DIV (UART_RX_CLK_DIV)
) uart_rx_inst (
.clk ( clk ),
.i_rx ( i_uart_rx ),
.o_ready ( rx_ready ),
.o_data ( rx_data )
);
uart_tx_line #(
.UART_TX_CLK_DIV (UART_TX_CLK_DIV)
) uart_tx_line_inst (
.clk ( clk ),
.o_tx ( o_uart_tx ),
.i_start ( tx_start ),
.i_data ( tx_data )
);
generate
genvar i;
for(i=0; i<8; i++) begin : convert_binary_to_ascii
always_comb
if(bus.rd_data[3+4*i:4*i]>4'h9)
rd_data_ascii[i] = "a" - 8'd10 + bus.rd_data[3+4*i:4*i];
else
rd_data_ascii[i] = "0" + bus.rd_data[3+4*i:4*i];
end
endgenerate
always @ (posedge clk)
rd_ok <= (bus.rd_req & bus.rd_gnt);
always @ (posedge clk)
wr_ok <= (bus.wr_req & bus.wr_gnt);
always @ (posedge clk)
if (rd_ok) begin
tx_start<= 1'b1;
tx_data <= rd_data_ascii;
end else if(wr_ok) begin
tx_start<= 1'b1;
tx_data <= "wr done ";
end else if(rx_ready && `E) begin
if(fsm==CMD) begin
tx_start<= 1'b1;
tx_data <= "rst done";
end else if(fsm==TRASH) begin
tx_start<= 1'b1;
tx_data <= "invalid ";
end
end else begin
tx_start<= 1'b0;
tx_data <= 64'h0;
end
always @ (posedge clk)
if(rx_ready && fsm==CMD && `E)
rst_chain <= 4'h0;
else
rst_chain <= {rst_chain[2:0],1'b1};
always @ (posedge clk)
if (bus.rd_req) begin
if(bus.rd_gnt)
bus.rd_req <= 1'b0;
end else if(bus.wr_req) begin
if(bus.wr_gnt)
bus.wr_req <= 1'b0;
end else if( rx_ready ) begin
case(fsm)
NEW : if (`C) begin
fsm <= CMD;
wr_data <= 0;
end else if(`S || `E) begin
fsm <= NEW;
addr <= 0;
wr_data <= 0;
end else if(`N) begin
fsm <= ADDR;
addr <= {addr[27:0], rx_binary_l}; // get a addr
end else begin
fsm <= TRASH;
end
CMD : if (`E) begin
o_boot_addr <= {wr_data[31:2],2'b00}; // 设置复位的boot地址，后两位截断(双字对齐)
fsm <= NEW; // cmd ok!
addr <= 0;
wr_data <= 0;
end else if(`S) begin
fsm <= CMD;
end else if(`N) begin
fsm <= CMD; // r字符后出现数字，说明该复位命令要指定boot地址，
wr_data <= {wr_data[27:0], rx_binary_l}; // get a data
end else begin
fsm <= TRASH;
end
ADDR : if (`E) begin
fsm <= NEW; // get a read command
bus.rd_req <= 1'b1; // TODO : launch a bus read
bus.rd_addr <= addr;
addr <= 0;
wr_data <= 0;
end else if(`N) begin
fsm <= ADDR;
addr <= {addr[27:0], rx_binary_l}; // get a addr
end else if(`S) begin
fsm <= EQUAL; // get addr down, waiting for data, maybe a write command
end else begin
fsm <= TRASH;
end
EQUAL : if (`E) begin
fsm <= NEW; // get a read command
bus.rd_req <= 1'b1; // TODO : launch a bus read
bus.rd_addr <= addr;
addr <= 0;
wr_data <= 0;
end else if(`N) begin
fsm <= DATA; // get a data
wr_data <= {wr_data[27:0], rx_binary_l}; // get a data
end else if(`S) begin
fsm <= EQUAL;
end else begin
fsm <= TRASH;
end
DATA : if (`E) begin
fsm <= NEW; // get a write command
bus.wr_req <= 1'b1; // TODO : launch a bus write
bus.wr_addr <= addr;
bus.wr_data <= wr_data;
addr <= 0;
wr_data <= 0;
end else if(`N) begin
fsm <= DATA; // get a data
wr_data <= {wr_data[27:0], rx_binary_l}; // get a data
end else if(`S) begin
fsm <= FINAL; // get data down, waiting for \r or \n
end else begin
fsm <= TRASH;
end
FINAL : if (`E) begin
fsm <= NEW; // get a write command
bus.wr_req <= 1'b1; // TODO : launch a bus write
bus.wr_addr <= addr;
bus.wr_data <= wr_data;
addr <= 0;
wr_data <= 0;
end else if(`S) begin
fsm <= FINAL; // get addr down, waiting for \r or \n
end else begin
fsm <= TRASH;
end
default : if (`E) begin
// get a syntax error
fsm <= NEW;
addr <= 0;
wr_data <= 0;
end else begin
fsm <= TRASH;
end
endcase
end
endmodule

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// UART
module isp_uart #(
parameter UART_RX_CLK_DIV = 108, // 50MHz/4/115200Hz=108
parameter UART_TX_CLK_DIV = 434 // 50MHz/1/115200Hz=434
)(
input logic clk,
input logic i_uart_rx,
output logic o_uart_tx,
output logic o_rst_n,
output logic [31:0] o_boot_addr,
naive_bus.master bus,
naive_bus.slave user_uart_bus
);
logic isp_uart_tx, user_uart_tx, isp_user_sel=1'b0;
logic uart_tx_line_fin;
logic [ 3:0] rst_chain = 4'b0;
logic rx_ready, rd_ok=1'b0, wr_ok=1'b0, tx_start=1'b0;
logic [ 7:0] rx_data, rx_data_raw, rx_binary;
logic [ 3:0] rx_binary_l;
logic [31:0] addr=0, wr_data=0;
logic [ 7:0][ 7:0] rd_data_ascii;
logic [ 7:0][ 7:0] tx_data = 64'h0;
enum {NEW, CMD,OPEN,CLOSE,ADDR, EQUAL, DATA, FINAL, TRASH} fsm = NEW;
enum {NONE, SELOPEN, SELCLOSE, RST} send_type = NONE;
`define C (rx_data=="r")
`define OP (rx_data=="o")
`define CL (rx_data=="s")
`define S (rx_data==" " || rx_data=="\t" )
`define E (rx_data=="\n" || rx_data=="\r" )
`define N ( (rx_data>="0" && rx_data<="9" ) || (rx_data>="a" && rx_data<="f" ) )
initial o_boot_addr = 0;
assign o_rst_n = &rst_chain;
assign o_uart_tx = isp_user_sel ? isp_uart_tx : user_uart_tx;
initial begin bus.rd_req = 1'b0; bus.wr_req = 1'b0; bus.rd_addr = 0; bus.wr_addr = 0; bus.wr_data = 0; end
assign bus.rd_be = 4'hf;
assign bus.wr_be = 4'hf;
assign rx_binary_l = rx_binary[3:0];
uart_rx #(
.UART_RX_CLK_DIV (UART_RX_CLK_DIV)
) uart_rx_inst (
.clk ( clk ),
.i_rx ( i_uart_rx ),
.o_ready ( rx_ready ),
.o_data ( rx_data_raw )
);
uart_tx_line #(
.UART_TX_CLK_DIV (UART_TX_CLK_DIV)
) uart_tx_line_inst (
.clk ( clk ),
.o_tx ( isp_uart_tx ),
.i_start ( tx_start ),
.o_fin ( uart_tx_line_fin ),
.i_data ( tx_data )
);
user_uart_tx #(
.UART_TX_CLK_DIV (UART_TX_CLK_DIV)
) user_uart_in_isp_inst (
.clk ( clk ),
.rst_n ( o_rst_n ),
.o_uart_tx ( user_uart_tx ),
.bus ( user_uart_bus )
);
always_comb // to lower case
if(rx_data_raw>="A" && rx_data_raw<="Z")
rx_data <= rx_data_raw | 8'b00100000;
else
rx_data <= rx_data_raw;
always_comb
if(rx_data>="0" && rx_data<="9" ) begin
rx_binary = rx_data - "0";
end else if(rx_data>="a" && rx_data<="f" ) begin
rx_binary = rx_data - "a" + 8'd10;
end else begin
rx_binary = 8'h0;
end
generate
genvar i;
for(i=0; i<8; i++) begin : convert_binary_to_ascii
always_comb
if(bus.rd_data[3+4*i:4*i]>4'h9)
rd_data_ascii[i] = "a" - 8'd10 + bus.rd_data[3+4*i:4*i];
else
rd_data_ascii[i] = "0" + bus.rd_data[3+4*i:4*i];
end
endgenerate
always @ (posedge clk)
rd_ok <= (bus.rd_req & bus.rd_gnt);
always @ (posedge clk)
wr_ok <= (bus.wr_req & bus.wr_gnt);
// uart send
always @ (posedge clk)
if (rd_ok) begin
tx_start<= 1'b1;
send_type <= NONE;
tx_data <= rd_data_ascii;
end else if(wr_ok) begin
tx_start<= 1'b1;
send_type <= NONE;
tx_data <= "wr done ";
end else if(rx_ready && `E) begin
if(fsm==CMD) begin
tx_start<= 1'b1;
send_type <= RST;
tx_data <= "rst done";
end else if(fsm==OPEN) begin
tx_start<= 1'b1;
send_type <= SELOPEN;
tx_data <= "user ";
end else if(fsm==CLOSE) begin
tx_start<= 1'b1;
send_type <= SELCLOSE;
tx_data <= "\r\ndebug ";
end else if(fsm==TRASH) begin
tx_start<= 1'b1;
send_type <= NONE;
tx_data <= "invalid ";
end
end else begin
tx_start<= 1'b0;
tx_data <= 64'h0;
end
always @ (posedge clk)
if(uart_tx_line_fin && send_type == RST)
rst_chain <= 4'h0;
else
rst_chain <= {rst_chain[2:0],1'b1};
always @ (posedge clk)
if(uart_tx_line_fin && (send_type == RST || send_type == SELOPEN) )
isp_user_sel <= 1'b0; // 切换到USER模式
else if(rx_ready && `E && (fsm==CLOSE) )
isp_user_sel <= 1'b1; // 切换到DEBUG模式
always @ (posedge clk)
if (bus.rd_req) begin
if(bus.rd_gnt)
bus.rd_req <= 1'b0;
end else if(bus.wr_req) begin
if(bus.wr_gnt)
bus.wr_req <= 1'b0;
end else if( rx_ready ) begin
case(fsm)
NEW : if (`C) begin
fsm <= CMD;
wr_data <= 0;
end else if(`OP) begin
fsm <= OPEN;
end else if(`CL) begin
fsm <= CLOSE;
end else if(`S || `E) begin
fsm <= NEW;
addr <= 0;
wr_data <= 0;
end else if(`N) begin
fsm <= ADDR;
addr <= {addr[27:0], rx_binary_l}; // get a addr
end else begin
fsm <= TRASH;
end
OPEN : if (`E) begin
fsm <= NEW; // cmd open ok!
end else if(`S) begin
fsm <= OPEN;
end else begin
fsm <= TRASH;
end
CLOSE : if (`E) begin
fsm <= NEW; // cmd close ok!
end else if(`S) begin
fsm <= CLOSE;
end else begin
fsm <= TRASH;
end
CMD : if (`E) begin
o_boot_addr <= {wr_data[31:2],2'b00}; // 设置复位的boot地址，后两位截断(双字对齐)
fsm <= NEW; // cmd ok!
addr <= 0;
wr_data <= 0;
end else if(`S) begin
fsm <= CMD;
end else if(`N) begin
fsm <= CMD; // r字符后出现数字，说明该复位命令要指定boot地址，
wr_data <= {wr_data[27:0], rx_binary_l}; // get a data
end else begin
fsm <= TRASH;
end
ADDR : if (`E) begin
fsm <= NEW; // get a read command
bus.rd_req <= 1'b1; // TODO : launch a bus read
bus.rd_addr <= addr;
addr <= 0;
wr_data <= 0;
end else if(`N) begin
fsm <= ADDR;
addr <= {addr[27:0], rx_binary_l}; // get a addr
end else if(`S) begin
fsm <= EQUAL; // get addr down, waiting for data, maybe a write command
end else begin
fsm <= TRASH;
end
EQUAL : if (`E) begin
fsm <= NEW; // get a read command
bus.rd_req <= 1'b1; // TODO : launch a bus read
bus.rd_addr <= addr;
addr <= 0;
wr_data <= 0;
end else if(`N) begin
fsm <= DATA; // get a data
wr_data <= {wr_data[27:0], rx_binary_l}; // get a data
end else if(`S) begin
fsm <= EQUAL;
end else begin
fsm <= TRASH;
end
DATA : if (`E) begin
fsm <= NEW; // get a write command
bus.wr_req <= 1'b1; // TODO : launch a bus write
bus.wr_addr <= addr;
bus.wr_data <= wr_data;
addr <= 0;
wr_data <= 0;
end else if(`N) begin
fsm <= DATA; // get a data
wr_data <= {wr_data[27:0], rx_binary_l}; // get a data
end else if(`S) begin
fsm <= FINAL; // get data down, waiting for \r or \n
end else begin
fsm <= TRASH;
end
FINAL : if (`E) begin
fsm <= NEW; // get a write command
bus.wr_req <= 1'b1; // TODO : launch a bus write
bus.wr_addr <= addr;
bus.wr_data <= wr_data;
addr <= 0;
wr_data <= 0;
end else if(`S) begin
fsm <= FINAL; // get addr down, waiting for \r or \n
end else begin
fsm <= TRASH;
end
default : if (`E) begin
// get a syntax error
fsm <= NEW;
addr <= 0;
wr_data <= 0;
end else begin
fsm <= TRASH;
end
endcase
end
endmodule

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`ifndef NAIVE_BUS_SV
`define NAIVE_BUS_SV
interface naive_bus();
// read interface
logic rd_req, rd_gnt;
logic [3:0] rd_be;
logic [31:0] rd_addr, rd_data;
// write interface
logic wr_req, wr_gnt;
logic [3:0] wr_be;
logic [31:0] wr_addr, wr_data;
modport master(
output rd_req, rd_be, rd_addr,
input rd_data, rd_gnt,
output wr_req, wr_be, wr_addr, wr_data,
input wr_gnt
);
modport slave(
input rd_req, rd_be, rd_addr,
output rd_data, rd_gnt,
input wr_req, wr_be, wr_addr, wr_data,
output wr_gnt
);
endinterface
`endif

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module naive_bus_router #(
parameter [7:0] N_MASTER = 2,
parameter [7:0] N_SLAVE = 3,
parameter [0:N_SLAVE-1][31:0] SLAVES_MASK = { 32'h0000_3fff , 32'h0000_3fff , 32'h0000_3fff },
parameter [0:N_SLAVE-1][31:0] SLAVES_BASE = { 32'h0000_0000 , 32'h0001_0000 , 32'h0002_0000 }
)(
input logic clk, rst_n,
naive_bus.slave masters [N_MASTER-1:0] ,
naive_bus.master slaves [ N_SLAVE-1:0]
);
`define SLAVE_ADDRESS(master_addr, slave_index) (master_addr) & ( SLAVES_MASK[slave_index] )
`define SLAVE_INRANGE(master_addr, slave_index) ( ((master_addr) & (~SLAVES_MASK[slave_index]))==(SLAVES_BASE[slave_index]) )
logic [N_MASTER-1:0] masters_rd_req;
logic [N_MASTER-1:0][ 3:0] masters_rd_be;
logic [N_MASTER-1:0][31:0] masters_rd_addr;
logic [N_MASTER-1:0] masters_wr_req;
logic [N_MASTER-1:0][ 3:0] masters_wr_be;
logic [N_MASTER-1:0][31:0] masters_wr_addr;
logic [N_MASTER-1:0][31:0] masters_wr_data;
logic [N_MASTER-1:0] masters_rd_gnt = 1'b0;
logic [N_MASTER-1:0][ 7:0] master_rd_slv_index = {N_MASTER{N_SLAVE}};
logic [N_MASTER-1:0][ 7:0] master_rd_slv_index_latch = {N_MASTER{N_SLAVE}};
logic [N_MASTER-1:0][ 7:0] slv = {N_MASTER{N_SLAVE}};
logic [N_SLAVE-1:0] slaves_wr_gnt, slaves_rd_gnt;
logic [N_SLAVE-1:0][ 7:0] mst = {N_SLAVE{N_MASTER}};
logic [N_SLAVE-1:0][ 7:0] slaves_wr_mst_index = {N_SLAVE{N_MASTER}};
logic [N_SLAVE-1:0][ 7:0] slaves_rd_mst_index = {N_SLAVE{N_MASTER}};
logic [N_SLAVE :0][31:0] slaves_rd_data;
assign slaves_rd_data[N_SLAVE] = 0;
generate
genvar slv_i_assign;
for(slv_i_assign=0; slv_i_assign<N_SLAVE; slv_i_assign++) begin: assign_slaves
assign slaves_wr_gnt[slv_i_assign] = slaves[slv_i_assign].wr_gnt;
assign slaves_rd_gnt[slv_i_assign] = slaves[slv_i_assign].rd_gnt;
assign slaves_rd_data[slv_i_assign]= slaves[slv_i_assign].rd_data;
end
endgenerate
generate
genvar mst_i_assign;
for(mst_i_assign=0; mst_i_assign<N_MASTER; mst_i_assign++) begin: assign_masters
assign masters_rd_req [mst_i_assign] = masters[mst_i_assign].rd_req;
assign masters_rd_be [mst_i_assign] = masters[mst_i_assign].rd_be;
assign masters_rd_addr[mst_i_assign] = masters[mst_i_assign].rd_addr;
assign masters_wr_req [mst_i_assign] = masters[mst_i_assign].wr_req;
assign masters_wr_be [mst_i_assign] = masters[mst_i_assign].wr_be;
assign masters_wr_addr[mst_i_assign] = masters[mst_i_assign].wr_addr;
assign masters_wr_data[mst_i_assign] = masters[mst_i_assign].wr_data;
assign masters[mst_i_assign].rd_gnt = masters_rd_gnt[mst_i_assign];
assign masters[mst_i_assign].rd_data = slaves_rd_data[master_rd_slv_index_latch[mst_i_assign]];
end
endgenerate
generate
genvar slv_i;
for(slv_i=0; slv_i<N_SLAVE; slv_i++) begin: generate_slave_loop
always_comb begin
slaves[slv_i].rd_req = 1'b0;
slaves[slv_i].rd_be = 4'h0;
slaves[slv_i].rd_addr = 0;
slaves_rd_mst_index[slv_i] = N_MASTER;
slaves[slv_i].wr_req = 1'b0;
slaves[slv_i].wr_be = 4'h0;
slaves[slv_i].wr_addr = 0;
slaves[slv_i].wr_data = 0;
slaves_wr_mst_index[slv_i] = N_MASTER;
for(mst[slv_i]=0; mst[slv_i]<N_MASTER; mst[slv_i]+=1) begin
if( `SLAVE_INRANGE(masters_rd_addr[mst[slv_i]], slv_i) & masters_rd_req[mst[slv_i]] ) begin
slaves[slv_i].rd_req = 1'b1;
slaves[slv_i].rd_be = masters_rd_be[mst[slv_i]];
slaves[slv_i].rd_addr = `SLAVE_ADDRESS(masters_rd_addr[mst[slv_i]], slv_i);
slaves_rd_mst_index[slv_i] = mst[slv_i];
end
if( `SLAVE_INRANGE(masters_wr_addr[mst[slv_i]], slv_i) & masters_wr_req[mst[slv_i]] ) begin
slaves[slv_i].wr_req = 1'b1;
slaves[slv_i].wr_be = masters_wr_be[mst[slv_i]];
slaves[slv_i].wr_addr = `SLAVE_ADDRESS(masters_wr_addr[mst[slv_i]], slv_i);
slaves[slv_i].wr_data = masters_wr_data[mst[slv_i]];
slaves_wr_mst_index[slv_i] = mst[slv_i];
end
end
end
end
endgenerate
generate
genvar mst_i;
for(mst_i=0; mst_i<N_MASTER; mst_i++) begin: generate_master_loop
always_comb begin
masters[mst_i].wr_gnt = 1'b1;
masters_rd_gnt[mst_i] = 1'b1;
master_rd_slv_index[mst_i] = N_SLAVE;
for(slv[mst_i]=0; slv[mst_i]<N_SLAVE; slv[mst_i]+=1) begin
if( `SLAVE_INRANGE(masters_rd_addr[mst_i], slv[mst_i]) ) begin
masters_rd_gnt[mst_i] = (slaves_rd_mst_index[slv[mst_i]]==mst_i) ? slaves_rd_gnt[slv[mst_i]] : 1'b0;
master_rd_slv_index[mst_i] = masters_rd_gnt[mst_i] ? slv[mst_i] : N_SLAVE;
end
if( `SLAVE_INRANGE(masters_wr_addr[mst_i], slv[mst_i]) ) begin
masters[mst_i].wr_gnt = (slaves_wr_mst_index[slv[mst_i]]==mst_i) ? slaves_wr_gnt[slv[mst_i]] : 1'b0;
end
end
end
end
endgenerate
always @ (posedge clk or negedge rst_n)
if(~rst_n)
master_rd_slv_index_latch <= {N_MASTER{N_SLAVE}};
else
master_rd_slv_index_latch <= master_rd_slv_index;
endmodule

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module ram( // 1024B
input logic clk,
input logic i_we,
input logic [ 9:0] i_waddr, i_raddr,
input logic [ 7:0] i_wdata,
output logic [ 7:0] o_rdata
);
initial o_rdata = 8'h0;
logic [7:0] data_ram_cell [0:1023] ;
always @ (posedge clk)
o_rdata <= data_ram_cell[i_raddr];
always @ (posedge clk)
if(i_we)
data_ram_cell[i_waddr] <= i_wdata;
endmodule

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module ram_bus_wrapper( // 4kB, valid address: 0x0000_0000 ~ 0x0000_0fff
input logic clk, rst_n,
naive_bus.slave bus
);
logic [9:0] cell_rd_addr, cell_wr_addr;
assign cell_rd_addr = bus.rd_addr[11:2];
assign cell_wr_addr = bus.wr_addr[11:2];
assign bus.rd_gnt = bus.rd_req;
assign bus.wr_gnt = bus.wr_req;
ram ram_block_inst_0(
.clk ( clk ),
.i_we ( bus.wr_req & bus.wr_be[0] ),
.i_waddr ( cell_wr_addr ),
.i_raddr ( cell_rd_addr ),
.i_wdata ( bus.wr_data[ 7: 0] ),
.o_rdata ( bus.rd_data[ 7: 0] )
);
ram ram_block_inst_1(
.clk ( clk ),
.i_we ( bus.wr_req & bus.wr_be[1] ),
.i_waddr ( cell_wr_addr ),
.i_raddr ( cell_rd_addr ),
.i_wdata ( bus.wr_data[15: 8] ),
.o_rdata ( bus.rd_data[15: 8] )
);
ram ram_block_inst_2(
.clk ( clk ),
.i_we ( bus.wr_req & bus.wr_be[2] ),
.i_waddr ( cell_wr_addr ),
.i_raddr ( cell_rd_addr ),
.i_wdata ( bus.wr_data[23:16] ),
.o_rdata ( bus.rd_data[23:16] )
);
ram ram_block_inst_3(
.clk ( clk ),
.i_we ( bus.wr_req & bus.wr_be[3] ),
.i_waddr ( cell_wr_addr ),
.i_raddr ( cell_rd_addr ),
.i_wdata ( bus.wr_data[31:24] ),
.o_rdata ( bus.rd_data[31:24] )
);
endmodule

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module soc_top #(
parameter UART_RX_CLK_DIV = 108, // 50MHz/4/115200Hz=108
parameter UART_TX_CLK_DIV = 434 // 50MHz/1/115200Hz=434
)(
// 时钟，要<EFBC8C><E8A681>?50MHz
input logic clk,
// 复位信号输出
output logic rst_n,
// 调试器UART信号
input logic isp_uart_rx,
output logic isp_uart_tx,
// 用户UART信号
// input logic user_uart_rx,
// output logic user_uart_tx,
// VGA显示输出信号
output logic vga_hsync, vga_vsync,
output logic [15:0] vga_pixel
);
logic [31:0] boot_addr;
naive_bus bus_masters[3]();
naive_bus bus_slaves[5]();
// <20><>?个能作为naive bus 主设备的调试<E8B083><E8AF95>?
// 它接收用户从UART发来的命令，操控复位等信号，或对总线进行读写。用户可以使用UART命令复位整个SoC，上传程序，或<EFBC8C>?<3F>查看运行时的RAM数据<E695B0><E68DAE>?
isp_uart #(
.UART_RX_CLK_DIV (UART_RX_CLK_DIV),
.UART_TX_CLK_DIV (UART_TX_CLK_DIV)
) isp_uart_inst(
.clk ( clk ),
.i_uart_rx ( isp_uart_rx ),
.o_uart_tx ( isp_uart_tx ),
.o_rst_n ( rst_n ),
.o_boot_addr ( boot_addr ),
.bus ( bus_masters[0] ),
.user_uart_bus ( bus_slaves[4] )
);
// RV32I <20><>?
core_top core_top_inst(
.clk ( clk ),
.rst_n ( rst_n ),
.i_boot_addr ( boot_addr ),
.instr_master ( bus_masters[1] ),
.data_master ( bus_masters[2] )
);
// 指令ROM
instr_rom instr_rom_inst(
.clk ( clk ),
.rst_n ( rst_n ),
.bus ( bus_slaves[0] )
);
// 指令RAM
ram_bus_wrapper instr_ram_inst(
.clk ( clk ),
.rst_n ( rst_n ),
.bus ( bus_slaves[1] )
);
// 数据RAM
ram_bus_wrapper data_ram_inst(
.clk ( clk ),
.rst_n ( rst_n ),
.bus ( bus_slaves[2] )
);
// 显存
video_ram video_ram_inst(
.clk ( clk ),
.rst_n ( rst_n ),
.bus ( bus_slaves[3] ),
.o_vsync ( vga_vsync ),
.o_hsync ( vga_hsync ),
.o_pixel ( vga_pixel )
);
// 3<><33>?5从<35>?<3F>线仲裁<E4BBB2><E8A381>?
//
// 主（越靠前优先级越高）：
// 0. UART调试<E8B083><E8AF95>?
// 1. Core Instr Master
// 2. Core Data Master
//
// 从：
// 1. 指令ROM<4F><4D>? 地址空间 00000000~00000fff
// 2. 指令RAM<41><4D>? 地址空间 00008000~00008fff
// 3. 数据RAM<41><4D>? 地址空间 00010000~00010fff
// 4. 显存RAM<41><4D>? 地址空间 00020000~00020fff
// 5. 用户UART，地<EFBC8C><E59CB0>?空间 00030000~00030003
naive_bus_router #(
.N_MASTER ( 3 ),
.N_SLAVE ( 5 ),
.SLAVES_MASK ( { 32'h0000_0003 , 32'h0000_0fff , 32'h0000_0fff , 32'h0000_0fff , 32'h0000_0fff } ),
.SLAVES_BASE ( { 32'h0003_0000 , 32'h0002_0000 , 32'h0001_0000 , 32'h0000_8000 , 32'h0000_0000 } )
) soc_bus_router_inst (
.clk ( clk ),
.rst_n ( rst_n ),
.masters ( bus_masters ),
.slaves ( bus_slaves )
);
endmodule

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module soc_top_tb();
logic clk, rst_n;
initial clk = 1'b1;
always #1 clk = ~clk;
wire vga_vsync, vga_hsync, user_uart_tx, isp_uart_tx;
wire [15:0] vga_pixel;
soc_top soc_inst(
.clk ( clk ),
.isp_uart_rx ( 1'b1 ),
.isp_uart_tx ( isp_uart_tx ),
.user_uart_rx ( 1'b1 ),
.user_uart_tx ( user_uart_tx),
.vga_hsync ( vga_hsync ),
.vga_vsync ( vga_vsync ),
.vga_pixel ( vga_pixel )
);
endmodule

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module uart_rx #(
parameter UART_RX_CLK_DIV = 108 // 50MHz/4/115200Hz=108
)(
input logic clk,
input logic i_rx,
output logic o_ready,
output logic [7:0] o_data
);
logic rx_bit, busy, last_busy=1'b0;
logic [ 5:0] shift = 6'h0, status = 6'h0;
logic [ 7:0] databuf = 8'h0;
logic [31:0] cnt = 0;
initial o_ready = 1'b0;
initial o_data = 8'h0;
assign busy = (status!=6'h0);
assign rx_bit = (shift[0]&shift[1]) | (shift[0]&i_rx) | (shift[1]&i_rx);
always @ (posedge clk)
last_busy <= busy;
always @ (posedge clk)
o_ready <= (~busy & last_busy);
always @ (posedge clk)
cnt <= (cnt<UART_RX_CLK_DIV-1) ? cnt+1 : 0;
always @ (posedge clk)
if(cnt==0) begin
if(~busy) begin
if(shift == 6'b111000)
status <= 6'h1;
end else begin
if(status[5] == 1'b0) begin
if(status[1:0] == 2'b11)
databuf <= {rx_bit, databuf[7:1]};
status <= status + 6'h1;
end else begin
if(status<62) begin
status <= 6'd62;
o_data <= databuf;
end else begin
status <= status + 6'd1;
end
end
end
shift <= shift<<1;
shift[0] <= i_rx;
end
endmodule

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module uart_tx_line #(
parameter UART_TX_CLK_DIV = 434 // 50MHz/1/115200Hz=434
)(
input logic clk,
output logic o_tx,
input logic i_start,
output logic o_fin,
input logic [7:0][7:0] i_data
);
logic [31:0] cnt = 0;
logic [ 6:0] tx_cnt = 0;
logic busy, busy_latch;
logic [99:0] tx_buffer, tx_shift;
initial tx_shift = 91'h0;
initial o_tx = 1'b1;
initial o_fin = 1'b0;
assign busy = tx_cnt>7'd0;
always @ (posedge clk)
busy_latch <= busy;
assign tx_buffer = {2'b11, 8'h0A , // 0x0A = \n , a end of line
2'b01, i_data[0],
2'b01, i_data[1],
2'b01, i_data[2],
2'b01, i_data[3],
2'b01, i_data[4],
2'b01, i_data[5],
2'b01, i_data[6],
2'b01, i_data[7],
2'b01, 8'b11111111 };
always @ (posedge clk)
cnt <= (cnt<UART_TX_CLK_DIV-1) ? cnt+1 : 0;
always @ (posedge clk)
if(busy) begin
if(cnt==0) begin
{tx_shift, o_tx} <= {1'b1, tx_shift};
tx_cnt <= tx_cnt - 7'd1;
end
end else begin
o_tx <= 1'b1;
if(i_start) begin
tx_cnt <= 7'd110;
tx_shift <= tx_buffer;
end else begin
tx_cnt <= 7'd0;
end
end
always @ (posedge clk)
o_fin <= (busy_latch & ~busy);
endmodule

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module user_uart_tx #(
parameter UART_TX_CLK_DIV = 434 // 50MHz/1/115200Hz=434
)(
input logic clk, rst_n,
output logic o_uart_tx,
naive_bus.slave bus
);
localparam TX_CNT = 5'd19;
logic [ 9:0] fifo_rd_pointer=10'h0, fifo_wr_pointer=10'h0, fifo_len;
logic fifo_full, fifo_empty;
logic rd_addr_valid, wr_addr_valid;
logic [31:0] cnt = 0;
logic [ 4:0] tx_cnt = 0;
logic [ 7:0] tx_shift = 8'h0;
logic [ 7:0] fifo_rd_data;
initial o_uart_tx = 1'b1;
assign rd_addr_valid = (bus.rd_addr[31:2] == 30'h0);
assign wr_addr_valid = (bus.wr_addr[31:2] == 30'h0);
assign fifo_len = fifo_wr_pointer - fifo_rd_pointer;
assign fifo_empty = (fifo_len==10'h000);
assign fifo_full = (fifo_len==10'h3ff);
assign bus.rd_gnt = bus.rd_req;
always @ (posedge clk or negedge rst_n)
if(~rst_n)
bus.rd_data <= 0;
else begin
if(bus.rd_req & rd_addr_valid)
bus.rd_data <= {22'h0, fifo_len};
else
bus.rd_data <= 0;
end
always_comb
if(bus.wr_req) begin
if(wr_addr_valid && bus.wr_be[0]) begin
bus.wr_gnt <= ~fifo_full;
end else begin
bus.wr_gnt <= 1'b1;
end
end else begin
bus.wr_gnt <= 1'b0;
end
always @ (posedge clk or negedge rst_n)
if(~rst_n) begin
fifo_wr_pointer <= 10'h0;
end else begin
if(bus.wr_req & wr_addr_valid & bus.wr_be[0] & ~fifo_full) begin
fifo_wr_pointer <= fifo_wr_pointer + 10'h1;
end
end
always @ (posedge clk or negedge rst_n)
if(~rst_n)
cnt <= 0;
else
cnt <= (cnt<UART_TX_CLK_DIV-1) ? cnt+1 : 0;
always @ (posedge clk or negedge rst_n)
if(~rst_n) begin
fifo_rd_pointer <= 10'h0;
o_uart_tx <= 1'b1;
tx_shift <= 8'h00;
tx_cnt <= 5'h0;
end else begin
if(tx_cnt>5'd0) begin
if(cnt==0) begin
if(tx_cnt==TX_CNT) begin
{tx_shift, o_uart_tx} <= ~{fifo_rd_data, 1'b1};
fifo_rd_pointer <= fifo_rd_pointer + 10'h1;
end else begin
{tx_shift, o_uart_tx} <= {1'b0, tx_shift[7:1], ~tx_shift[0]};
end
tx_cnt <= tx_cnt - 5'd1;
end
end else begin
o_uart_tx <= 1'b1;
tx_cnt <= fifo_empty ? 5'd0 : TX_CNT;
end
end
ram ram_for_uart_tx_fifo_inst(
.clk ( clk ),
.i_we ( bus.wr_req & wr_addr_valid & bus.wr_be[0] & ~fifo_full ),
.i_waddr ( fifo_wr_pointer ),
.i_wdata ( bus.wr_data[7:0] ),
.i_raddr ( fifo_rd_pointer ),
.o_rdata ( fifo_rd_data )
);
endmodule

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module video_ram(
input logic clk, rst_n,
output logic o_hsync, o_vsync,
output logic [15:0] o_pixel,
naive_bus.slave bus
);
logic [ 9:0] vga_addr_h;
logic [ 1:0] vga_addr_l, vga_addr_l_latch = 2'b00;
logic [ 7:0] vga_ascii;
logic [ 9:0] cell_wr_addr;
logic [ 7:0] vga_rdata [4];
assign cell_wr_addr = bus.wr_addr[11:2];
assign bus.rd_gnt = bus.rd_req;
assign bus.wr_gnt = bus.wr_req;
assign bus.rd_data = 0;
always @ (posedge clk or negedge rst_n)
if(~rst_n)
vga_addr_l_latch <= 2'b00;
else
vga_addr_l_latch <= vga_addr_l;
ram ram_block_inst_0(
.clk ( clk ),
.i_we ( bus.wr_req & bus.wr_be[0] ),
.i_waddr ( cell_wr_addr ),
.i_wdata ( bus.wr_data[ 7: 0] ),
.i_raddr ( vga_addr_h ),
.o_rdata ( vga_rdata[0] )
);
ram ram_block_inst_1(
.clk ( clk ),
.i_we ( bus.wr_req & bus.wr_be[1] ),
.i_waddr ( cell_wr_addr ),
.i_wdata ( bus.wr_data[15: 8] ),
.i_raddr ( vga_addr_h ),
.o_rdata ( vga_rdata[1] )
);
ram ram_block_inst_2(
.clk ( clk ),
.i_we ( bus.wr_req & bus.wr_be[2] ),
.i_waddr ( cell_wr_addr ),
.i_wdata ( bus.wr_data[23:16] ),
.i_raddr ( vga_addr_h ),
.o_rdata ( vga_rdata[2] )
);
ram ram_block_inst_3(
.clk ( clk ),
.i_we ( bus.wr_req & bus.wr_be[3] ),
.i_waddr ( cell_wr_addr ),
.i_wdata ( bus.wr_data[31:24] ),
.i_raddr ( vga_addr_h ),
.o_rdata ( vga_rdata[3] )
);
always_comb
case(vga_addr_l_latch)
2'b00 : vga_ascii <= vga_rdata[0];
2'b01 : vga_ascii <= vga_rdata[1];
2'b10 : vga_ascii <= vga_rdata[2];
2'b11 : vga_ascii <= vga_rdata[3];
endcase
vgaChar98x36 vga_char_inst(
.clk ( clk ),
.rst_n ( rst_n ),
.hsync ( o_hsync ),
.vsync ( o_vsync ),
.pixel ( o_pixel ),
.addr ( {vga_addr_h,vga_addr_l} ),
.ascii ( vga_ascii )
);
endmodule
module vgaChar98x36(
// clock
input clk, rst_n,
// vga interfaces
output hsync, vsync,
output [15:0] pixel,
// user interface
output [11:0] addr,
input [7:0] ascii
);
wire b;
wire [15:0] req_pixel;
reg [15:0] border, border_latch;
wire req;
wire [2:0] x_l;
wire [3:0] y_l;
wire [6:0] x_h;
wire [5:0] y_h;
wire [9:0] x, y;
reg [9:0] x_latch, y_latch;
always @ (posedge clk) begin
x_latch <= x;
y_latch <= y;
border_latch <= border;
end
assign {x_h, x_l} = x - 10'd8;
assign {y_h, y_l} = y - 10'd12;
assign addr = y_h * 12'd98 + x_h;
vga vga_inst(
.clk (clk),
.hsync (hsync),
.vsync (vsync),
.pixel (pixel),
.req (req),
.x (x),
.y (y),
.req_pixel (req_pixel)
);
assign req_pixel = ( x_latch>=8 && x_latch<(800-8) && y_latch>=12 && y_latch<(600-12) ) ? {16{b}} : border_latch;
always @ (posedge clk)
if(req)
border <= ( x<5 || x>(800-5) || y<5 || y>(600-5) ) ? 16'hff00 : 16'h0000;
char8x16_rom char_8x16_rom_inst(
.clk ( clk ),
.rst_n ( rst_n ),
.ascii ( ascii ),
.x ( x_l ),
.y ( y_l ),
.b ( b )
);
endmodule
module vga(
// clock
input clk,
// vga interface
output reg hsync, vsync,
output reg [15:0] pixel,
// user interface
output req,
output [ 9:0] x, y,
input [15:0] req_pixel
);
localparam H_END = 800,
H_SYNCSTART = H_END + 8,
H_SYNCEND = H_SYNCSTART + 128,
H_PERIOD = H_SYNCEND + 72,
V_END = 600,
V_SYNCSTART = V_END + 8,
V_SYNCEND = V_SYNCSTART + 4,
V_PERIOD = V_SYNCEND + 36;
reg [31:0] hcnt,vcnt;
always @ (posedge clk)
hcnt <= (hcnt<H_PERIOD) ? hcnt + 1 : 0;
always @ (posedge clk)
hsync <= ~(hcnt>=H_SYNCSTART && hcnt<H_SYNCEND);
always @ (posedge hsync)
vcnt <= (vcnt<V_PERIOD) ? vcnt + 1 : 0;
always @ (posedge hsync)
vsync <= ~(vcnt>=V_SYNCSTART && vcnt<V_SYNCEND);
wire h_range = hcnt<H_END;
wire v_range = vcnt<V_END;
wire range = (h_range & v_range);
assign x = range ? hcnt[9:0] : 10'h0;
assign y = range ? vcnt[9:0] : 10'h0;
assign req = range;
always @ (posedge clk)
pixel <= (hcnt>0 && hcnt<=H_END && v_range) ? req_pixel : 16'h0;
endmodule
// 存放所有ASCII字符的字码
// 该ROM自动综合成Block RAM
module char8x16_rom(
input clk, rst_n,
input [7:0] ascii,
input [2:0] x,
input [3:0] y,
output b
);
reg [ 6:0] addr = 7'h0;
reg [127:0] ch = 128'h0;
always @ (posedge clk or negedge rst_n)
if(~rst_n)
addr <= 7'h0;
else
addr <= ~{y,x};
assign b = ch[addr];
always @ (posedge clk or negedge rst_n)
if(~rst_n)
ch <= 128'h0;
else
case(ascii)
33: ch <= 128'h00000018181818181808000818000000; //!0
34: ch <= 128'h00000034242424000000000000000000; //"1
35: ch <= 128'h0000000016247F2424247E2424000000; //#2
36: ch <= 128'h000000083E6848681C1612127C101000; //$3
37: ch <= 128'h00000061D296740810162949C6000000; //%4
38: ch <= 128'h000000003C646438724ACE467F000000; //&5
39: ch <= 128'h00000018181818000000000000000000; //'6
40: ch <= 128'h00000004081810303030301010180C04; //(7
41: ch <= 128'h000000201008080C0404040C08181020; //)8
42: ch <= 128'h000000080A341C6A0800000000000000; //*9
43: ch <= 128'h0000000000001818187F181818000000; //+10
44: ch <= 128'h00000000000000000000001818083000; //,11
45: ch <= 128'h0000000000000000003C000000000000; //-12
46: ch <= 128'h00000000000000000000001818000000; //.13
47: ch <= 128'h0000000206040C080810102020400000; ///14
48: ch <= 128'h000000003C6642475B7342663C000000; //015
49: ch <= 128'h0000000018784808080808087E000000; //116
50: ch <= 128'h000000003C460606040810207E000000; //217
51: ch <= 128'h000000007C0606043C0202067C000000; //318
52: ch <= 128'h000000000C1C14246444FF0404000000; //419
53: ch <= 128'h000000007E6060607E0202067C000000; //520
54: ch <= 128'h000000001E306048764242623C000000; //621
55: ch <= 128'h000000007E0206040C08181030000000; //722
56: ch <= 128'h000000003C6242361C6642423C000000; //823
57: ch <= 128'h000000003C664242661A020478000000; //924
58: ch <= 128'h00000000000018180000001818000000; //:25
59: ch <= 128'h00000000000018180000001818083000; //;26
60: ch <= 128'h00000000000004183060100C06000000; //<27
61: ch <= 128'h00000000000000007E007E0000000000; //=28
62: ch <= 128'h000000000000301804060C1020000000; //>29
63: ch <= 128'h000000301C0606061810001010000000; //?30
64: ch <= 128'h0000001C224141DDB5A5A5AF94C0403C; //@31
65: ch <= 128'h00000000181C342426627E43C1000000; //A32
66: ch <= 128'h000000007C4642467C4242427C000000; //B33
67: ch <= 128'h000000001E204040404040603E000000; //C34
68: ch <= 128'h000000007C4642434343424678000000; //D35
69: ch <= 128'h000000007E6060607E6060607E000000; //E36
70: ch <= 128'h000000007E6060607E60606060000000; //F37
71: ch <= 128'h000000001E604040CE4242623E000000; //G38
72: ch <= 128'h00000000424242427E42424242000000; //H39
73: ch <= 128'h000000007E181818181818187E000000; //I40
74: ch <= 128'h000000007C0404040404044478000000; //J41
75: ch <= 128'h000000004244485070584C4442000000; //K42
76: ch <= 128'h0000000020202020202020203E000000; //L43
77: ch <= 128'h000000006266675F5B5BC1C1C1000000; //M44
78: ch <= 128'h00000000626272525A4A4E4646000000; //N45
79: ch <= 128'h000000003C6243C3C3C343623C000000; //O46
80: ch <= 128'h000000007C4642424678404040000000; //P47
81: ch <= 128'h000000003C6243C3C3C343623C180F00; //Q48
82: ch <= 128'h000000007C6662667C6C646662000000; //R49
83: ch <= 128'h000000003E6040601C0602027C000000; //S50
84: ch <= 128'h000000007F1818181818181818000000; //T51
85: ch <= 128'h0000000042424242424242623C000000; //U52
86: ch <= 128'h00000000C14342622624341C18000000; //V53
87: ch <= 128'h00000000C1C141495B5B766666000000; //W54
88: ch <= 128'h0000000043663418181C2466C3000000; //X55
89: ch <= 128'h00000000C14266341C18181818000000; //Y56
90: ch <= 128'h000000007E02040C181020607E000000; //Z57
91: ch <= 128'h0000001C10101010101010101010101C; //[58
92: ch <= 128'h000000402020101008080C0406020000; //\59
93: ch <= 128'h0000003C0C0C0C0C0C0C0C0C0C0C0C3C; //]60
94: ch <= 128'h00000000181C24620000000000000000; //^61
95: ch <= 128'h000000000000000000000000000000FF; //_62
96: ch <= 128'h00000020100000000000000000000000; //`63
97: ch <= 128'h0000000000003C06023E42467A000000; //a64
98: ch <= 128'h0000004040405C62424242427C000000; //b65
99: ch <= 128'h0000000000001E20604060203E000000; //c66
100: ch <= 128'h0000000202023E62424242663A000000; //d67
101: ch <= 128'h0000000000003C62427E40603E000000; //e68
102: ch <= 128'h0000000F1810107E1010101010000000; //f69
103: ch <= 128'h0000000000003F66426658403E43423C; //g70
104: ch <= 128'h0000004040405C624242424242000000; //h71
105: ch <= 128'h0000001818007808080808087E000000; //i72
106: ch <= 128'h000000040C007C040404040404040C78; //j73
107: ch <= 128'h000000606060626C7870686462000000; //k74
108: ch <= 128'h0000007808080808080808087E000000; //l75
109: ch <= 128'h000000000000764B4B4B4B4B4B000000; //m76
110: ch <= 128'h0000000000005C624242424242000000; //n77
111: ch <= 128'h0000000000003C62424342623C000000; //o78
112: ch <= 128'h0000000000005C62424242427C404040; //p79
113: ch <= 128'h0000000000003E62424242663A020202; //q80
114: ch <= 128'h0000000000006E726360606060000000; //r81
115: ch <= 128'h0000000000003E20203C06027C000000; //s82
116: ch <= 128'h000000001010FE10101010101E000000; //t83
117: ch <= 128'h0000000000004242424242663A000000; //u84
118: ch <= 128'h00000000000043426624341818000000; //v85
119: ch <= 128'h000000000000C1C15B5A5E6666000000; //w86
120: ch <= 128'h00000000000062261C181C2662000000; //x87
121: ch <= 128'h00000000000043426624341C181830E0; //y88
122: ch <= 128'h0000000000007E060C1810207E000000; //z89
123: ch <= 128'h0000000E18101010307010101010180E; //{90
124: ch <= 128'h00000808080808080808080808080808; //|91
125: ch <= 128'h00000030180808080C0E080808081830; //}92
126: ch <= 128'h0000000000000000714B060000000000; //~93
default ch <= 128'h0;
endcase
endmodule

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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:33:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3136:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7265747265657461626c6570616e656c5f636f72655f747265655f7461626c65:33:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:637265617465636f6e73747261696e747366696c6570616e656c5f66696c655f6e616d65:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f74797065:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:313037:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3133:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:37:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6970636f7265766965775f7461626265645f70616e65:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c6f676d6f6e69746f725f6d6f6e69746f72:33:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f68656c70:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746f6f6c73:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f76696577:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f77696e646f77:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e746f6f6c6261726d67725f72756e:38:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e77696e6d656e756d67725f6c61796f7574:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d657373616765776974686f7074696f6e6469616c6f675f646f6e745f73686f775f746869735f6469616c6f675f616761696e:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f7365766572697479:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:3431:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f637269746963616c5f7761726e696e6773:35:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f7761726e696e675f6d65737361676573:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e65746c69737474726565766965775f6e65746c6973745f74726565:3131:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:36:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:3133:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6c6963656e73655f6d616e616765:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7265706f7274735f77696e646f77:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f62697467656e:38:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f73796e746865736973:36:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7365745f61735f746f70:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:38:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f646576696365:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061727463686f6f7365725f66616d696c795f63686f6f736572:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061727463686f6f7365725f7061727473:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f63686f6f73655f70726f6a6563745f6c6f636174696f6e:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d61727974696d696e6770616e656c5f70726f6a6563745f73756d6d6172795f74696d696e675f70616e656c5f746162626564:3131:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d6172797574696c697a6174696f6e6761646765745f70726f6a6563745f73756d6d6172795f7574696c697a6174696f6e5f6761646765745f746162626564:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d6172797574696c697a6174696f6e70616e656c5f70726f6a6563745f73756d6d6172795f7574696c697a6174696f6e5f70616e656c5f746162626564:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f72756e5f6761646765745f7461626265645f70616e65:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f73686f775f6572726f72:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f63616e63656c:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:33:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:3131:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f726566726573685f686965726172636879:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7374616c6572756e6469616c6f675f796573:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:746f756368706f696e747375727665796469616c6f675f6e6f:31:00:00
eof:507062380

21
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/java_command_handlers.wdf Normal file
View File

@ -0,0 +1,21 @@
version:1
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:36:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:32:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f726576696577:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:34:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:32:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:36:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:32:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:32:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265706f72747574696c697a6174696f6e:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:38:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:33:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:36:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766566696c6570726f787968616e646c6572:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574746f706e6f6465:32:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:37:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7570646174657265676964:31:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b73796e746865736973:31:00:00
eof:1581560588

4
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/project.wpc Normal file
View File

@ -0,0 +1,4 @@
version:1
57656254616c6b5472616e736d697373696f6e417474656d70746564:4
6d6f64655f636f756e7465727c4755494d6f6465:4
eof:

39
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/synthesis.wdf Normal file
View File

@ -0,0 +1,39 @@
version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78633761313030746373673332342d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:4e65787973345f555354435256536f435f746f70:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a333273:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313136352e3539304d42:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3837362e3037304d42:00:00
eof:3997631030

3
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/synthesis_details.wdf Normal file
View File

@ -0,0 +1,3 @@
version:1
73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
eof:2511430288

106
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt/webtalk_pa.xml Normal file
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@ -0,0 +1,106 @@
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Tue Feb 26 19:19:01 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="802f49394334431ea9abba122e836e9e" type="ProjectID"/>
<property name="ProjectIteration" value="12" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="RTL" type="DesignMode"/>
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="AddSources" value="6" type="JavaHandler"/>
<property name="AutoConnectTarget" value="2" type="JavaHandler"/>
<property name="CoreView" value="1" type="JavaHandler"/>
<property name="CustomizeCore" value="1" type="JavaHandler"/>
<property name="EditDelete" value="4" type="JavaHandler"/>
<property name="LaunchProgramFpga" value="2" type="JavaHandler"/>
<property name="NewProject" value="1" type="JavaHandler"/>
<property name="OpenHardwareManager" value="6" type="JavaHandler"/>
<property name="OpenRecentTarget" value="2" type="JavaHandler"/>
<property name="ProgramDevice" value="2" type="JavaHandler"/>
<property name="ReportUtilization" value="1" type="JavaHandler"/>
<property name="RunBitgen" value="8" type="JavaHandler"/>
<property name="RunImplementation" value="3" type="JavaHandler"/>
<property name="RunSynthesis" value="6" type="JavaHandler"/>
<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/>
<property name="SetTopNode" value="2" type="JavaHandler"/>
<property name="ShowView" value="7" type="JavaHandler"/>
<property name="UpdateRegId" value="1" type="JavaHandler"/>
<property name="ViewTaskSynthesis" value="1" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="AddSrcWizard_SPECIFY_HDL_NETLIST_BLOCK_DESIGN" value="2" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="3" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="16" type="GuiHandlerData"/>
<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="2" type="GuiHandlerData"/>
<property name="ConstraintsChooserPanel_ADD_FILES" value="1" type="GuiHandlerData"/>
<property name="ConstraintsChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="3" type="GuiHandlerData"/>
<property name="CreateConstraintsFilePanel_FILE_NAME" value="2" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_TYPE" value="1" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="107" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="13" type="GuiHandlerData"/>
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="7" type="GuiHandlerData"/>
<property name="IPCoreView_TABBED_PANE" value="2" type="GuiHandlerData"/>
<property name="LogMonitor_MONITOR" value="3" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_HELP" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_VIEW" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="2" type="GuiHandlerData"/>
<property name="MainToolbarMgr_RUN" value="8" type="GuiHandlerData"/>
<property name="MainWinMenuMgr_LAYOUT" value="2" type="GuiHandlerData"/>
<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_SEVERITY" value="2" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="41" type="GuiHandlerData"/>
<property name="MsgView_CRITICAL_WARNINGS" value="5" type="GuiHandlerData"/>
<property name="MsgView_WARNING_MESSAGES" value="2" type="GuiHandlerData"/>
<property name="NetlistTreeView_NETLIST_TREE" value="11" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_SOURCES" value="6" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="13" type="GuiHandlerData"/>
<property name="PACommandNames_LICENSE_MANAGE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_REPORTS_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_BITGEN" value="8" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_SYNTHESIS" value="6" type="GuiHandlerData"/>
<property name="PACommandNames_SET_AS_TOP" value="2" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="8" type="GuiHandlerData"/>
<property name="PAViews_DEVICE" value="2" type="GuiHandlerData"/>
<property name="PartChooser_FAMILY_CHOOSER" value="1" type="GuiHandlerData"/>
<property name="PartChooser_PARTS" value="2" type="GuiHandlerData"/>
<property name="ProgramFpgaDialog_PROGRAM" value="1" type="GuiHandlerData"/>
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="1" type="GuiHandlerData"/>
<property name="ProjectNameChooser_PROJECT_NAME" value="2" type="GuiHandlerData"/>
<property name="ProjectSummaryTimingPanel_PROJECT_SUMMARY_TIMING_PANEL_TABBED" value="11" type="GuiHandlerData"/>
<property name="ProjectSummaryUtilizationGadget_PROJECT_SUMMARY_UTILIZATION_GADGET_TABBED" value="1" type="GuiHandlerData"/>
<property name="ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_PANEL_TABBED" value="2" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="4" type="GuiHandlerData"/>
<property name="RunGadget_RUN_GADGET_TABBED_PANE" value="1" type="GuiHandlerData"/>
<property name="RunGadget_SHOW_ERROR" value="2" type="GuiHandlerData"/>
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="2" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="3" type="GuiHandlerData"/>
<property name="SrcChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="11" type="GuiHandlerData"/>
<property name="SrcMenu_REFRESH_HIERARCHY" value="1" type="GuiHandlerData"/>
<property name="StaleRunDialog_YES" value="1" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="2" type="GuiHandlerData"/>
<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="1" type="GuiHandlerData"/>
<property name="TouchpointSurveyDialog_NO" value="1" type="GuiHandlerData"/>
</item>
</section>
</application>
</document>

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hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.hw/USTCRVSoC-nexys4.lpr Normal file
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@ -0,0 +1,8 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2017.4 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0">
<HWSession Dir="hw_1" File="hw.xml"/>
</labtools>

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hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.hw/hw_1/hw.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2017.4 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -->
<hwsession version="1" minor="2">
<device name="xc7a100t_0" gui_info=""/>
<ObjectList object_type="hw_device" gui_info="">
<Object name="xc7a100t_0" gui_info="">
<Properties Property="FULL_PROBES.FILE" value=""/>
<Properties Property="PROBES.FILE" value=""/>
<Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/Nexys4_USTCRVSoC_top.bit"/>
<Properties Property="SLR.COUNT" value="1"/>
</Object>
</ObjectList>
<probeset name="hw project" active="false"/>
</hwsession>

1
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.ip_user_files/README.txt Normal file
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@ -0,0 +1 @@
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

5
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/.jobs/vrs_config_1.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

5
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/.jobs/vrs_config_10.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
</Runs>

8
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/.jobs/vrs_config_11.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

5
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/.jobs/vrs_config_12.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

5
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/.jobs/vrs_config_13.xml Normal file
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@ -0,0 +1,5 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
</Runs>

5
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/.jobs/vrs_config_14.xml Normal file
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@ -0,0 +1,5 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
</Runs>

5
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/.jobs/vrs_config_15.xml Normal file
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@ -0,0 +1,5 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
</Runs>

8
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/.jobs/vrs_config_16.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

5
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/.jobs/vrs_config_2.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

5
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/.jobs/vrs_config_3.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

5
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/.jobs/vrs_config_4.xml Normal file
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@ -0,0 +1,5 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
</Runs>

5
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/.jobs/vrs_config_5.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
</Runs>

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hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/.jobs/vrs_config_6.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

5
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/.jobs/vrs_config_7.xml Normal file
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@ -0,0 +1,5 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
</Runs>

5
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/.jobs/vrs_config_8.xml Normal file
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@ -0,0 +1,5 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

5
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/.jobs/vrs_config_9.xml Normal file
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@ -0,0 +1,5 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
</Runs>

0
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/.Vivado_Implementation.queue.rst Normal file
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hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/.init_design.begin.rst Normal file
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@ -0,0 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="wgg" Host="DESKTOP-C6I6OAQ" Pid="20504">
</Process>
</ProcessHandle>

0
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/.init_design.end.rst Normal file
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5
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/.opt_design.begin.rst Normal file
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@ -0,0 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="wgg" Host="DESKTOP-C6I6OAQ" Pid="20504">
</Process>
</ProcessHandle>

0
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/.opt_design.end.rst Normal file
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5
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/.place_design.begin.rst Normal file
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@ -0,0 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="wgg" Host="DESKTOP-C6I6OAQ" Pid="20504">
</Process>
</ProcessHandle>

0
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/.place_design.end.rst Normal file
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5
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/.route_design.begin.rst Normal file
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@ -0,0 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="wgg" Host="DESKTOP-C6I6OAQ" Pid="20504">
</Process>
</ProcessHandle>

0
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/.route_design.end.rst Normal file
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hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/.vivado.begin.rst Normal file
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@ -0,0 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="wgg" Host="DESKTOP-C6I6OAQ" Pid="21308">
</Process>
</ProcessHandle>

0
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/.vivado.end.rst Normal file
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hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/.write_bitstream.begin.rst Normal file
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@ -0,0 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="wgg" Host="DESKTOP-C6I6OAQ" Pid="20504">
</Process>
</ProcessHandle>

0
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/.write_bitstream.end.rst Normal file
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//
// Vivado(TM)
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
//
// GLOBAL VARIABLES
var ISEShell = new ActiveXObject( "WScript.Shell" );
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
var ISERunDir = "";
var ISELogFile = "runme.log";
var ISELogFileStr = null;
var ISELogEcho = true;
var ISEOldVersionWSH = false;
// BOOTSTRAP
ISEInit();
//
// ISE FUNCTIONS
//
function ISEInit() {
// 1. RUN DIR setup
var ISEScrFP = WScript.ScriptFullName;
var ISEScrN = WScript.ScriptName;
ISERunDir =
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
// 2. LOG file setup
ISELogFileStr = ISEOpenFile( ISELogFile );
// 3. LOG echo?
var ISEScriptArgs = WScript.Arguments;
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
if ( ISEScriptArgs(loopi) == "-quiet" ) {
ISELogEcho = false;
break;
}
}
// 4. WSH version check
var ISEOptimalVersionWSH = 5.6;
var ISECurrentVersionWSH = WScript.Version;
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
ISEStdErr( "" );
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
ISEOptimalVersionWSH + " or higher. Downloads" );
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
ISEStdErr( "" );
ISEOldVersionWSH = true;
}
}
function ISEStep( ISEProg, ISEArgs ) {
// CHECK for a STOP FILE
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
ISEStdErr( "" );
ISEStdErr( "*** Halting run - EA reset detected ***" );
ISEStdErr( "" );
WScript.Quit( 1 );
}
// WRITE STEP HEADER to LOG
ISEStdOut( "" );
ISEStdOut( "*** Running " + ISEProg );
ISEStdOut( " with args " + ISEArgs );
ISEStdOut( "" );
// LAUNCH!
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
if ( ISEExitCode != 0 ) {
WScript.Quit( ISEExitCode );
}
}
function ISEExec( ISEProg, ISEArgs ) {
var ISEStep = ISEProg;
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
ISEProg += ".bat";
}
var ISECmdLine = ISEProg + " " + ISEArgs;
var ISEExitCode = 1;
if ( ISEOldVersionWSH ) { // WSH 5.1
// BEGIN file creation
ISETouchFile( ISEStep, "begin" );
// LAUNCH!
ISELogFileStr.Close();
ISECmdLine =
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
ISELogFileStr = ISEOpenFile( ISELogFile );
} else { // WSH 5.6
// LAUNCH!
ISEShell.CurrentDirectory = ISERunDir;
// Redirect STDERR to STDOUT
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
var ISEProcess = ISEShell.Exec( ISECmdLine );
// BEGIN file creation
var ISENetwork = WScript.CreateObject( "WScript.Network" );
var ISEHost = ISENetwork.ComputerName;
var ISEUser = ISENetwork.UserName;
var ISEPid = ISEProcess.ProcessID;
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
"\" Owner=\"" + ISEUser +
"\" Host=\"" + ISEHost +
"\" Pid=\"" + ISEPid +
"\">" );
ISEBeginFile.WriteLine( " </Process>" );
ISEBeginFile.WriteLine( "</ProcessHandle>" );
ISEBeginFile.Close();
var ISEOutStr = ISEProcess.StdOut;
var ISEErrStr = ISEProcess.StdErr;
// WAIT for ISEStep to finish
while ( ISEProcess.Status == 0 ) {
// dump stdout then stderr - feels a little arbitrary
while ( !ISEOutStr.AtEndOfStream ) {
ISEStdOut( ISEOutStr.ReadLine() );
}
WScript.Sleep( 100 );
}
ISEExitCode = ISEProcess.ExitCode;
}
ISELogFileStr.Close();
// END/ERROR file creation
if ( ISEExitCode != 0 ) {
ISETouchFile( ISEStep, "error" );
} else {
ISETouchFile( ISEStep, "end" );
}
return ISEExitCode;
}
//
// UTILITIES
//
function ISEStdOut( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdOut.WriteLine( ISELine );
}
}
function ISEStdErr( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdErr.WriteLine( ISELine );
}
}
function ISETouchFile( ISERoot, ISEStatus ) {
var ISETFile =
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
ISETFile.Close();
}
function ISEOpenFile( ISEFilename ) {
// This function has been updated to deal with a problem seen in CR #870871.
// In that case the user runs a script that runs impl_1, and then turns around
// and runs impl_1 -to_step write_bitstream. That second run takes place in
// the same directory, which means we may hit some of the same files, and in
// particular, we will open the runme.log file. Even though this script closes
// the file (now), we see cases where a subsequent attempt to open the file
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
// play? In any case, we try to work around this by first waiting if the file
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
// and try to open the file 10 times with a one second delay after each attempt.
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
// If there is an unrecognized exception when trying to open the file, we output
// an error message and write details to an exception.log file.
var ISEFullPath = ISERunDir + "/" + ISEFilename;
if (ISEFileSys.FileExists(ISEFullPath)) {
// File is already there. This could be a problem. Wait in case it is still in use.
WScript.Sleep(5000);
}
var i;
for (i = 0; i < 10; ++i) {
try {
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
} catch (exception) {
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
if (error_code == 52) { // 52 is bad file name or number.
// Wait a second and try again.
WScript.Sleep(1000);
continue;
} else {
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
var exceptionFilePath = ISERunDir + "/exception.log";
if (!ISEFileSys.FileExists(exceptionFilePath)) {
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
exceptionFile.WriteLine("\tException name: " + exception.name);
exceptionFile.WriteLine("\tException error code: " + error_code);
exceptionFile.WriteLine("\tException message: " + exception.message);
exceptionFile.Close();
}
throw exception;
}
}
}
// If we reached this point, we failed to open the file after 10 attempts.
// We need to error out.
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
WScript.Quit(1);
}

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#!/bin/sh
#
# Vivado(TM)
# ISEWrap.sh: Vivado Runs Script for UNIX
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
#
HD_LOG=$1
shift
# CHECK for a STOP FILE
if [ -f .stop.rst ]
then
echo "" >> $HD_LOG
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
echo "" >> $HD_LOG
exit 1
fi
ISE_STEP=$1
shift
# WRITE STEP HEADER to LOG
echo "" >> $HD_LOG
echo "*** Running $ISE_STEP" >> $HD_LOG
echo " with args $@" >> $HD_LOG
echo "" >> $HD_LOG
# LAUNCH!
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
# BEGIN file creation
ISE_PID=$!
if [ X != X$HOSTNAME ]
then
ISE_HOST=$HOSTNAME #bash
else
ISE_HOST=$HOST #csh
fi
ISE_USER=$USER
ISE_BEGINFILE=.$ISE_STEP.begin.rst
/bin/touch $ISE_BEGINFILE
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
echo " </Process>" >> $ISE_BEGINFILE
echo "</ProcessHandle>" >> $ISE_BEGINFILE
# WAIT for ISEStep to finish
wait $ISE_PID
# END/ERROR file creation
RETVAL=$?
if [ $RETVAL -eq 0 ]
then
/bin/touch .$ISE_STEP.end.rst
else
/bin/touch .$ISE_STEP.error.rst
fi
exit $RETVAL

BIN
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit Normal file
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166
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.tcl Normal file
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#
# Report generation script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
proc start_step { step } {
set stopFile ".stop.rst"
if {[file isfile .stop.rst]} {
puts ""
puts "*** Halting run - EA reset detected ***"
puts ""
puts ""
return -code error
}
set beginFile ".$step.begin.rst"
set platform "$::tcl_platform(platform)"
set user "$::tcl_platform(user)"
set pid [pid]
set host ""
if { [string equal $platform unix] } {
if { [info exist ::env(HOSTNAME)] } {
set host $::env(HOSTNAME)
}
} else {
if { [info exist ::env(COMPUTERNAME)] } {
set host $::env(COMPUTERNAME)
}
}
set ch [open $beginFile w]
puts $ch "<?xml version=\"1.0\"?>"
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
puts $ch " </Process>"
puts $ch "</ProcessHandle>"
close $ch
}
proc end_step { step } {
set endFile ".$step.end.rst"
set ch [open $endFile w]
close $ch
}
proc step_failed { step } {
set endFile ".$step.error.rst"
set ch [open $endFile w]
close $ch
}
start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
create_project -in_memory -part xc7a100tcsg324-1
set_property design_mode GateLvl [current_fileset]
set_param project.singleFileAddWarning.threshold 0
set_property webtalk.parent_dir E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/wt [current_project]
set_property parent.project_path E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr [current_project]
set_property ip_output_repo E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
add_files -quiet E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1/Nexys4_USTCRVSoC_top.dcp
read_xdc E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc
link_design -top Nexys4_USTCRVSoC_top -part xc7a100tcsg324-1
close_msg_db -file init_design.pb
} RESULT]
if {$rc} {
step_failed init_design
return -code error $RESULT
} else {
end_step init_design
unset ACTIVE_STEP
}
start_step opt_design
set ACTIVE_STEP opt_design
set rc [catch {
create_msg_db opt_design.pb
opt_design
write_checkpoint -force Nexys4_USTCRVSoC_top_opt.dcp
create_report "impl_1_opt_report_drc_0" "report_drc -file Nexys4_USTCRVSoC_top_drc_opted.rpt -pb Nexys4_USTCRVSoC_top_drc_opted.pb -rpx Nexys4_USTCRVSoC_top_drc_opted.rpx"
close_msg_db -file opt_design.pb
} RESULT]
if {$rc} {
step_failed opt_design
return -code error $RESULT
} else {
end_step opt_design
unset ACTIVE_STEP
}
start_step place_design
set ACTIVE_STEP place_design
set rc [catch {
create_msg_db place_design.pb
implement_debug_core
place_design
write_checkpoint -force Nexys4_USTCRVSoC_top_placed.dcp
create_report "impl_1_place_report_io_0" "report_io -file Nexys4_USTCRVSoC_top_io_placed.rpt"
create_report "impl_1_place_report_utilization_0" "report_utilization -file Nexys4_USTCRVSoC_top_utilization_placed.rpt -pb Nexys4_USTCRVSoC_top_utilization_placed.pb"
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file Nexys4_USTCRVSoC_top_control_sets_placed.rpt"
close_msg_db -file place_design.pb
} RESULT]
if {$rc} {
step_failed place_design
return -code error $RESULT
} else {
end_step place_design
unset ACTIVE_STEP
}
start_step route_design
set ACTIVE_STEP route_design
set rc [catch {
create_msg_db route_design.pb
route_design
write_checkpoint -force Nexys4_USTCRVSoC_top_routed.dcp
create_report "impl_1_route_report_drc_0" "report_drc -file Nexys4_USTCRVSoC_top_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_drc_routed.rpx"
create_report "impl_1_route_report_methodology_0" "report_methodology -file Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_methodology_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_methodology_drc_routed.rpx"
create_report "impl_1_route_report_power_0" "report_power -file Nexys4_USTCRVSoC_top_power_routed.rpt -pb Nexys4_USTCRVSoC_top_power_summary_routed.pb -rpx Nexys4_USTCRVSoC_top_power_routed.rpx"
create_report "impl_1_route_report_route_status_0" "report_route_status -file Nexys4_USTCRVSoC_top_route_status.rpt -pb Nexys4_USTCRVSoC_top_route_status.pb"
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file Nexys4_USTCRVSoC_top_timing_summary_routed.rpt -rpx Nexys4_USTCRVSoC_top_timing_summary_routed.rpx -warn_on_violation "
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file Nexys4_USTCRVSoC_top_incremental_reuse_routed.rpt"
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file Nexys4_USTCRVSoC_top_clock_utilization_routed.rpt"
close_msg_db -file route_design.pb
} RESULT]
if {$rc} {
write_checkpoint -force Nexys4_USTCRVSoC_top_routed_error.dcp
step_failed route_design
return -code error $RESULT
} else {
end_step route_design
unset ACTIVE_STEP
}
start_step write_bitstream
set ACTIVE_STEP write_bitstream
set rc [catch {
create_msg_db write_bitstream.pb
catch { write_mem_info -force Nexys4_USTCRVSoC_top.mmi }
write_bitstream -force Nexys4_USTCRVSoC_top.bit
catch {write_debug_probes -quiet -force Nexys4_USTCRVSoC_top}
catch {file copy -force Nexys4_USTCRVSoC_top.ltx debug_nets.ltx}
close_msg_db -file write_bitstream.pb
} RESULT]
if {$rc} {
step_failed write_bitstream
return -code error $RESULT
} else {
end_step write_bitstream
unset ACTIVE_STEP
}

539
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.vdi Normal file
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#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Tue Feb 26 19:20:55 2019
# Process ID: 20504
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1
# Command line: vivado.exe -log Nexys4_USTCRVSoC_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Nexys4_USTCRVSoC_top.tcl -notrace
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.vdi
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source Nexys4_USTCRVSoC_top.tcl -notrace
Command: link_design -top Nexys4_USTCRVSoC_top -part xc7a100tcsg324-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 319 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc]
Finished Parsing XDC File [E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 641.695 ; gain = 348.359
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.526 . Memory (MB): peak = 646.332 ; gain = 4.637
INFO: [Timing 38-35] Done setting XDC timing constraints.
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 13eadb8e1
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.372 . Memory (MB): peak = 1213.672 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 3 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 169946815
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.516 . Memory (MB): peak = 1213.672 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 10ac3042c
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.618 . Memory (MB): peak = 1213.672 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 18 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 10ac3042c
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.707 . Memory (MB): peak = 1213.672 ; gain = 0.000
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 10ac3042c
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.783 . Memory (MB): peak = 1213.672 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1213.672 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 1105aca7b
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.865 . Memory (MB): peak = 1213.672 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.769 | TNS=0.000 |
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 13 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 5 Total Ports: 26
Ending PowerOpt Patch Enables Task | Checksum: 15ce38535
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1415.492 ; gain = 0.000
Ending Power Optimization Task | Checksum: 15ce38535
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1415.492 ; gain = 201.820
Starting Logic Optimization Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1 Remap
Phase 1 Remap | Checksum: 16c4c4a0f
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.386 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [Opt 31-389] Phase Remap created 5 cells and removed 10 cells
Ending Logic Optimization Task | Checksum: 16c4c4a0f
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.397 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 1415.492 ; gain = 773.797
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file Nexys4_USTCRVSoC_top_drc_opted.rpt -pb Nexys4_USTCRVSoC_top_drc_opted.pb -rpx Nexys4_USTCRVSoC_top_drc_opted.rpx
Command: report_drc -file Nexys4_USTCRVSoC_top_drc_opted.rpt -pb Nexys4_USTCRVSoC_top_drc_opted.pb -rpx Nexys4_USTCRVSoC_top_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_drc_opted.rpt.
report_drc completed successfully
INFO: [Chipscope 16-241] No debug cores found in the current design.
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_memwrite_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[16]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[17]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[19]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[21]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[22]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[23]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[24]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[25]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[26]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[28]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[29]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[30]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[31]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 21 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 40e63c3d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 19c12ad57
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 2654ed21f
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 2654ed21f
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 2654ed21f
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 26f8edad2
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 26f8edad2
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 244c6aa9d
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1e06eec96
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 20a4c2c3c
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 2da3e0599
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1f5000c7e
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1f5000c7e
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 3 Detail Placement | Checksum: 1f5000c7e
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: a6f92177
Phase 4.1.1.1 BUFG Insertion
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
Phase 4.1.1.1 BUFG Insertion | Checksum: a6f92177
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.882. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 4dee693a
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 4.1 Post Commit Optimization | Checksum: 4dee693a
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 4dee693a
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 4dee693a
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: a535ead8
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up | Checksum: a535ead8
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
Ending Placer Task | Checksum: 9fd0d3a8
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
54 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:12 . Memory (MB): peak = 1415.492 ; gain = 0.000
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.499 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file Nexys4_USTCRVSoC_top_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file Nexys4_USTCRVSoC_top_utilization_placed.rpt -pb Nexys4_USTCRVSoC_top_utilization_placed.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [runtcl-4] Executing : report_control_sets -verbose -file Nexys4_USTCRVSoC_top_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1415.492 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: e685d48 ConstDB: 0 ShapeSum: 91687660 RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 7fa797b6
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1422.488 ; gain = 6.996
Post Restoration Checksum: NetGraph: 29d8a759 NumContArr: 55cef05d Constraints: 0 Timing: 0
Phase 2 Router Initialization
Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 7fa797b6
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1422.488 ; gain = 6.996
Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 7fa797b6
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1422.488 ; gain = 6.996
Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 7fa797b6
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1422.488 ; gain = 6.996
Number of Nodes with overlaps = 0
Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 28a805e33
Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1436.664 ; gain = 21.172
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.796 | TNS=0.000 | WHS=0.007 | THS=0.000 |
Phase 2 Router Initialization | Checksum: 292708314
Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 212fd4de5
Time (s): cpu = 00:00:33 ; elapsed = 00:00:28 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 1074
Number of Nodes with overlaps = 9
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.421 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 1eeceb63b
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 4 Rip-up And Reroute | Checksum: 1eeceb63b
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 1eeceb63b
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1eeceb63b
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 5 Delay and Skew Optimization | Checksum: 1eeceb63b
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1cac9a9f3
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.517 | TNS=0.000 | WHS=0.401 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 1cac9a9f3
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 6 Post Hold Fix | Checksum: 1cac9a9f3
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 1.46077 %
Global Horizontal Routing Utilization = 1.79511 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 1cac9a9f3
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1cac9a9f3
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1aca853e4
Time (s): cpu = 00:00:38 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.517 | TNS=0.000 | WHS=0.401 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 1aca853e4
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1436.664 ; gain = 21.172
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1436.664 ; gain = 21.172
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
70 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:40 ; elapsed = 00:00:31 . Memory (MB): peak = 1436.664 ; gain = 21.172
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.667 . Memory (MB): peak = 1436.664 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file Nexys4_USTCRVSoC_top_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_drc_routed.rpx
Command: report_drc -file Nexys4_USTCRVSoC_top_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_methodology_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_methodology_drc_routed.rpx
Command: report_methodology -file Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_methodology_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file Nexys4_USTCRVSoC_top_power_routed.rpt -pb Nexys4_USTCRVSoC_top_power_summary_routed.pb -rpx Nexys4_USTCRVSoC_top_power_routed.rpx
Command: report_power -file Nexys4_USTCRVSoC_top_power_routed.rpt -pb Nexys4_USTCRVSoC_top_power_summary_routed.pb -rpx Nexys4_USTCRVSoC_top_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
82 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file Nexys4_USTCRVSoC_top_route_status.rpt -pb Nexys4_USTCRVSoC_top_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Nexys4_USTCRVSoC_top_timing_summary_routed.rpt -rpx Nexys4_USTCRVSoC_top_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file Nexys4_USTCRVSoC_top_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
INFO: [runtcl-4] Executing : report_clock_utilization -file Nexys4_USTCRVSoC_top_clock_utilization_routed.rpt
Command: write_bitstream -force Nexys4_USTCRVSoC_top.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_memwrite_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[16]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[17]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[19]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[21]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[22]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[23]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[24]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[25]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[26]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[28]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[29]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[30]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[31]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 22 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Project 1-821] Please set project.enableDesignId to be 'true'.
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./Nexys4_USTCRVSoC_top.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-186] 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Feb 26 19:22:42 2019. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2017.4/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
100 Infos, 43 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1910.711 ; gain = 447.070
INFO: [Common 17-206] Exiting Vivado at Tue Feb 26 19:22:42 2019...

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#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Tue Feb 26 17:56:46 2019
# Process ID: 520
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1
# Command line: vivado.exe -log Nexys4_USTCRVSoC_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Nexys4_USTCRVSoC_top.tcl -notrace
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.vdi
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source Nexys4_USTCRVSoC_top.tcl -notrace
Command: link_design -top Nexys4_USTCRVSoC_top -part xc7a100tcsg324-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 319 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc]
Finished Parsing XDC File [E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 642.496 ; gain = 349.480
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.539 . Memory (MB): peak = 651.313 ; gain = 8.816
INFO: [Timing 38-35] Done setting XDC timing constraints.
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: f6786b86
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.357 . Memory (MB): peak = 1213.191 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 3 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 197279e5e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.502 . Memory (MB): peak = 1213.191 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: bf162ee0
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.604 . Memory (MB): peak = 1213.191 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 18 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: bf162ee0
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.694 . Memory (MB): peak = 1213.191 ; gain = 0.000
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: bf162ee0
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.771 . Memory (MB): peak = 1213.191 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1213.191 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 184e8243e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.856 . Memory (MB): peak = 1213.191 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.769 | TNS=0.000 |
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 13 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 5 Total Ports: 26
Ending PowerOpt Patch Enables Task | Checksum: 53b43e8f
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1418.734 ; gain = 0.000
Ending Power Optimization Task | Checksum: 53b43e8f
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1418.734 ; gain = 205.543
Starting Logic Optimization Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1 Remap
Phase 1 Remap | Checksum: fa17b0bc
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.381 . Memory (MB): peak = 1418.734 ; gain = 0.000
INFO: [Opt 31-389] Phase Remap created 5 cells and removed 10 cells
Ending Logic Optimization Task | Checksum: fa17b0bc
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.392 . Memory (MB): peak = 1418.734 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 1418.734 ; gain = 776.238
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1418.734 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file Nexys4_USTCRVSoC_top_drc_opted.rpt -pb Nexys4_USTCRVSoC_top_drc_opted.pb -rpx Nexys4_USTCRVSoC_top_drc_opted.rpx
Command: report_drc -file Nexys4_USTCRVSoC_top_drc_opted.rpt -pb Nexys4_USTCRVSoC_top_drc_opted.pb -rpx Nexys4_USTCRVSoC_top_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_drc_opted.rpt.
report_drc completed successfully
INFO: [Chipscope 16-241] No debug cores found in the current design.
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_memwrite_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[16]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[17]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[18]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[19]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[21]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[22]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[23]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[24]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[25]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[27]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[28]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[29]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[31]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 21 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d5f6be65
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1418.734 ; gain = 0.000
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 19141b54c
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 26e6ee7f4
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 26e6ee7f4
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 26e6ee7f4
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 279477d6a
Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 279477d6a
Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 15cdba6a9
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 206e90d49
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1805ce344
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 14ba068f7
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1117e4fa0
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1117e4fa0
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 3 Detail Placement | Checksum: 1117e4fa0
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: a197169c
Phase 4.1.1.1 BUFG Insertion
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
Phase 4.1.1.1 BUFG Insertion | Checksum: a197169c
Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 1418.734 ; gain = 0.000
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.867. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 5dd8f8be
Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 4.1 Post Commit Optimization | Checksum: 5dd8f8be
Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 5dd8f8be
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 5dd8f8be
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 2f1f95ac
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1418.734 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2f1f95ac
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1418.734 ; gain = 0.000
Ending Placer Task | Checksum: 2d3cbfee
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1418.734 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
54 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 1418.734 ; gain = 0.000
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.499 . Memory (MB): peak = 1418.734 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file Nexys4_USTCRVSoC_top_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1418.734 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file Nexys4_USTCRVSoC_top_utilization_placed.rpt -pb Nexys4_USTCRVSoC_top_utilization_placed.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.076 . Memory (MB): peak = 1418.734 ; gain = 0.000
INFO: [runtcl-4] Executing : report_control_sets -verbose -file Nexys4_USTCRVSoC_top_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1418.734 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 1dafca7a ConstDB: 0 ShapeSum: f8cf574 RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 107e60b4f
Time (s): cpu = 00:00:30 ; elapsed = 00:00:27 . Memory (MB): peak = 1427.777 ; gain = 9.043
Post Restoration Checksum: NetGraph: 7d407409 NumContArr: 8aa59746 Constraints: 0 Timing: 0
Phase 2 Router Initialization
Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 107e60b4f
Time (s): cpu = 00:00:30 ; elapsed = 00:00:27 . Memory (MB): peak = 1427.777 ; gain = 9.043
Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 107e60b4f
Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1427.777 ; gain = 9.043
Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 107e60b4f
Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1427.777 ; gain = 9.043
Number of Nodes with overlaps = 0
Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 1bb8b35b4
Time (s): cpu = 00:00:33 ; elapsed = 00:00:28 . Memory (MB): peak = 1431.434 ; gain = 12.699
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.781 | TNS=0.000 | WHS=0.001 | THS=0.000 |
Phase 2 Router Initialization | Checksum: 1ecbd7787
Time (s): cpu = 00:00:33 ; elapsed = 00:00:28 . Memory (MB): peak = 1431.434 ; gain = 12.699
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 145a48684
Time (s): cpu = 00:00:35 ; elapsed = 00:00:29 . Memory (MB): peak = 1431.434 ; gain = 12.699
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 1072
Number of Nodes with overlaps = 5
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.142 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 2356a8003
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
Phase 4 Rip-up And Reroute | Checksum: 2356a8003
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 2356a8003
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 2356a8003
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
Phase 5 Delay and Skew Optimization | Checksum: 2356a8003
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 2220221b5
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.238 | TNS=0.000 | WHS=0.472 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 2220221b5
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
Phase 6 Post Hold Fix | Checksum: 2220221b5
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 1.49872 %
Global Horizontal Routing Utilization = 1.8604 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 2220221b5
Time (s): cpu = 00:00:39 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 2220221b5
Time (s): cpu = 00:00:39 ; elapsed = 00:00:31 . Memory (MB): peak = 1431.434 ; gain = 12.699
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 25b5d5941
Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 1431.434 ; gain = 12.699
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.238 | TNS=0.000 | WHS=0.472 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 25b5d5941
Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 1431.434 ; gain = 12.699
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 1431.434 ; gain = 12.699
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
70 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 1431.434 ; gain = 12.699
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.673 . Memory (MB): peak = 1431.434 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file Nexys4_USTCRVSoC_top_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_drc_routed.rpx
Command: report_drc -file Nexys4_USTCRVSoC_top_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_methodology_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_methodology_drc_routed.rpx
Command: report_methodology -file Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_methodology_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file Nexys4_USTCRVSoC_top_power_routed.rpt -pb Nexys4_USTCRVSoC_top_power_summary_routed.pb -rpx Nexys4_USTCRVSoC_top_power_routed.rpx
Command: report_power -file Nexys4_USTCRVSoC_top_power_routed.rpt -pb Nexys4_USTCRVSoC_top_power_summary_routed.pb -rpx Nexys4_USTCRVSoC_top_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
82 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file Nexys4_USTCRVSoC_top_route_status.rpt -pb Nexys4_USTCRVSoC_top_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Nexys4_USTCRVSoC_top_timing_summary_routed.rpt -rpx Nexys4_USTCRVSoC_top_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file Nexys4_USTCRVSoC_top_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
INFO: [runtcl-4] Executing : report_clock_utilization -file Nexys4_USTCRVSoC_top_clock_utilization_routed.rpt
INFO: [Common 17-206] Exiting Vivado at Tue Feb 26 17:58:16 2019...
#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Tue Feb 26 19:10:27 2019
# Process ID: 17984
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1
# Command line: vivado.exe -log Nexys4_USTCRVSoC_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Nexys4_USTCRVSoC_top.tcl -notrace
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.vdi
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source Nexys4_USTCRVSoC_top.tcl -notrace
*** Halting run - EA reset detected ***
while executing
"start_step write_bitstream"
(file "Nexys4_USTCRVSoC_top.tcl" line 64)
INFO: [Common 17-206] Exiting Vivado at Tue Feb 26 19:10:35 2019...

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<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7a100tcsg324-1" LaunchTime="1551179941">
<File Type="PWROPT-DCP" Name="Nexys4_USTCRVSoC_top_pwropt.dcp"/>
<File Type="ROUTE-PWR" Name="Nexys4_USTCRVSoC_top_power_routed.rpt"/>
<File Type="PA-TCL" Name="Nexys4_USTCRVSoC_top.tcl"/>
<File Type="ROUTE-PWR-SUM" Name="Nexys4_USTCRVSoC_top_power_summary_routed.pb"/>
<File Type="REPORTS-TCL" Name="Nexys4_USTCRVSoC_top_reports.tcl"/>
<File Type="BG-DRC" Name="Nexys4_USTCRVSoC_top.drc"/>
<File Type="OPT-METHODOLOGY-DRC" Name="Nexys4_USTCRVSoC_top_methodology_drc_opted.rpt"/>
<File Type="INIT-TIMING" Name="Nexys4_USTCRVSoC_top_timing_summary_init.rpt"/>
<File Type="OPT-HWDEF" Name="Nexys4_USTCRVSoC_top.hwdef"/>
<File Type="OPT-DCP" Name="Nexys4_USTCRVSoC_top_opt.dcp"/>
<File Type="OPT-DRC" Name="Nexys4_USTCRVSoC_top_drc_opted.rpt"/>
<File Type="OPT-TIMING" Name="Nexys4_USTCRVSoC_top_timing_summary_opted.rpt"/>
<File Type="PWROPT-DRC" Name="Nexys4_USTCRVSoC_top_drc_pwropted.rpt"/>
<File Type="PWROPT-TIMING" Name="Nexys4_USTCRVSoC_top_timing_summary_pwropted.rpt"/>
<File Type="PLACE-DCP" Name="Nexys4_USTCRVSoC_top_placed.dcp"/>
<File Type="PLACE-IO" Name="Nexys4_USTCRVSoC_top_io_placed.rpt"/>
<File Type="PLACE-CLK" Name="Nexys4_USTCRVSoC_top_clock_utilization_placed.rpt"/>
<File Type="PLACE-UTIL" Name="Nexys4_USTCRVSoC_top_utilization_placed.rpt"/>
<File Type="PLACE-UTIL-PB" Name="Nexys4_USTCRVSoC_top_utilization_placed.pb"/>
<File Type="PLACE-CTRL" Name="Nexys4_USTCRVSoC_top_control_sets_placed.rpt"/>
<File Type="PLACE-SIMILARITY" Name="Nexys4_USTCRVSoC_top_incremental_reuse_placed.rpt"/>
<File Type="PLACE-PRE-SIMILARITY" Name="Nexys4_USTCRVSoC_top_incremental_reuse_pre_placed.rpt"/>
<File Type="PLACE-TIMING" Name="Nexys4_USTCRVSoC_top_timing_summary_placed.rpt"/>
<File Type="POSTPLACE-PWROPT-DCP" Name="Nexys4_USTCRVSoC_top_postplace_pwropt.dcp"/>
<File Type="POSTPLACE-PWROPT-TIMING" Name="Nexys4_USTCRVSoC_top_timing_summary_postplace_pwropted.rpt"/>
<File Type="PHYSOPT-DCP" Name="Nexys4_USTCRVSoC_top_physopt.dcp"/>
<File Type="PHYSOPT-DRC" Name="Nexys4_USTCRVSoC_top_drc_physopted.rpt"/>
<File Type="BG-BIT" Name="Nexys4_USTCRVSoC_top.bit"/>
<File Type="PHYSOPT-TIMING" Name="Nexys4_USTCRVSoC_top_timing_summary_physopted.rpt"/>
<File Type="ROUTE-ERROR-DCP" Name="Nexys4_USTCRVSoC_top_routed_error.dcp"/>
<File Type="ROUTE-DCP" Name="Nexys4_USTCRVSoC_top_routed.dcp"/>
<File Type="ROUTE-BLACKBOX-DCP" Name="Nexys4_USTCRVSoC_top_routed_bb.dcp"/>
<File Type="ROUTE-DRC" Name="Nexys4_USTCRVSoC_top_drc_routed.rpt"/>
<File Type="ROUTE-DRC-PB" Name="Nexys4_USTCRVSoC_top_drc_routed.pb"/>
<File Type="BITSTR-MSK" Name="Nexys4_USTCRVSoC_top.msk"/>
<File Type="ROUTE-DRC-RPX" Name="Nexys4_USTCRVSoC_top_drc_routed.rpx"/>
<File Type="BG-BGN" Name="Nexys4_USTCRVSoC_top.bgn"/>
<File Type="ROUTE-METHODOLOGY-DRC" Name="Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt"/>
<File Type="BITSTR-RBT" Name="Nexys4_USTCRVSoC_top.rbt"/>
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="Nexys4_USTCRVSoC_top_methodology_drc_routed.rpx"/>
<File Type="BG-BIN" Name="Nexys4_USTCRVSoC_top.bin"/>
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="Nexys4_USTCRVSoC_top_methodology_drc_routed.pb"/>
<File Type="ROUTE-PWR-RPX" Name="Nexys4_USTCRVSoC_top_power_routed.rpx"/>
<File Type="ROUTE-STATUS" Name="Nexys4_USTCRVSoC_top_route_status.rpt"/>
<File Type="ROUTE-STATUS-PB" Name="Nexys4_USTCRVSoC_top_route_status.pb"/>
<File Type="ROUTE-TIMINGSUMMARY" Name="Nexys4_USTCRVSoC_top_timing_summary_routed.rpt"/>
<File Type="ROUTE-TIMING-PB" Name="Nexys4_USTCRVSoC_top_timing_summary_routed.pb"/>
<File Type="ROUTE-TIMING-RPX" Name="Nexys4_USTCRVSoC_top_timing_summary_routed.rpx"/>
<File Type="ROUTE-SIMILARITY" Name="Nexys4_USTCRVSoC_top_incremental_reuse_routed.rpt"/>
<File Type="RDI-RDI" Name="Nexys4_USTCRVSoC_top.vdi"/>
<File Type="ROUTE-CLK" Name="Nexys4_USTCRVSoC_top_clock_utilization_routed.rpt"/>
<File Type="POSTROUTE-PHYSOPT-DCP" Name="Nexys4_USTCRVSoC_top_postroute_physopt.dcp"/>
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="Nexys4_USTCRVSoC_top_postroute_physopt_bb.dcp"/>
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="Nexys4_USTCRVSoC_top_timing_summary_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="Nexys4_USTCRVSoC_top_timing_summary_postroute_physopted.pb"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="Nexys4_USTCRVSoC_top_timing_summary_postroute_physopted.rpx"/>
<File Type="BITSTR-NKY" Name="Nexys4_USTCRVSoC_top.nky"/>
<File Type="BITSTR-BMM" Name="Nexys4_USTCRVSoC_top_bd.bmm"/>
<File Type="BITSTR-MMI" Name="Nexys4_USTCRVSoC_top.mmi"/>
<File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
<File Type="BITSTR-LTX" Name="Nexys4_USTCRVSoC_top.ltx"/>
<File Type="BITSTR-SYSDEF" Name="Nexys4_USTCRVSoC_top.sysdef"/>
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../../RTL/core_alu.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../RTL/core_bus_wrapper.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../RTL/core_ex_branch_judge.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../RTL/core_id_stage.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../RTL/core_regfile.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../RTL/core_top.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../RTL/instr_rom.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../RTL/isp_uart.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../RTL/naive_bus.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../RTL/naive_bus_router.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../RTL/ram.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../RTL/ram_bus_wrapper.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../RTL/soc_top.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../RTL/uart_rx.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../RTL/uart_tx_line.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../RTL/user_uart_tx.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../RTL/video_ram.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/Nexys4_USTCRVSoC_top.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="Nexys4_USTCRVSoC_top"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/Nexys-A7-100T-Master.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</GenRun>

9
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/htr.txt Normal file
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REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
REM
vivado -log Nexys4_USTCRVSoC_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Nexys4_USTCRVSoC_top.tcl -notrace

BIN
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hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/project.wdf Normal file
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@ -0,0 +1,31 @@
version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3138:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6464633833343066316562613462386262623037366131316239623832303238:506172656e742050412070726f6a656374204944:00
eof:566565886

BIN
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/route_design.pb Normal file
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40
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/rundef.js Normal file
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//
// Vivado(TM)
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//
var WshShell = new ActiveXObject( "WScript.Shell" );
var ProcEnv = WshShell.Environment( "Process" );
var PathVal = ProcEnv("PATH");
if ( PathVal.length == 0 ) {
PathVal = "C:/Xilinx/SDK/2017.4/bin;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2017.4/bin;";
} else {
PathVal = "C:/Xilinx/SDK/2017.4/bin;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2017.4/bin;" + PathVal;
}
ProcEnv("PATH") = PathVal;
var RDScrFP = WScript.ScriptFullName;
var RDScrN = WScript.ScriptName;
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
eval( EAInclude(ISEJScriptLib) );
// pre-commands:
ISETouchFile( "init_design", "begin" );
ISEStep( "vivado",
"-log Nexys4_USTCRVSoC_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Nexys4_USTCRVSoC_top.tcl -notrace" );
function EAInclude( EAInclFilename ) {
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
var EAIFContents = EAInclFile.ReadAll();
EAInclFile.Close();
return EAIFContents;
}

10
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/runme.bat Normal file
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@ -0,0 +1,10 @@
@echo off
rem Vivado (TM)
rem runme.bat: a Vivado-generated Script
rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
set HD_SDIR=%~dp0
cd /d "%HD_SDIR%"
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*

538
hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/runme.log Normal file
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*** Running vivado
with args -log Nexys4_USTCRVSoC_top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Nexys4_USTCRVSoC_top.tcl -notrace
****** Vivado v2017.4 (64-bit)
**** SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
**** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
source Nexys4_USTCRVSoC_top.tcl -notrace
Command: link_design -top Nexys4_USTCRVSoC_top -part xc7a100tcsg324-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 319 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc]
Finished Parsing XDC File [E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.srcs/constrs_1/Nexys-A7-100T-Master.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 641.695 ; gain = 348.359
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.526 . Memory (MB): peak = 646.332 ; gain = 4.637
INFO: [Timing 38-35] Done setting XDC timing constraints.
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 13eadb8e1
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.372 . Memory (MB): peak = 1213.672 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 3 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 169946815
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.516 . Memory (MB): peak = 1213.672 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 10ac3042c
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.618 . Memory (MB): peak = 1213.672 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 18 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 10ac3042c
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.707 . Memory (MB): peak = 1213.672 ; gain = 0.000
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 10ac3042c
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.783 . Memory (MB): peak = 1213.672 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1213.672 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 1105aca7b
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.865 . Memory (MB): peak = 1213.672 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.769 | TNS=0.000 |
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 13 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 5 Total Ports: 26
Ending PowerOpt Patch Enables Task | Checksum: 15ce38535
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1415.492 ; gain = 0.000
Ending Power Optimization Task | Checksum: 15ce38535
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 1415.492 ; gain = 201.820
Starting Logic Optimization Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1 Remap
Phase 1 Remap | Checksum: 16c4c4a0f
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.386 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [Opt 31-389] Phase Remap created 5 cells and removed 10 cells
Ending Logic Optimization Task | Checksum: 16c4c4a0f
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.397 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 1415.492 ; gain = 773.797
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file Nexys4_USTCRVSoC_top_drc_opted.rpt -pb Nexys4_USTCRVSoC_top_drc_opted.pb -rpx Nexys4_USTCRVSoC_top_drc_opted.rpx
Command: report_drc -file Nexys4_USTCRVSoC_top_drc_opted.rpt -pb Nexys4_USTCRVSoC_top_drc_opted.pb -rpx Nexys4_USTCRVSoC_top_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_drc_opted.rpt.
report_drc completed successfully
INFO: [Chipscope 16-241] No debug cores found in the current design.
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_memwrite_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[16]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[17]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[19]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[21]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[22]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[23]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[24]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[25]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[26]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[28]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[29]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[30]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[31]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 21 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 40e63c3d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 19c12ad57
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 2654ed21f
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 2654ed21f
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 2654ed21f
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 26f8edad2
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 26f8edad2
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 244c6aa9d
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1e06eec96
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 20a4c2c3c
Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 2da3e0599
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1f5000c7e
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1f5000c7e
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 3 Detail Placement | Checksum: 1f5000c7e
Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: a6f92177
Phase 4.1.1.1 BUFG Insertion
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
Phase 4.1.1.1 BUFG Insertion | Checksum: a6f92177
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.882. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 4dee693a
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 4.1 Post Commit Optimization | Checksum: 4dee693a
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 4dee693a
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 4dee693a
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: a535ead8
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up | Checksum: a535ead8
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
Ending Placer Task | Checksum: 9fd0d3a8
Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
54 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:12 . Memory (MB): peak = 1415.492 ; gain = 0.000
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.499 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file Nexys4_USTCRVSoC_top_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file Nexys4_USTCRVSoC_top_utilization_placed.rpt -pb Nexys4_USTCRVSoC_top_utilization_placed.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1415.492 ; gain = 0.000
INFO: [runtcl-4] Executing : report_control_sets -verbose -file Nexys4_USTCRVSoC_top_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1415.492 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: e685d48 ConstDB: 0 ShapeSum: 91687660 RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 7fa797b6
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1422.488 ; gain = 6.996
Post Restoration Checksum: NetGraph: 29d8a759 NumContArr: 55cef05d Constraints: 0 Timing: 0
Phase 2 Router Initialization
Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 7fa797b6
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1422.488 ; gain = 6.996
Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 7fa797b6
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1422.488 ; gain = 6.996
Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 7fa797b6
Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1422.488 ; gain = 6.996
Number of Nodes with overlaps = 0
Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 28a805e33
Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1436.664 ; gain = 21.172
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.796 | TNS=0.000 | WHS=0.007 | THS=0.000 |
Phase 2 Router Initialization | Checksum: 292708314
Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 212fd4de5
Time (s): cpu = 00:00:33 ; elapsed = 00:00:28 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 1074
Number of Nodes with overlaps = 9
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.421 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 1eeceb63b
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 4 Rip-up And Reroute | Checksum: 1eeceb63b
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 1eeceb63b
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1eeceb63b
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 5 Delay and Skew Optimization | Checksum: 1eeceb63b
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1cac9a9f3
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.517 | TNS=0.000 | WHS=0.401 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 1cac9a9f3
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 6 Post Hold Fix | Checksum: 1cac9a9f3
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 1.46077 %
Global Horizontal Routing Utilization = 1.79511 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 1cac9a9f3
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1cac9a9f3
Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1aca853e4
Time (s): cpu = 00:00:38 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.664 ; gain = 21.172
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.517 | TNS=0.000 | WHS=0.401 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 1aca853e4
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1436.664 ; gain = 21.172
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1436.664 ; gain = 21.172
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
70 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:40 ; elapsed = 00:00:31 . Memory (MB): peak = 1436.664 ; gain = 21.172
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.667 . Memory (MB): peak = 1436.664 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file Nexys4_USTCRVSoC_top_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_drc_routed.rpx
Command: report_drc -file Nexys4_USTCRVSoC_top_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_methodology_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_methodology_drc_routed.rpx
Command: report_methodology -file Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt -pb Nexys4_USTCRVSoC_top_methodology_drc_routed.pb -rpx Nexys4_USTCRVSoC_top_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file Nexys4_USTCRVSoC_top_power_routed.rpt -pb Nexys4_USTCRVSoC_top_power_summary_routed.pb -rpx Nexys4_USTCRVSoC_top_power_routed.rpx
Command: report_power -file Nexys4_USTCRVSoC_top_power_routed.rpt -pb Nexys4_USTCRVSoC_top_power_summary_routed.pb -rpx Nexys4_USTCRVSoC_top_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
82 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file Nexys4_USTCRVSoC_top_route_status.rpt -pb Nexys4_USTCRVSoC_top_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Nexys4_USTCRVSoC_top_timing_summary_routed.rpt -rpx Nexys4_USTCRVSoC_top_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file Nexys4_USTCRVSoC_top_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
INFO: [runtcl-4] Executing : report_clock_utilization -file Nexys4_USTCRVSoC_top_clock_utilization_routed.rpt
Command: write_bitstream -force Nexys4_USTCRVSoC_top.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit reached: 20 violations have been found.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_memwrite_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[16]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[17]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[19]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[20]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[21]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[22]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[23]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[24]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[25]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[26]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[28]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[29]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[30]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg has an input control pin soc_inst/data_ram_inst/ram_block_inst_0/data_ram_cell_reg/ADDRARDADDR[13] (net: soc_inst/data_ram_inst/ram_block_inst_0/bus\\.wr_addr_reg[11][9]) which is driven by a register (soc_inst/core_top_inst/mem_s1_plus_imm_reg[31]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 22 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Project 1-821] Please set project.enableDesignId to be 'true'.
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./Nexys4_USTCRVSoC_top.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-186] 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Feb 26 19:22:42 2019. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2017.4/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
100 Infos, 43 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1910.711 ; gain = 447.070
INFO: [Common 17-206] Exiting Vivado at Tue Feb 26 19:22:42 2019...

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