mirror of
https://github.com/WangXuan95/USTC-RVSoC.git
synced 2025-01-30 23:02:55 +08:00
chore: 添加modelsim和quartus工程的gitignore
This commit is contained in:
parent
df43dd1898
commit
cac1b99f6e
43
.gitignore
vendored
43
.gitignore
vendored
@ -26,3 +26,46 @@
|
||||
!Nexys4_USTCRVSoC_top.bit
|
||||
**/software/ASM
|
||||
**/Quartus/UART_ISP_TEST
|
||||
|
||||
|
||||
##############quartus###################
|
||||
db
|
||||
greybox_tmp
|
||||
incremental_db
|
||||
output_files
|
||||
simulation
|
||||
*.qws
|
||||
*.ddb
|
||||
*.xml
|
||||
*.csv
|
||||
*.wlf
|
||||
*.bak
|
||||
*.tmp2
|
||||
*1.v
|
||||
*.html
|
||||
*.xml
|
||||
*.rpt
|
||||
*.stp
|
||||
*.echo
|
||||
*.done
|
||||
*.smsg
|
||||
*.summary
|
||||
*.jdi
|
||||
*.qdf
|
||||
*.jic
|
||||
|
||||
|
||||
##############modelsim###################
|
||||
work
|
||||
*.mpf
|
||||
*.mti
|
||||
*.wlf
|
||||
*.vstf
|
||||
wlf*
|
||||
transcript
|
||||
virtuals.do
|
||||
wave.do
|
||||
*.ini
|
||||
*.tr
|
||||
*.ver
|
||||
|
||||
|
Loading…
x
Reference in New Issue
Block a user