mirror of
https://github.com/WangXuan95/USTC-RVSoC.git
synced 2024-12-24 22:58:56 +08:00
优化Core和VGA的资源消耗
This commit is contained in:
WangXuan95
parent
6ac644f407
commit
e36557d90f
@ -8,8 +8,8 @@
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> * 简单直观的32bit握手总线 (naive_bus.sv)，
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> * 总线仲裁器(naive_bus_router.sv)可修改，以方便拓展外设、多核、DMA等
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> * 具有交互式UART调试器(isp_uart.sv)，用户可以使用PC上的串口助手、minicom等软件，实现系统复位、上传程序、查看内存等功能
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> * 全部使用SystemVerilog实现，不调用IP核，方便在Altera、Xilinx、Lattice等不同FPGA平台上移植
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> * RAM符合一定的Verilog写法，自动综合成Block RAM
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> * 全部使用 SystemVerilog 实现，不调用IP核，方便在 Altera、Xilinx、Lattice 等不同FPGA平台上移植，也方便在各种工具中进行仿真
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> * RAM 符合一定的Verilog写法，自动综合成 Block RAM
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# SoC 结构
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Binary file not shown.
@ -48,7 +48,7 @@
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this.portSelectionBox = new System.Windows.Forms.ComboBox();
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this.bootAddrGroup = new System.Windows.Forms.GroupBox();
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this.bootAddrTextBox = new System.Windows.Forms.TextBox();
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this.tableLayoutPanel1 = new System.Windows.Forms.TableLayoutPanel();
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this.MainLayout = new System.Windows.Forms.TableLayoutPanel();
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this.tableLayoutPanel2 = new System.Windows.Forms.TableLayoutPanel();
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this.groupBox1 = new System.Windows.Forms.GroupBox();
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this.tableLayoutPanel7 = new System.Windows.Forms.TableLayoutPanel();
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@ -58,6 +58,15 @@
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this.userPortOpenCloseBtn = new System.Windows.Forms.Button();
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this.userPortShowHex = new System.Windows.Forms.CheckBox();
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this.UserPortRecvCountLabel = new System.Windows.Forms.Label();
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this.内存DumpGroup = new System.Windows.Forms.GroupBox();
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this.内存DumpLayout = new System.Windows.Forms.TableLayoutPanel();
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this.内存内容 = new System.Windows.Forms.TextBox();
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this.地址长度指定Layout = new System.Windows.Forms.TableLayoutPanel();
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this.起始地址 = new System.Windows.Forms.TextBox();
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this.长度 = new System.Windows.Forms.TextBox();
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this.长度Title = new System.Windows.Forms.Label();
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this.起始地址Title = new System.Windows.Forms.Label();
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this.DUMP内存 = new System.Windows.Forms.Button();
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this.serialPort = new System.IO.Ports.SerialPort(this.components);
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this.compileGroup.SuspendLayout();
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this.tableLayoutPanel3.SuspendLayout();
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@ -66,11 +75,14 @@
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this.tableLayoutPanel5.SuspendLayout();
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this.tableLayoutPanel6.SuspendLayout();
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this.bootAddrGroup.SuspendLayout();
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this.tableLayoutPanel1.SuspendLayout();
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this.MainLayout.SuspendLayout();
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this.tableLayoutPanel2.SuspendLayout();
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this.groupBox1.SuspendLayout();
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this.tableLayoutPanel7.SuspendLayout();
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this.tableLayoutPanel8.SuspendLayout();
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this.内存DumpGroup.SuspendLayout();
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this.内存DumpLayout.SuspendLayout();
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this.地址长度指定Layout.SuspendLayout();
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this.SuspendLayout();
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//
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// fileSelectionText
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@ -83,7 +95,7 @@
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this.fileSelectionText.Margin = new System.Windows.Forms.Padding(5);
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this.fileSelectionText.Name = "fileSelectionText";
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this.fileSelectionText.ReadOnly = true;
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this.fileSelectionText.Size = new System.Drawing.Size(304, 28);
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this.fileSelectionText.Size = new System.Drawing.Size(187, 28);
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this.fileSelectionText.TabIndex = 0;
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//
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// fileSelectionBtn
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@ -92,7 +104,7 @@
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| System.Windows.Forms.AnchorStyles.Left)
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| System.Windows.Forms.AnchorStyles.Right)));
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this.fileSelectionBtn.Font = new System.Drawing.Font("宋体", 9F, System.Drawing.FontStyle.Regular, System.Drawing.GraphicsUnit.Point, ((byte)(134)));
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this.fileSelectionBtn.Location = new System.Drawing.Point(317, 3);
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this.fileSelectionBtn.Location = new System.Drawing.Point(200, 3);
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this.fileSelectionBtn.Name = "fileSelectionBtn";
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this.fileSelectionBtn.Size = new System.Drawing.Size(114, 34);
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this.fileSelectionBtn.TabIndex = 1;
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@ -108,7 +120,7 @@
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this.compileGroup.Location = new System.Drawing.Point(7, 7);
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this.compileGroup.Margin = new System.Windows.Forms.Padding(7);
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this.compileGroup.Name = "compileGroup";
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this.compileGroup.Size = new System.Drawing.Size(680, 64);
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this.compileGroup.Size = new System.Drawing.Size(563, 64);
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this.compileGroup.TabIndex = 2;
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this.compileGroup.TabStop = false;
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this.compileGroup.Text = "文件";
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@ -129,7 +141,7 @@
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this.tableLayoutPanel3.Name = "tableLayoutPanel3";
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this.tableLayoutPanel3.RowCount = 1;
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this.tableLayoutPanel3.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Percent, 50F));
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this.tableLayoutPanel3.Size = new System.Drawing.Size(674, 40);
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this.tableLayoutPanel3.Size = new System.Drawing.Size(557, 40);
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this.tableLayoutPanel3.TabIndex = 7;
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//
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// otherSaveBtn
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@ -138,7 +150,7 @@
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| System.Windows.Forms.AnchorStyles.Left)
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| System.Windows.Forms.AnchorStyles.Right)));
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this.otherSaveBtn.Font = new System.Drawing.Font("宋体", 9F, System.Drawing.FontStyle.Regular, System.Drawing.GraphicsUnit.Point, ((byte)(134)));
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this.otherSaveBtn.Location = new System.Drawing.Point(557, 3);
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this.otherSaveBtn.Location = new System.Drawing.Point(440, 3);
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this.otherSaveBtn.Name = "otherSaveBtn";
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this.otherSaveBtn.Size = new System.Drawing.Size(114, 34);
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this.otherSaveBtn.TabIndex = 5;
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@ -153,7 +165,7 @@
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| System.Windows.Forms.AnchorStyles.Right)));
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this.saveBtn.Enabled = false;
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this.saveBtn.Font = new System.Drawing.Font("宋体", 9F, System.Drawing.FontStyle.Regular, System.Drawing.GraphicsUnit.Point, ((byte)(134)));
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this.saveBtn.Location = new System.Drawing.Point(437, 3);
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this.saveBtn.Location = new System.Drawing.Point(320, 3);
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this.saveBtn.Name = "saveBtn";
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this.saveBtn.Size = new System.Drawing.Size(114, 34);
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this.saveBtn.TabIndex = 4;
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@ -172,7 +184,7 @@
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this.codeText.Multiline = true;
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this.codeText.Name = "codeText";
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this.codeText.ScrollBars = System.Windows.Forms.ScrollBars.Both;
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this.codeText.Size = new System.Drawing.Size(688, 444);
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this.codeText.Size = new System.Drawing.Size(571, 504);
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this.codeText.TabIndex = 4;
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//
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// compilePromptText
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@ -181,12 +193,12 @@
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| System.Windows.Forms.AnchorStyles.Left)
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| System.Windows.Forms.AnchorStyles.Right)));
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this.compilePromptText.Font = new System.Drawing.Font("Consolas", 9F, System.Drawing.FontStyle.Regular, System.Drawing.GraphicsUnit.Point, ((byte)(0)));
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this.compilePromptText.Location = new System.Drawing.Point(3, 531);
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this.compilePromptText.Location = new System.Drawing.Point(3, 591);
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this.compilePromptText.Multiline = true;
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this.compilePromptText.Name = "compilePromptText";
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this.compilePromptText.ReadOnly = true;
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this.compilePromptText.ScrollBars = System.Windows.Forms.ScrollBars.Both;
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this.compilePromptText.Size = new System.Drawing.Size(688, 137);
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this.compilePromptText.Size = new System.Drawing.Size(571, 156);
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this.compilePromptText.TabIndex = 3;
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//
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// HexStreamGroup
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@ -196,9 +208,9 @@
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| System.Windows.Forms.AnchorStyles.Right)));
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this.HexStreamGroup.Controls.Add(this.tableLayoutPanel4);
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this.HexStreamGroup.Font = new System.Drawing.Font("宋体", 9F, System.Drawing.FontStyle.Regular, System.Drawing.GraphicsUnit.Point, ((byte)(134)));
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this.HexStreamGroup.Location = new System.Drawing.Point(703, 3);
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this.HexStreamGroup.Location = new System.Drawing.Point(586, 3);
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this.HexStreamGroup.Name = "HexStreamGroup";
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this.HexStreamGroup.Size = new System.Drawing.Size(294, 671);
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this.HexStreamGroup.Size = new System.Drawing.Size(244, 750);
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this.HexStreamGroup.TabIndex = 5;
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this.HexStreamGroup.TabStop = false;
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this.HexStreamGroup.Text = "指令流";
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@ -219,7 +231,7 @@
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this.tableLayoutPanel4.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Absolute, 50F));
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this.tableLayoutPanel4.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Absolute, 60F));
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this.tableLayoutPanel4.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Percent, 50F));
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this.tableLayoutPanel4.Size = new System.Drawing.Size(288, 647);
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this.tableLayoutPanel4.Size = new System.Drawing.Size(238, 726);
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this.tableLayoutPanel4.TabIndex = 0;
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//
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// binText
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@ -233,7 +245,7 @@
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this.binText.Multiline = true;
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this.binText.Name = "binText";
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this.binText.ScrollBars = System.Windows.Forms.ScrollBars.Both;
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this.binText.Size = new System.Drawing.Size(282, 481);
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this.binText.Size = new System.Drawing.Size(232, 560);
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this.binText.TabIndex = 5;
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//
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// tableLayoutPanel5
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@ -248,16 +260,16 @@
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this.tableLayoutPanel5.Name = "tableLayoutPanel5";
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this.tableLayoutPanel5.RowCount = 1;
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this.tableLayoutPanel5.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Percent, 100F));
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this.tableLayoutPanel5.Size = new System.Drawing.Size(282, 44);
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this.tableLayoutPanel5.Size = new System.Drawing.Size(232, 44);
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this.tableLayoutPanel5.TabIndex = 0;
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//
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// saveVerilog
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//
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this.saveVerilog.Dock = System.Windows.Forms.DockStyle.Fill;
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this.saveVerilog.Font = new System.Drawing.Font("宋体", 9F, System.Drawing.FontStyle.Regular, System.Drawing.GraphicsUnit.Point, ((byte)(134)));
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this.saveVerilog.Location = new System.Drawing.Point(87, 3);
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this.saveVerilog.Location = new System.Drawing.Point(72, 3);
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this.saveVerilog.Name = "saveVerilog";
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this.saveVerilog.Size = new System.Drawing.Size(192, 38);
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this.saveVerilog.Size = new System.Drawing.Size(157, 38);
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this.saveVerilog.TabIndex = 2;
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this.saveVerilog.Text = "保存指令流 (Verilog)";
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this.saveVerilog.UseVisualStyleBackColor = true;
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@ -269,7 +281,7 @@
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this.compileBtn.Font = new System.Drawing.Font("宋体", 9F, System.Drawing.FontStyle.Regular, System.Drawing.GraphicsUnit.Point, ((byte)(134)));
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this.compileBtn.Location = new System.Drawing.Point(3, 3);
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this.compileBtn.Name = "compileBtn";
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this.compileBtn.Size = new System.Drawing.Size(78, 38);
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this.compileBtn.Size = new System.Drawing.Size(63, 38);
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this.compileBtn.TabIndex = 0;
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this.compileBtn.Text = "汇编";
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this.compileBtn.UseVisualStyleBackColor = true;
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@ -287,16 +299,16 @@
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this.tableLayoutPanel6.Name = "tableLayoutPanel6";
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this.tableLayoutPanel6.RowCount = 1;
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this.tableLayoutPanel6.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Percent, 50F));
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this.tableLayoutPanel6.Size = new System.Drawing.Size(282, 44);
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this.tableLayoutPanel6.Size = new System.Drawing.Size(232, 44);
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this.tableLayoutPanel6.TabIndex = 1;
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//
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// programBtn
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//
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this.programBtn.Dock = System.Windows.Forms.DockStyle.Fill;
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this.programBtn.Font = new System.Drawing.Font("宋体", 9F, System.Drawing.FontStyle.Regular, System.Drawing.GraphicsUnit.Point, ((byte)(134)));
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this.programBtn.Location = new System.Drawing.Point(191, 3);
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this.programBtn.Location = new System.Drawing.Point(157, 3);
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this.programBtn.Name = "programBtn";
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this.programBtn.Size = new System.Drawing.Size(88, 38);
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this.programBtn.Size = new System.Drawing.Size(72, 38);
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this.programBtn.TabIndex = 3;
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this.programBtn.Text = "烧写";
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this.programBtn.UseVisualStyleBackColor = true;
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@ -310,7 +322,7 @@
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this.portSelectionBox.FormattingEnabled = true;
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this.portSelectionBox.Location = new System.Drawing.Point(3, 3);
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this.portSelectionBox.Name = "portSelectionBox";
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this.portSelectionBox.Size = new System.Drawing.Size(182, 28);
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this.portSelectionBox.Size = new System.Drawing.Size(148, 28);
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this.portSelectionBox.TabIndex = 0;
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this.portSelectionBox.DropDown += new System.EventHandler(this.InitializeCurrentPort);
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//
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@ -320,10 +332,10 @@
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this.bootAddrGroup.Dock = System.Windows.Forms.DockStyle.Fill;
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this.bootAddrGroup.Location = new System.Drawing.Point(3, 103);
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this.bootAddrGroup.Name = "bootAddrGroup";
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this.bootAddrGroup.Size = new System.Drawing.Size(282, 54);
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this.bootAddrGroup.Size = new System.Drawing.Size(232, 54);
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this.bootAddrGroup.TabIndex = 6;
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this.bootAddrGroup.TabStop = false;
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this.bootAddrGroup.Text = "boot地址";
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this.bootAddrGroup.Text = "BOOT地址";
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//
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// bootAddrTextBox
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//
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@ -332,28 +344,30 @@
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this.bootAddrTextBox.Location = new System.Drawing.Point(3, 21);
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this.bootAddrTextBox.Margin = new System.Windows.Forms.Padding(5);
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this.bootAddrTextBox.Name = "bootAddrTextBox";
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this.bootAddrTextBox.Size = new System.Drawing.Size(276, 28);
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this.bootAddrTextBox.Size = new System.Drawing.Size(226, 28);
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this.bootAddrTextBox.TabIndex = 1;
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this.bootAddrTextBox.Text = "00008000";
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this.bootAddrTextBox.TextAlign = System.Windows.Forms.HorizontalAlignment.Right;
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//
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// tableLayoutPanel1
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// MainLayout
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//
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this.tableLayoutPanel1.ColumnCount = 3;
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this.tableLayoutPanel1.ColumnStyles.Add(new System.Windows.Forms.ColumnStyle(System.Windows.Forms.SizeType.Percent, 100F));
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this.tableLayoutPanel1.ColumnStyles.Add(new System.Windows.Forms.ColumnStyle(System.Windows.Forms.SizeType.Absolute, 300F));
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this.tableLayoutPanel1.ColumnStyles.Add(new System.Windows.Forms.ColumnStyle(System.Windows.Forms.SizeType.Absolute, 300F));
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this.tableLayoutPanel1.Controls.Add(this.HexStreamGroup, 1, 0);
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this.tableLayoutPanel1.Controls.Add(this.tableLayoutPanel2, 0, 0);
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this.tableLayoutPanel1.Controls.Add(this.groupBox1, 2, 0);
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this.tableLayoutPanel1.Dock = System.Windows.Forms.DockStyle.Fill;
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this.tableLayoutPanel1.Location = new System.Drawing.Point(0, 0);
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this.tableLayoutPanel1.Name = "tableLayoutPanel1";
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this.tableLayoutPanel1.RowCount = 1;
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this.tableLayoutPanel1.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Percent, 100F));
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this.tableLayoutPanel1.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Absolute, 20F));
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this.tableLayoutPanel1.Size = new System.Drawing.Size(1300, 677);
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this.tableLayoutPanel1.TabIndex = 6;
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this.MainLayout.ColumnCount = 4;
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this.MainLayout.ColumnStyles.Add(new System.Windows.Forms.ColumnStyle(System.Windows.Forms.SizeType.Percent, 100F));
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this.MainLayout.ColumnStyles.Add(new System.Windows.Forms.ColumnStyle(System.Windows.Forms.SizeType.Absolute, 250F));
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this.MainLayout.ColumnStyles.Add(new System.Windows.Forms.ColumnStyle(System.Windows.Forms.SizeType.Absolute, 250F));
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this.MainLayout.ColumnStyles.Add(new System.Windows.Forms.ColumnStyle(System.Windows.Forms.SizeType.Absolute, 380F));
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this.MainLayout.Controls.Add(this.HexStreamGroup, 1, 0);
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this.MainLayout.Controls.Add(this.tableLayoutPanel2, 0, 0);
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this.MainLayout.Controls.Add(this.groupBox1, 2, 0);
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this.MainLayout.Controls.Add(this.内存DumpGroup, 3, 0);
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this.MainLayout.Dock = System.Windows.Forms.DockStyle.Fill;
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this.MainLayout.Location = new System.Drawing.Point(0, 0);
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this.MainLayout.Name = "MainLayout";
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this.MainLayout.RowCount = 1;
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this.MainLayout.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Percent, 100F));
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this.MainLayout.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Absolute, 20F));
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this.MainLayout.Size = new System.Drawing.Size(1463, 756);
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this.MainLayout.TabIndex = 6;
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//
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// tableLayoutPanel2
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//
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@ -370,16 +384,16 @@
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this.tableLayoutPanel2.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Absolute, 78F));
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this.tableLayoutPanel2.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Percent, 76F));
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this.tableLayoutPanel2.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Percent, 24F));
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this.tableLayoutPanel2.Size = new System.Drawing.Size(694, 671);
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this.tableLayoutPanel2.Size = new System.Drawing.Size(577, 750);
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this.tableLayoutPanel2.TabIndex = 6;
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//
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// groupBox1
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//
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this.groupBox1.Controls.Add(this.tableLayoutPanel7);
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this.groupBox1.Dock = System.Windows.Forms.DockStyle.Fill;
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this.groupBox1.Location = new System.Drawing.Point(1003, 3);
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this.groupBox1.Location = new System.Drawing.Point(836, 3);
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this.groupBox1.Name = "groupBox1";
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this.groupBox1.Size = new System.Drawing.Size(294, 671);
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this.groupBox1.Size = new System.Drawing.Size(244, 750);
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this.groupBox1.TabIndex = 7;
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this.groupBox1.TabStop = false;
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this.groupBox1.Text = "串口查看";
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@ -398,7 +412,7 @@
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this.tableLayoutPanel7.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Absolute, 90F));
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this.tableLayoutPanel7.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Percent, 50F));
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this.tableLayoutPanel7.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Absolute, 40F));
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this.tableLayoutPanel7.Size = new System.Drawing.Size(288, 647);
|
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this.tableLayoutPanel7.Size = new System.Drawing.Size(238, 726);
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this.tableLayoutPanel7.TabIndex = 0;
|
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//
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// userPortTextBox
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@ -412,7 +426,7 @@
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this.userPortTextBox.Multiline = true;
|
||||
this.userPortTextBox.Name = "userPortTextBox";
|
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this.userPortTextBox.ScrollBars = System.Windows.Forms.ScrollBars.Both;
|
||||
this.userPortTextBox.Size = new System.Drawing.Size(282, 511);
|
||||
this.userPortTextBox.Size = new System.Drawing.Size(232, 590);
|
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this.userPortTextBox.TabIndex = 6;
|
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//
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// tableLayoutPanel8
|
||||
@ -429,16 +443,16 @@
|
||||
this.tableLayoutPanel8.RowCount = 2;
|
||||
this.tableLayoutPanel8.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Percent, 50F));
|
||||
this.tableLayoutPanel8.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Percent, 50F));
|
||||
this.tableLayoutPanel8.Size = new System.Drawing.Size(282, 84);
|
||||
this.tableLayoutPanel8.Size = new System.Drawing.Size(232, 84);
|
||||
this.tableLayoutPanel8.TabIndex = 2;
|
||||
//
|
||||
// userPortClearBtn
|
||||
//
|
||||
this.userPortClearBtn.Dock = System.Windows.Forms.DockStyle.Fill;
|
||||
this.userPortClearBtn.Font = new System.Drawing.Font("宋体", 9F, System.Drawing.FontStyle.Regular, System.Drawing.GraphicsUnit.Point, ((byte)(134)));
|
||||
this.userPortClearBtn.Location = new System.Drawing.Point(191, 45);
|
||||
this.userPortClearBtn.Location = new System.Drawing.Point(157, 45);
|
||||
this.userPortClearBtn.Name = "userPortClearBtn";
|
||||
this.userPortClearBtn.Size = new System.Drawing.Size(88, 36);
|
||||
this.userPortClearBtn.Size = new System.Drawing.Size(72, 36);
|
||||
this.userPortClearBtn.TabIndex = 4;
|
||||
this.userPortClearBtn.Text = "清空";
|
||||
this.userPortClearBtn.UseVisualStyleBackColor = true;
|
||||
@ -448,9 +462,9 @@
|
||||
//
|
||||
this.userPortOpenCloseBtn.Dock = System.Windows.Forms.DockStyle.Fill;
|
||||
this.userPortOpenCloseBtn.Font = new System.Drawing.Font("宋体", 9F, System.Drawing.FontStyle.Regular, System.Drawing.GraphicsUnit.Point, ((byte)(134)));
|
||||
this.userPortOpenCloseBtn.Location = new System.Drawing.Point(191, 3);
|
||||
this.userPortOpenCloseBtn.Location = new System.Drawing.Point(157, 3);
|
||||
this.userPortOpenCloseBtn.Name = "userPortOpenCloseBtn";
|
||||
this.userPortOpenCloseBtn.Size = new System.Drawing.Size(88, 36);
|
||||
this.userPortOpenCloseBtn.Size = new System.Drawing.Size(72, 36);
|
||||
this.userPortOpenCloseBtn.TabIndex = 3;
|
||||
this.userPortOpenCloseBtn.Text = "打开";
|
||||
this.userPortOpenCloseBtn.UseVisualStyleBackColor = true;
|
||||
@ -462,7 +476,7 @@
|
||||
this.userPortShowHex.Dock = System.Windows.Forms.DockStyle.Fill;
|
||||
this.userPortShowHex.Location = new System.Drawing.Point(3, 45);
|
||||
this.userPortShowHex.Name = "userPortShowHex";
|
||||
this.userPortShowHex.Size = new System.Drawing.Size(182, 36);
|
||||
this.userPortShowHex.Size = new System.Drawing.Size(148, 36);
|
||||
this.userPortShowHex.TabIndex = 5;
|
||||
this.userPortShowHex.Text = "十六进制显示";
|
||||
this.userPortShowHex.UseVisualStyleBackColor = true;
|
||||
@ -471,13 +485,132 @@
|
||||
//
|
||||
this.UserPortRecvCountLabel.AutoSize = true;
|
||||
this.UserPortRecvCountLabel.Dock = System.Windows.Forms.DockStyle.Fill;
|
||||
this.UserPortRecvCountLabel.Location = new System.Drawing.Point(3, 610);
|
||||
this.UserPortRecvCountLabel.Location = new System.Drawing.Point(3, 689);
|
||||
this.UserPortRecvCountLabel.Margin = new System.Windows.Forms.Padding(3);
|
||||
this.UserPortRecvCountLabel.Name = "UserPortRecvCountLabel";
|
||||
this.UserPortRecvCountLabel.Size = new System.Drawing.Size(282, 34);
|
||||
this.UserPortRecvCountLabel.Size = new System.Drawing.Size(232, 34);
|
||||
this.UserPortRecvCountLabel.TabIndex = 7;
|
||||
this.UserPortRecvCountLabel.Text = "接收: 0 B";
|
||||
//
|
||||
// 内存DumpGroup
|
||||
//
|
||||
this.内存DumpGroup.Controls.Add(this.内存DumpLayout);
|
||||
this.内存DumpGroup.Dock = System.Windows.Forms.DockStyle.Fill;
|
||||
this.内存DumpGroup.Location = new System.Drawing.Point(1086, 3);
|
||||
this.内存DumpGroup.Name = "内存DumpGroup";
|
||||
this.内存DumpGroup.Size = new System.Drawing.Size(374, 750);
|
||||
this.内存DumpGroup.TabIndex = 8;
|
||||
this.内存DumpGroup.TabStop = false;
|
||||
this.内存DumpGroup.Text = "内存DUMP";
|
||||
//
|
||||
// 内存DumpLayout
|
||||
//
|
||||
this.内存DumpLayout.ColumnCount = 1;
|
||||
this.内存DumpLayout.ColumnStyles.Add(new System.Windows.Forms.ColumnStyle(System.Windows.Forms.SizeType.Percent, 100F));
|
||||
this.内存DumpLayout.ColumnStyles.Add(new System.Windows.Forms.ColumnStyle(System.Windows.Forms.SizeType.Absolute, 20F));
|
||||
this.内存DumpLayout.Controls.Add(this.内存内容, 0, 2);
|
||||
this.内存DumpLayout.Controls.Add(this.地址长度指定Layout, 0, 0);
|
||||
this.内存DumpLayout.Controls.Add(this.DUMP内存, 0, 1);
|
||||
this.内存DumpLayout.Dock = System.Windows.Forms.DockStyle.Fill;
|
||||
this.内存DumpLayout.Location = new System.Drawing.Point(3, 21);
|
||||
this.内存DumpLayout.Name = "内存DumpLayout";
|
||||
this.内存DumpLayout.RowCount = 3;
|
||||
this.内存DumpLayout.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Absolute, 85F));
|
||||
this.内存DumpLayout.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Absolute, 40F));
|
||||
this.内存DumpLayout.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Percent, 100F));
|
||||
this.内存DumpLayout.Size = new System.Drawing.Size(368, 726);
|
||||
this.内存DumpLayout.TabIndex = 1;
|
||||
//
|
||||
// 内存内容
|
||||
//
|
||||
this.内存内容.Anchor = ((System.Windows.Forms.AnchorStyles)((((System.Windows.Forms.AnchorStyles.Top | System.Windows.Forms.AnchorStyles.Bottom)
|
||||
| System.Windows.Forms.AnchorStyles.Left)
|
||||
| System.Windows.Forms.AnchorStyles.Right)));
|
||||
this.内存内容.Font = new System.Drawing.Font("Consolas", 12F, System.Drawing.FontStyle.Regular, System.Drawing.GraphicsUnit.Point, ((byte)(0)));
|
||||
this.内存内容.ForeColor = System.Drawing.Color.FromArgb(((int)(((byte)(0)))), ((int)(((byte)(0)))), ((int)(((byte)(192)))));
|
||||
this.内存内容.Location = new System.Drawing.Point(3, 128);
|
||||
this.内存内容.Multiline = true;
|
||||
this.内存内容.Name = "内存内容";
|
||||
this.内存内容.ReadOnly = true;
|
||||
this.内存内容.ScrollBars = System.Windows.Forms.ScrollBars.Both;
|
||||
this.内存内容.Size = new System.Drawing.Size(362, 595);
|
||||
this.内存内容.TabIndex = 6;
|
||||
//
|
||||
// 地址长度指定Layout
|
||||
//
|
||||
this.地址长度指定Layout.ColumnCount = 2;
|
||||
this.地址长度指定Layout.ColumnStyles.Add(new System.Windows.Forms.ColumnStyle(System.Windows.Forms.SizeType.Percent, 50F));
|
||||
this.地址长度指定Layout.ColumnStyles.Add(new System.Windows.Forms.ColumnStyle(System.Windows.Forms.SizeType.Percent, 50F));
|
||||
this.地址长度指定Layout.Controls.Add(this.起始地址, 1, 0);
|
||||
this.地址长度指定Layout.Controls.Add(this.长度, 1, 1);
|
||||
this.地址长度指定Layout.Controls.Add(this.长度Title, 0, 1);
|
||||
this.地址长度指定Layout.Controls.Add(this.起始地址Title, 0, 0);
|
||||
this.地址长度指定Layout.Dock = System.Windows.Forms.DockStyle.Fill;
|
||||
this.地址长度指定Layout.Location = new System.Drawing.Point(3, 3);
|
||||
this.地址长度指定Layout.Name = "地址长度指定Layout";
|
||||
this.地址长度指定Layout.RowCount = 2;
|
||||
this.地址长度指定Layout.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Percent, 50F));
|
||||
this.地址长度指定Layout.RowStyles.Add(new System.Windows.Forms.RowStyle(System.Windows.Forms.SizeType.Percent, 50F));
|
||||
this.地址长度指定Layout.Size = new System.Drawing.Size(362, 79);
|
||||
this.地址长度指定Layout.TabIndex = 0;
|
||||
//
|
||||
// 起始地址
|
||||
//
|
||||
this.起始地址.Dock = System.Windows.Forms.DockStyle.Fill;
|
||||
this.起始地址.Font = new System.Drawing.Font("宋体", 10.8F, System.Drawing.FontStyle.Regular, System.Drawing.GraphicsUnit.Point, ((byte)(134)));
|
||||
this.起始地址.Location = new System.Drawing.Point(186, 5);
|
||||
this.起始地址.Margin = new System.Windows.Forms.Padding(5);
|
||||
this.起始地址.Name = "起始地址";
|
||||
this.起始地址.Size = new System.Drawing.Size(171, 28);
|
||||
this.起始地址.TabIndex = 4;
|
||||
this.起始地址.Text = "00010000";
|
||||
this.起始地址.TextAlign = System.Windows.Forms.HorizontalAlignment.Right;
|
||||
//
|
||||
// 长度
|
||||
//
|
||||
this.长度.Dock = System.Windows.Forms.DockStyle.Fill;
|
||||
this.长度.Font = new System.Drawing.Font("宋体", 10.8F, System.Drawing.FontStyle.Regular, System.Drawing.GraphicsUnit.Point, ((byte)(134)));
|
||||
this.长度.Location = new System.Drawing.Point(186, 44);
|
||||
this.长度.Margin = new System.Windows.Forms.Padding(5);
|
||||
this.长度.Name = "长度";
|
||||
this.长度.Size = new System.Drawing.Size(171, 28);
|
||||
this.长度.TabIndex = 3;
|
||||
this.长度.Text = "80";
|
||||
this.长度.TextAlign = System.Windows.Forms.HorizontalAlignment.Right;
|
||||
//
|
||||
// 长度Title
|
||||
//
|
||||
this.长度Title.AutoSize = true;
|
||||
this.长度Title.Dock = System.Windows.Forms.DockStyle.Fill;
|
||||
this.长度Title.Location = new System.Drawing.Point(3, 39);
|
||||
this.长度Title.Name = "长度Title";
|
||||
this.长度Title.Size = new System.Drawing.Size(175, 40);
|
||||
this.长度Title.TabIndex = 2;
|
||||
this.长度Title.Text = "长度(16进制):";
|
||||
this.长度Title.TextAlign = System.Drawing.ContentAlignment.MiddleCenter;
|
||||
//
|
||||
// 起始地址Title
|
||||
//
|
||||
this.起始地址Title.AutoSize = true;
|
||||
this.起始地址Title.Dock = System.Windows.Forms.DockStyle.Fill;
|
||||
this.起始地址Title.Location = new System.Drawing.Point(3, 0);
|
||||
this.起始地址Title.Name = "起始地址Title";
|
||||
this.起始地址Title.Size = new System.Drawing.Size(175, 39);
|
||||
this.起始地址Title.TabIndex = 0;
|
||||
this.起始地址Title.Text = "起始地址(16进制)";
|
||||
this.起始地址Title.TextAlign = System.Drawing.ContentAlignment.MiddleCenter;
|
||||
//
|
||||
// DUMP内存
|
||||
//
|
||||
this.DUMP内存.Dock = System.Windows.Forms.DockStyle.Fill;
|
||||
this.DUMP内存.Location = new System.Drawing.Point(3, 88);
|
||||
this.DUMP内存.Name = "DUMP内存";
|
||||
this.DUMP内存.Size = new System.Drawing.Size(362, 34);
|
||||
this.DUMP内存.TabIndex = 1;
|
||||
this.DUMP内存.Text = "DUMP内存";
|
||||
this.DUMP内存.UseVisualStyleBackColor = true;
|
||||
this.DUMP内存.Click += new System.EventHandler(this.DUMP内存_Click);
|
||||
//
|
||||
// serialPort
|
||||
//
|
||||
this.serialPort.BaudRate = 115200;
|
||||
@ -489,8 +622,8 @@
|
||||
//
|
||||
this.AutoScaleDimensions = new System.Drawing.SizeF(8F, 15F);
|
||||
this.AutoScaleMode = System.Windows.Forms.AutoScaleMode.Font;
|
||||
this.ClientSize = new System.Drawing.Size(1300, 677);
|
||||
this.Controls.Add(this.tableLayoutPanel1);
|
||||
this.ClientSize = new System.Drawing.Size(1463, 756);
|
||||
this.Controls.Add(this.MainLayout);
|
||||
this.Name = "MainForm";
|
||||
this.Text = "USTCRVSoC 辅助工具";
|
||||
this.compileGroup.ResumeLayout(false);
|
||||
@ -503,7 +636,7 @@
|
||||
this.tableLayoutPanel6.ResumeLayout(false);
|
||||
this.bootAddrGroup.ResumeLayout(false);
|
||||
this.bootAddrGroup.PerformLayout();
|
||||
this.tableLayoutPanel1.ResumeLayout(false);
|
||||
this.MainLayout.ResumeLayout(false);
|
||||
this.tableLayoutPanel2.ResumeLayout(false);
|
||||
this.tableLayoutPanel2.PerformLayout();
|
||||
this.groupBox1.ResumeLayout(false);
|
||||
@ -511,6 +644,11 @@
|
||||
this.tableLayoutPanel7.PerformLayout();
|
||||
this.tableLayoutPanel8.ResumeLayout(false);
|
||||
this.tableLayoutPanel8.PerformLayout();
|
||||
this.内存DumpGroup.ResumeLayout(false);
|
||||
this.内存DumpLayout.ResumeLayout(false);
|
||||
this.内存DumpLayout.PerformLayout();
|
||||
this.地址长度指定Layout.ResumeLayout(false);
|
||||
this.地址长度指定Layout.PerformLayout();
|
||||
this.ResumeLayout(false);
|
||||
|
||||
}
|
||||
@ -524,7 +662,7 @@
|
||||
private System.Windows.Forms.TextBox codeText;
|
||||
private System.Windows.Forms.Button saveBtn;
|
||||
private System.Windows.Forms.GroupBox HexStreamGroup;
|
||||
private System.Windows.Forms.TableLayoutPanel tableLayoutPanel1;
|
||||
private System.Windows.Forms.TableLayoutPanel MainLayout;
|
||||
private System.Windows.Forms.TableLayoutPanel tableLayoutPanel2;
|
||||
private System.Windows.Forms.TableLayoutPanel tableLayoutPanel3;
|
||||
private System.Windows.Forms.Button otherSaveBtn;
|
||||
@ -547,6 +685,15 @@
|
||||
private System.Windows.Forms.Button userPortClearBtn;
|
||||
private System.Windows.Forms.CheckBox userPortShowHex;
|
||||
private System.Windows.Forms.Label UserPortRecvCountLabel;
|
||||
private System.Windows.Forms.GroupBox 内存DumpGroup;
|
||||
private System.Windows.Forms.TableLayoutPanel 内存DumpLayout;
|
||||
private System.Windows.Forms.TextBox 内存内容;
|
||||
private System.Windows.Forms.TableLayoutPanel 地址长度指定Layout;
|
||||
private System.Windows.Forms.TextBox 起始地址;
|
||||
private System.Windows.Forms.TextBox 长度;
|
||||
private System.Windows.Forms.Label 长度Title;
|
||||
private System.Windows.Forms.Label 起始地址Title;
|
||||
private System.Windows.Forms.Button DUMP内存;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,26 +1,20 @@
|
||||
using System;
|
||||
using System.IO;
|
||||
using System.Collections.Generic;
|
||||
using System.ComponentModel;
|
||||
using System.Data;
|
||||
using System.Drawing;
|
||||
using System.Linq;
|
||||
using System.Text;
|
||||
using System.Threading.Tasks;
|
||||
using System.Windows.Forms;
|
||||
using System.IO.Ports;
|
||||
using System.Drawing;
|
||||
using System.Text;
|
||||
using System.Windows.Forms;
|
||||
|
||||
|
||||
namespace USTCRVSoC_tool
|
||||
{
|
||||
public partial class MainForm : Form
|
||||
{
|
||||
private const string RISCV_TOOLS_PATH = ".\\riscv32-elf-tools-windows\\";
|
||||
private const string VerilogHead = "module instr_rom(\n input logic clk, rst_n,\n naive_bus.slave bus\n);\nlocalparam INSTR_CNT = 30'd";
|
||||
private const string VerilogMid = ";\nwire [0:INSTR_CNT-1] [31:0] instr_rom_cell = {\n";
|
||||
private const string VerilogTail = "};\n\nlogic [29:0] cell_rd_addr;\n\nassign bus.rd_gnt = bus.rd_req;\nassign bus.wr_gnt = bus.wr_req;\nassign cell_rd_addr = bus.rd_addr[31:2];\nalways @ (posedge clk or negedge rst_n)\n if(~rst_n)\n bus.rd_data <= 0;\n else begin\n if(bus.rd_req)\n bus.rd_data <= (cell_rd_addr>=INSTR_CNT) ? 0 : instr_rom_cell[cell_rd_addr];\n else\n bus.rd_data <= 0;\n end\n\nendmodule\n\n";
|
||||
private uint _userPortCount;
|
||||
private const string RISCV_TOOLS_PATH = ".\\riscv32-elf-tools-windows\\"; // RISC-V工具链的路径
|
||||
|
||||
private uint userPortCount
|
||||
#region 控制接收字节数计数
|
||||
private uint _userPortCount;
|
||||
private uint userPortCount // 接收字节数计数属性
|
||||
{
|
||||
get
|
||||
{
|
||||
@ -32,13 +26,15 @@ namespace USTCRVSoC_tool
|
||||
changeCountText(String.Format("接收: {0:D} B", _userPortCount));
|
||||
}
|
||||
}
|
||||
#endregion
|
||||
|
||||
public MainForm()
|
||||
public MainForm() // 窗体构造函数
|
||||
{
|
||||
InitializeComponent();
|
||||
InitializeCurrentPort(null, null);
|
||||
}
|
||||
|
||||
#region 自动查照存在的串口
|
||||
private void InitializeCurrentPort(object sender, EventArgs e)
|
||||
{
|
||||
string[] ports = SerialPort.GetPortNames();
|
||||
@ -53,7 +49,9 @@ namespace USTCRVSoC_tool
|
||||
compilePromptText.Text = "未找到串口，请插入设备，或者检查串口驱动是否安装";
|
||||
}
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region 打开、保存、另存 汇编代码文件
|
||||
private void fileSelectionBtn_Click(object sender, EventArgs e)
|
||||
{
|
||||
OpenFileDialog openFileDialog = new OpenFileDialog();
|
||||
@ -111,8 +109,10 @@ namespace USTCRVSoC_tool
|
||||
}
|
||||
}
|
||||
}
|
||||
#endregion
|
||||
|
||||
public bool RunCmd(string path, string command, ref string msg)
|
||||
#region 汇编
|
||||
public bool RunCmd(string path, string command, ref string msg) // 调用 CMD 运行一个命令
|
||||
{
|
||||
try
|
||||
{
|
||||
@ -143,8 +143,7 @@ namespace USTCRVSoC_tool
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
private string dumpBin(string bin_file_path)
|
||||
private string dumpBin(string bin_file_path) // 读取汇编出的.bin 文件并调整字节序、转换为一行一行的指令
|
||||
{
|
||||
StringBuilder strbuild = new StringBuilder();
|
||||
byte[] bin = System.IO.File.ReadAllBytes(bin_file_path);
|
||||
@ -156,8 +155,7 @@ namespace USTCRVSoC_tool
|
||||
}
|
||||
return strbuild.ToString();
|
||||
}
|
||||
|
||||
private void compileBtn_Click(object sender, EventArgs e)
|
||||
private void compileBtn_Click(object sender, EventArgs e) // 点击“汇编”按钮时，完成一系列CMD命令，并把编译结果读入到 binText 这个控件里
|
||||
{
|
||||
bool stat;
|
||||
string msg = "";
|
||||
@ -226,6 +224,12 @@ namespace USTCRVSoC_tool
|
||||
return;
|
||||
}
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region 生成 Verilog InstrROM 代码
|
||||
private const string VerilogHead = "module instr_rom(\n input logic clk, rst_n,\n naive_bus.slave bus\n);\nlocalparam INSTR_CNT = 30'd";
|
||||
private const string VerilogMid = ";\nwire [0:INSTR_CNT-1] [31:0] instr_rom_cell = {\n";
|
||||
private const string VerilogTail = "};\n\nlogic [29:0] cell_rd_addr;\n\nassign bus.rd_gnt = bus.rd_req;\nassign bus.wr_gnt = bus.wr_req;\nassign cell_rd_addr = bus.rd_addr[31:2];\nalways @ (posedge clk or negedge rst_n)\n if(~rst_n)\n bus.rd_data <= 0;\n else begin\n if(bus.rd_req)\n bus.rd_data <= (cell_rd_addr>=INSTR_CNT) ? 0 : instr_rom_cell[cell_rd_addr];\n else\n bus.rd_data <= 0;\n end\n\nendmodule\n\n";
|
||||
|
||||
private string genVerilogRom()
|
||||
{
|
||||
@ -271,24 +275,32 @@ namespace USTCRVSoC_tool
|
||||
}
|
||||
}
|
||||
}
|
||||
#endregion
|
||||
|
||||
private bool serialSessionA(string send, ref string response)
|
||||
#region 串口的命令函数
|
||||
private bool serialSessionA(string send, ref string response) // 发送一个命令并得到响应字符串
|
||||
{
|
||||
return serialSessionTry(send, ref response, "");
|
||||
}
|
||||
|
||||
private bool serialSessionB(string send, string respectResponse)
|
||||
private bool serialSessionB(string send, string respectResponse) // 发送一个命令并等待指定的响应字符串到来
|
||||
{
|
||||
string response = "";
|
||||
return serialSessionTry(send, ref response, respectResponse);
|
||||
}
|
||||
|
||||
private bool serialSessionTry(string send, ref string response, string respectResponse, int try_time = 3)
|
||||
private bool serialSessionTry(string send, ref string response, string respectResponse, int try_time = 3) // 多次请求全部失败时，返回失败，否则返回成功
|
||||
{
|
||||
for (int i = 0; i < try_time; i++)
|
||||
{
|
||||
try { serialPort.ReadExisting(); }// 清空接收缓冲区
|
||||
catch { }
|
||||
if (serialSend(send))
|
||||
{
|
||||
if (serialRead(ref response, respectResponse))
|
||||
return true;
|
||||
}
|
||||
}
|
||||
compilePromptText.AppendText(" *** 串口调试多次尝试失败 ***\r\n");
|
||||
return false;
|
||||
}
|
||||
@ -331,20 +343,61 @@ namespace USTCRVSoC_tool
|
||||
compilePromptText.AppendText(" response: *** 超时 ***\r\n" + response);
|
||||
return false;
|
||||
}
|
||||
#endregion
|
||||
|
||||
private uint getBootAddr()
|
||||
#region 串口打开
|
||||
private bool refreshSerial()
|
||||
{
|
||||
return Convert.ToUInt32(bootAddrTextBox.Text, 16);
|
||||
if (serialPort.IsOpen)
|
||||
serialPort.Close();
|
||||
try
|
||||
{
|
||||
serialPort.PortName = portSelectionBox.Text;
|
||||
serialPort.Open();
|
||||
}
|
||||
catch (Exception ex)
|
||||
{
|
||||
compilePromptText.AppendText(" *** 打开串口出错 ***\r\n " + ex.Message);
|
||||
refreshPortStatus();
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
private void programBtn_Click(object sender, EventArgs e)
|
||||
private void refreshPortStatus()
|
||||
{
|
||||
if (serialPort.IsOpen)
|
||||
userPortOpenCloseBtn.Text = "关闭";
|
||||
else
|
||||
userPortOpenCloseBtn.Text = "打开";
|
||||
}
|
||||
private void userPortOpenCloseBtn_Click(object sender, EventArgs e)
|
||||
{
|
||||
if (userPortOpenCloseBtn.Text == "打开")
|
||||
{
|
||||
compilePromptText.Clear();
|
||||
refreshSerial();
|
||||
serialSessionB("s", "debug");
|
||||
serialSessionB("o", "user");
|
||||
}
|
||||
else
|
||||
{
|
||||
serialPort.Close();
|
||||
}
|
||||
refreshPortStatus();
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region 烧录程序
|
||||
private void programBtn_Click(object sender, EventArgs e) // 烧录程序
|
||||
{
|
||||
enableUartDisplay = false;
|
||||
userPortTextBox.Clear();
|
||||
compilePromptText.Clear();
|
||||
|
||||
uint boot_addr;
|
||||
try
|
||||
{
|
||||
boot_addr = getBootAddr();
|
||||
boot_addr = Convert.ToUInt32(bootAddrTextBox.Text, 16);
|
||||
}
|
||||
catch (Exception ex)
|
||||
{
|
||||
@ -352,26 +405,11 @@ namespace USTCRVSoC_tool
|
||||
return;
|
||||
}
|
||||
|
||||
if (!serialPort.IsOpen)
|
||||
{
|
||||
serialPort.PortName = portSelectionBox.Text;
|
||||
try
|
||||
{
|
||||
serialPort.Open();
|
||||
}
|
||||
catch (Exception ex)
|
||||
{
|
||||
compilePromptText.AppendText(" *** 打开串口出错 ***\r\n " + ex.Message);
|
||||
refreshPortStatus();
|
||||
return;
|
||||
}
|
||||
}
|
||||
refreshPortStatus();
|
||||
if (!refreshSerial())
|
||||
return;
|
||||
|
||||
if (!serialSessionB("s", "debug"))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
uint index = 0;
|
||||
foreach (string line in binText.Text.Split())
|
||||
@ -383,49 +421,74 @@ namespace USTCRVSoC_tool
|
||||
index++;
|
||||
|
||||
if (!serialSessionB(send_str, "wr done"))
|
||||
{
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
if (!serialSessionB(string.Format("r{0:x8}", boot_addr), "rst done"))
|
||||
return;
|
||||
|
||||
compilePromptText.AppendText(" *** 烧录完成 ***\r\n");
|
||||
try { serialPort.ReadExisting(); }// 清空接收缓冲区
|
||||
catch { }
|
||||
userPortTextBox.Clear();
|
||||
enableUartDisplay = true;
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region DUMP内存
|
||||
private void DUMP内存_Click(object sender, EventArgs e) // 查看内存
|
||||
{
|
||||
enableUartDisplay = false;
|
||||
userPortTextBox.Clear();
|
||||
compilePromptText.Clear();
|
||||
|
||||
uint start, len;
|
||||
try
|
||||
{
|
||||
start = Convert.ToUInt32(起始地址.Text, 16);
|
||||
len = Convert.ToUInt32(长度.Text, 16);
|
||||
}
|
||||
catch (Exception ex)
|
||||
{
|
||||
compilePromptText.AppendText(" *** 起始地址格式有误 ***\r\n " + ex.Message);
|
||||
return;
|
||||
}
|
||||
|
||||
compilePromptText.AppendText(" *** 烧录成功 ***\r\n");
|
||||
}
|
||||
|
||||
private void userPortOpenCloseBtn_Click(object sender, EventArgs e)
|
||||
{
|
||||
if (userPortOpenCloseBtn.Text == "打开")
|
||||
start = 4 * (start / 4); // 起始地址自动与4对齐
|
||||
if (len > 0x1000)
|
||||
{
|
||||
serialPort.PortName = portSelectionBox.Text;
|
||||
try
|
||||
{
|
||||
serialPort.Open();
|
||||
userPortCount = 0;
|
||||
}
|
||||
catch (Exception ex)
|
||||
{
|
||||
compilePromptText.AppendText(" *** 打开串口出错 ***\r\n " + ex.Message);
|
||||
}
|
||||
compilePromptText.AppendText(" *** 长度不能大于0x1000 ***\r\n ");
|
||||
return;
|
||||
}
|
||||
else
|
||||
len /= 4;
|
||||
|
||||
if (!refreshSerial())
|
||||
return;
|
||||
if (!serialSessionB("s", "debug"))
|
||||
return;
|
||||
|
||||
内存内容.Clear();
|
||||
|
||||
uint index = 0;
|
||||
for (index = 0; index < len; index++)
|
||||
{
|
||||
serialPort.Close();
|
||||
string send_str = String.Format("{0:x8}", start + index * 4);
|
||||
string response = "";
|
||||
if (!serialSessionA(send_str, ref response))
|
||||
return;
|
||||
内存内容.AppendText(String.Format("{0:x8} : {1:S}\r\n", start + index * 4, response.Trim()));
|
||||
}
|
||||
refreshPortStatus();
|
||||
}
|
||||
|
||||
private void refreshPortStatus()
|
||||
{
|
||||
if (serialPort.IsOpen)
|
||||
userPortOpenCloseBtn.Text = "关闭";
|
||||
else
|
||||
userPortOpenCloseBtn.Text = "打开";
|
||||
serialSessionB("o", "user");
|
||||
compilePromptText.AppendText(" *** Dump内存完成 ***\r\n");
|
||||
try { serialPort.ReadExisting(); }// 清空接收缓冲区
|
||||
catch { }
|
||||
userPortTextBox.Clear();
|
||||
enableUartDisplay = true;
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region 右侧串口监视窗的实时显示
|
||||
bool enableUartDisplay = true;
|
||||
public delegate void changeTextHandler(object str);
|
||||
|
||||
private void appendUserPortText(object str)
|
||||
@ -454,7 +517,6 @@ namespace USTCRVSoC_tool
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
private void userPortClearBtn_Click(object sender, EventArgs e)
|
||||
{
|
||||
userPortTextBox.Clear();
|
||||
@ -462,26 +524,30 @@ namespace USTCRVSoC_tool
|
||||
|
||||
private void serialPort_DataReceived(object sender, System.IO.Ports.SerialDataReceivedEventArgs e)
|
||||
{
|
||||
SerialPort sp = (SerialPort)sender;
|
||||
try
|
||||
if (enableUartDisplay)
|
||||
{
|
||||
string recvdata = sp.ReadExisting();
|
||||
if (userPortShowHex.Checked)
|
||||
SerialPort sp = (SerialPort)sender;
|
||||
try
|
||||
{
|
||||
StringBuilder sb = new StringBuilder();
|
||||
foreach (byte ch in recvdata)
|
||||
string recvdata = sp.ReadExisting();
|
||||
if (userPortShowHex.Checked)
|
||||
{
|
||||
sb.Append(String.Format("{0:X2} ", ch));
|
||||
StringBuilder sb = new StringBuilder();
|
||||
foreach (byte ch in recvdata)
|
||||
{
|
||||
sb.Append(String.Format("{0:X2} ", ch));
|
||||
}
|
||||
appendUserPortText(sb.ToString());
|
||||
}
|
||||
appendUserPortText(sb.ToString());
|
||||
else
|
||||
{
|
||||
appendUserPortText(recvdata);
|
||||
}
|
||||
userPortCount += (uint)recvdata.Length;
|
||||
}
|
||||
else
|
||||
{
|
||||
appendUserPortText(recvdata);
|
||||
}
|
||||
userPortCount += (uint)recvdata.Length;
|
||||
catch { }
|
||||
}
|
||||
catch { }
|
||||
}
|
||||
#endregion
|
||||
}
|
||||
}
|
||||
|
||||
166
hardware/ModelSim/USTCRVSoC.cr.mti
Normal file
166
hardware/ModelSim/USTCRVSoC.cr.mti
Normal file
@ -0,0 +1,166 @@
|
||||
E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv {1 {vlog -work work -sv {E:\work-Lab\USTCRVSoC\hardware\RTL\soc_top_tb.sv}
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module soc_top_tb
|
||||
|
||||
Top level modules:
|
||||
soc_top_tb
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling interface naive_bus
|
||||
|
||||
Top level modules:
|
||||
--none--
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module uart_rx
|
||||
|
||||
Top level modules:
|
||||
uart_rx
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module instr_rom
|
||||
|
||||
Top level modules:
|
||||
instr_rom
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module uart_tx_line
|
||||
|
||||
Top level modules:
|
||||
uart_tx_line
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module core_regfile
|
||||
|
||||
Top level modules:
|
||||
core_regfile
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv {2 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module isp_uart
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv(92): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv(94): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
|
||||
Top level modules:
|
||||
isp_uart
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module ram
|
||||
|
||||
Top level modules:
|
||||
ram
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module ram_bus_wrapper
|
||||
|
||||
Top level modules:
|
||||
ram_bus_wrapper
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv {2 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module naive_bus_router
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(64): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(65): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(66): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(67): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(68): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(69): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(70): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(71): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(72): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(73): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(73): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(75): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(76): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(77): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(78): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(81): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(82): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(83): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(84): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(85): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(96): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(97): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(98): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(99): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(99): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(101): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(102): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(105): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
|
||||
|
||||
|
||||
Top level modules:
|
||||
naive_bus_router
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module core_ex_branch_judge
|
||||
|
||||
Top level modules:
|
||||
core_ex_branch_judge
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module core_id_stage
|
||||
|
||||
Top level modules:
|
||||
core_id_stage
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module core_alu
|
||||
|
||||
Top level modules:
|
||||
core_alu
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module core_bus_wrapper
|
||||
|
||||
Top level modules:
|
||||
core_bus_wrapper
|
||||
|
||||
} {} {}} E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv
|
||||
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
|
||||
-- Compiling module core_top
|
||||
|
||||
Top level modules:
|
||||
core_top
|
||||
|
||||
} {} {}}
|
||||
533
hardware/ModelSim/USTCRVSoC.mpf
Normal file
533
hardware/ModelSim/USTCRVSoC.mpf
Normal file
@ -0,0 +1,533 @@
|
||||
; Copyright 1991-2009 Mentor Graphics Corporation
|
||||
;
|
||||
; All Rights Reserved.
|
||||
;
|
||||
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
|
||||
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
;
|
||||
|
||||
[Library]
|
||||
std = $MODEL_TECH/../std
|
||||
ieee = $MODEL_TECH/../ieee
|
||||
verilog = $MODEL_TECH/../verilog
|
||||
vital2000 = $MODEL_TECH/../vital2000
|
||||
std_developerskit = $MODEL_TECH/../std_developerskit
|
||||
synopsys = $MODEL_TECH/../synopsys
|
||||
modelsim_lib = $MODEL_TECH/../modelsim_lib
|
||||
sv_std = $MODEL_TECH/../sv_std
|
||||
|
||||
; Altera Primitive libraries
|
||||
;
|
||||
; VHDL Section
|
||||
;
|
||||
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
|
||||
altera = $MODEL_TECH/../altera/vhdl/altera
|
||||
altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
|
||||
lpm = $MODEL_TECH/../altera/vhdl/220model
|
||||
220model = $MODEL_TECH/../altera/vhdl/220model
|
||||
max = $MODEL_TECH/../altera/vhdl/max
|
||||
maxii = $MODEL_TECH/../altera/vhdl/maxii
|
||||
maxv = $MODEL_TECH/../altera/vhdl/maxv
|
||||
stratix = $MODEL_TECH/../altera/vhdl/stratix
|
||||
stratixii = $MODEL_TECH/../altera/vhdl/stratixii
|
||||
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
|
||||
hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii
|
||||
hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii
|
||||
hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv
|
||||
cyclone = $MODEL_TECH/../altera/vhdl/cyclone
|
||||
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
|
||||
cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii
|
||||
cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils
|
||||
sgate = $MODEL_TECH/../altera/vhdl/sgate
|
||||
stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx
|
||||
altgxb = $MODEL_TECH/../altera/vhdl/altgxb
|
||||
stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb
|
||||
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
|
||||
arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi
|
||||
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
|
||||
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
|
||||
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
|
||||
arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
|
||||
arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
|
||||
arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
|
||||
arriagx = $MODEL_TECH/../altera/vhdl/arriagx
|
||||
altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb
|
||||
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
|
||||
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
|
||||
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
|
||||
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
|
||||
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
|
||||
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
|
||||
cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
|
||||
hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi
|
||||
hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip
|
||||
stratixv = $MODEL_TECH/../altera/vhdl/stratixv
|
||||
stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
|
||||
stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
|
||||
arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
|
||||
arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
|
||||
arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
|
||||
arriav = $MODEL_TECH/../altera/vhdl/arriav
|
||||
cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
|
||||
twentynm = $MODEL_TECH/../altera/vhdl/twentynm
|
||||
twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
|
||||
twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
|
||||
;
|
||||
; Verilog Section
|
||||
;
|
||||
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
|
||||
altera_ver = $MODEL_TECH/../altera/verilog/altera
|
||||
altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
|
||||
lpm_ver = $MODEL_TECH/../altera/verilog/220model
|
||||
220model_ver = $MODEL_TECH/../altera/verilog/220model
|
||||
max_ver = $MODEL_TECH/../altera/verilog/max
|
||||
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
|
||||
maxv_ver = $MODEL_TECH/../altera/verilog/maxv
|
||||
stratix_ver = $MODEL_TECH/../altera/verilog/stratix
|
||||
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
|
||||
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
|
||||
arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx
|
||||
hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii
|
||||
hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii
|
||||
hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv
|
||||
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
|
||||
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
|
||||
cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii
|
||||
cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils
|
||||
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
|
||||
stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx
|
||||
altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb
|
||||
stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb
|
||||
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
|
||||
arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi
|
||||
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
|
||||
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
|
||||
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
|
||||
arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
|
||||
arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
|
||||
arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
|
||||
stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
|
||||
stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
|
||||
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
|
||||
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
|
||||
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
|
||||
stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
|
||||
stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
|
||||
stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
|
||||
arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
|
||||
arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
|
||||
arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
|
||||
arriav_ver = $MODEL_TECH/../altera/verilog/arriav
|
||||
arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
|
||||
arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
|
||||
cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
|
||||
cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
|
||||
cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
|
||||
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
|
||||
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
|
||||
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
|
||||
cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
|
||||
hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi
|
||||
hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip
|
||||
twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
|
||||
twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
|
||||
twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
|
||||
|
||||
work = work
|
||||
[vcom]
|
||||
; VHDL93 variable selects language version as the default.
|
||||
; Default is VHDL-2002.
|
||||
; Value of 0 or 1987 for VHDL-1987.
|
||||
; Value of 1 or 1993 for VHDL-1993.
|
||||
; Default or value of 2 or 2002 for VHDL-2002.
|
||||
; Default or value of 3 or 2008 for VHDL-2008.
|
||||
VHDL93 = 2002
|
||||
|
||||
; Show source line containing error. Default is off.
|
||||
; Show_source = 1
|
||||
|
||||
; Turn off unbound-component warnings. Default is on.
|
||||
; Show_Warning1 = 0
|
||||
|
||||
; Turn off process-without-a-wait-statement warnings. Default is on.
|
||||
; Show_Warning2 = 0
|
||||
|
||||
; Turn off null-range warnings. Default is on.
|
||||
; Show_Warning3 = 0
|
||||
|
||||
; Turn off no-space-in-time-literal warnings. Default is on.
|
||||
; Show_Warning4 = 0
|
||||
|
||||
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
||||
; Show_Warning5 = 0
|
||||
|
||||
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
||||
; Optimize_1164 = 0
|
||||
|
||||
; Turn on resolving of ambiguous function overloading in favor of the
|
||||
; "explicit" function declaration (not the one automatically created by
|
||||
; the compiler for each type declaration). Default is off.
|
||||
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
|
||||
; will match the behavior of synthesis tools.
|
||||
Explicit = 1
|
||||
|
||||
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
||||
; NoVital = 1
|
||||
|
||||
; Turn off VITAL compliance checking. Default is checking on.
|
||||
; NoVitalCheck = 1
|
||||
|
||||
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
||||
; IgnoreVitalErrors = 1
|
||||
|
||||
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
||||
; Show_VitalChecksWarnings = 0
|
||||
|
||||
; Keep silent about case statement static warnings.
|
||||
; Default is to give a warning.
|
||||
; NoCaseStaticError = 1
|
||||
|
||||
; Keep silent about warnings caused by aggregates that are not locally static.
|
||||
; Default is to give a warning.
|
||||
; NoOthersStaticError = 1
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "Loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on some limited synthesis rule compliance checking. Checks only:
|
||||
; -- signals used (read) by a process must be in the sensitivity list
|
||||
; CheckSynthesis = 1
|
||||
|
||||
; Activate optimizations on expressions that do not involve signals,
|
||||
; waits, or function/procedure/task invocations. Default is off.
|
||||
; ScalarOpts = 1
|
||||
|
||||
; Require the user to specify a configuration for all bindings,
|
||||
; and do not generate a compile time default binding for the
|
||||
; component. This will result in an elaboration error of
|
||||
; 'component not bound' if the user fails to do so. Avoids the rare
|
||||
; issue of a false dependency upon the unused default binding.
|
||||
; RequireConfigForAllDefaultBinding = 1
|
||||
|
||||
; Inhibit range checking on subscripts of arrays. Range checking on
|
||||
; scalars defined with subtypes is inhibited by default.
|
||||
; NoIndexCheck = 1
|
||||
|
||||
; Inhibit range checks on all (implicit and explicit) assignments to
|
||||
; scalar objects defined with subtypes.
|
||||
; NoRangeCheck = 1
|
||||
|
||||
[vlog]
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
||||
; Default is off.
|
||||
; Hazard = 1
|
||||
|
||||
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
||||
; insensitivity for module names. Default is no conversion.
|
||||
; UpCase = 1
|
||||
|
||||
; Turn on incremental compilation of modules. Default is off.
|
||||
; Incremental = 1
|
||||
|
||||
; Turns on lint-style checking.
|
||||
; Show_Lint = 1
|
||||
|
||||
[vsim]
|
||||
; Simulator resolution
|
||||
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
||||
Resolution = ps
|
||||
|
||||
; User time unit for run commands
|
||||
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
||||
; unit specified for Resolution. For example, if Resolution is 100ps,
|
||||
; then UserTimeUnit defaults to ps.
|
||||
; Should generally be set to default.
|
||||
UserTimeUnit = default
|
||||
|
||||
; Default run length
|
||||
RunLength = 100 ps
|
||||
|
||||
; Maximum iterations that can be run without advancing simulation time
|
||||
IterationLimit = 5000
|
||||
|
||||
; Directive to license manager:
|
||||
; vhdl Immediately reserve a VHDL license
|
||||
; vlog Immediately reserve a Verilog license
|
||||
; plus Immediately reserve a VHDL and Verilog license
|
||||
; nomgc Do not look for Mentor Graphics Licenses
|
||||
; nomti Do not look for Model Technology Licenses
|
||||
; noqueue Do not wait in the license queue when a license isn't available
|
||||
; viewsim Try for viewer license but accept simulator license(s) instead
|
||||
; of queuing for viewer license
|
||||
; License = plus
|
||||
|
||||
; Stop the simulator after a VHDL/Verilog assertion message
|
||||
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
||||
BreakOnAssertion = 3
|
||||
|
||||
; Assertion Message Format
|
||||
; %S - Severity Level
|
||||
; %R - Report Message
|
||||
; %T - Time of assertion
|
||||
; %D - Delta
|
||||
; %I - Instance or Region pathname (if available)
|
||||
; %% - print '%' character
|
||||
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||
|
||||
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
|
||||
; AssertFile = assert.log
|
||||
|
||||
; Default radix for all windows and commands...
|
||||
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
||||
DefaultRadix = symbolic
|
||||
|
||||
; VSIM Startup command
|
||||
; Startup = do startup.do
|
||||
|
||||
; File for saving command transcript
|
||||
TranscriptFile = transcript
|
||||
|
||||
; File for saving command history
|
||||
; CommandHistory = cmdhist.log
|
||||
|
||||
; Specify whether paths in simulator commands should be described
|
||||
; in VHDL or Verilog format.
|
||||
; For VHDL, PathSeparator = /
|
||||
; For Verilog, PathSeparator = .
|
||||
; Must not be the same character as DatasetSeparator.
|
||||
PathSeparator = /
|
||||
|
||||
; Specify the dataset separator for fully rooted contexts.
|
||||
; The default is ':'. For example, sim:/top
|
||||
; Must not be the same character as PathSeparator.
|
||||
DatasetSeparator = :
|
||||
|
||||
; Disable VHDL assertion messages
|
||||
; IgnoreNote = 1
|
||||
; IgnoreWarning = 1
|
||||
; IgnoreError = 1
|
||||
; IgnoreFailure = 1
|
||||
|
||||
; Default force kind. May be freeze, drive, deposit, or default
|
||||
; or in other terms, fixed, wired, or charged.
|
||||
; A value of "default" will use the signal kind to determine the
|
||||
; force kind, drive for resolved signals, freeze for unresolved signals
|
||||
; DefaultForceKind = freeze
|
||||
|
||||
; If zero, open files when elaborated; otherwise, open files on
|
||||
; first read or write. Default is 0.
|
||||
; DelayFileOpen = 1
|
||||
|
||||
; Control VHDL files opened for write.
|
||||
; 0 = Buffered, 1 = Unbuffered
|
||||
UnbufferedOutput = 0
|
||||
|
||||
; Control the number of VHDL files open concurrently.
|
||||
; This number should always be less than the current ulimit
|
||||
; setting for max file descriptors.
|
||||
; 0 = unlimited
|
||||
ConcurrentFileLimit = 40
|
||||
|
||||
; Control the number of hierarchical regions displayed as
|
||||
; part of a signal name shown in the Wave window.
|
||||
; A value of zero tells VSIM to display the full name.
|
||||
; The default is 0.
|
||||
; WaveSignalNameWidth = 0
|
||||
|
||||
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
||||
; and std_logic_signed packages.
|
||||
; StdArithNoWarnings = 1
|
||||
|
||||
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
||||
; NumericStdNoWarnings = 1
|
||||
|
||||
; Control the format of the (VHDL) FOR generate statement label
|
||||
; for each iteration. Do not quote it.
|
||||
; The format string here must contain the conversion codes %s and %d,
|
||||
; in that order, and no other conversion codes. The %s represents
|
||||
; the generate_label; the %d represents the generate parameter value
|
||||
; at a particular generate iteration (this is the position number if
|
||||
; the generate parameter is of an enumeration type). Embedded whitespace
|
||||
; is allowed (but discouraged); leading and trailing whitespace is ignored.
|
||||
; Application of the format must result in a unique scope name over all
|
||||
; such names in the design so that name lookup can function properly.
|
||||
; GenerateFormat = %s__%d
|
||||
|
||||
; Specify whether checkpoint files should be compressed.
|
||||
; The default is 1 (compressed).
|
||||
; CheckpointCompressMode = 0
|
||||
|
||||
; List of dynamically loaded objects for Verilog PLI applications
|
||||
; Veriuser = veriuser.sl
|
||||
|
||||
; Specify default options for the restart command. Options can be one
|
||||
; or more of: -force -nobreakpoint -nolist -nolog -nowave
|
||||
; DefaultRestartOptions = -force
|
||||
|
||||
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
||||
; (> 500 megabyte memory footprint). Default is disabled.
|
||||
; Specify number of megabytes to lock.
|
||||
; LockedMemory = 1000
|
||||
|
||||
; Turn on (1) or off (0) WLF file compression.
|
||||
; The default is 1 (compress WLF file).
|
||||
; WLFCompress = 0
|
||||
|
||||
; Specify whether to save all design hierarchy (1) in the WLF file
|
||||
; or only regions containing logged signals (0).
|
||||
; The default is 0 (save only regions with logged signals).
|
||||
; WLFSaveAllRegions = 1
|
||||
|
||||
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
||||
; to the specified amount of simulation time. When the limit is exceeded
|
||||
; the earliest times get truncated from the file.
|
||||
; If both time and size limits are specified the most restrictive is used.
|
||||
; UserTimeUnits are used if time units are not specified.
|
||||
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
|
||||
; WLFTimeLimit = 0
|
||||
|
||||
; WLF file size limit. Limit WLF file size, as closely as possible,
|
||||
; to the specified number of megabytes. If both time and size limits
|
||||
; are specified then the most restrictive is used.
|
||||
; The default is 0 (no limit).
|
||||
; WLFSizeLimit = 1000
|
||||
|
||||
; Specify whether or not a WLF file should be deleted when the
|
||||
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
||||
; The default is 0 (do not delete WLF file when simulation ends).
|
||||
; WLFDeleteOnQuit = 1
|
||||
|
||||
; Automatic SDF compilation
|
||||
; Disables automatic compilation of SDF files in flows that support it.
|
||||
; Default is on, uncomment to turn off.
|
||||
; NoAutoSDFCompile = 1
|
||||
|
||||
[lmc]
|
||||
|
||||
[msg_system]
|
||||
; Change a message severity or suppress a message.
|
||||
; The format is: <msg directive> = <msg number>[,<msg number>...]
|
||||
; Examples:
|
||||
; note = 3009
|
||||
; warning = 3033
|
||||
; error = 3010,3016
|
||||
; fatal = 3016,3033
|
||||
; suppress = 3009,3016,3043
|
||||
; The command verror <msg number> can be used to get the complete
|
||||
; description of a message.
|
||||
|
||||
; Control transcripting of elaboration/runtime messages.
|
||||
; The default is to have messages appear in the transcript and
|
||||
; recorded in the wlf file (messages that are recorded in the
|
||||
; wlf file can be viewed in the MsgViewer). The other settings
|
||||
; are to send messages only to the transcript or only to the
|
||||
; wlf file. The valid values are
|
||||
; both {default}
|
||||
; tran {transcript only}
|
||||
; wlf {wlf file only}
|
||||
; msgmode = both
|
||||
[Project]
|
||||
; Warning -- Do not edit the project properties directly.
|
||||
; Property names are dynamic in nature and property
|
||||
; values have special syntax. Changing property data directly
|
||||
; can result in a corrupt MPF file. All project properties
|
||||
; can be modified through project window dialogs.
|
||||
Project_Version = 6
|
||||
Project_DefaultLib = work
|
||||
Project_SortMethod = unused
|
||||
Project_Files_Count = 18
|
||||
Project_File_0 = E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv
|
||||
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1551505557 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_1 = E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv
|
||||
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_2 = E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv
|
||||
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1551167092 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_3 = E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv
|
||||
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_4 = E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv
|
||||
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551094921 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_5 = E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv
|
||||
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1551166630 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_6 = E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv
|
||||
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551092170 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_7 = E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv
|
||||
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_8 = E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv
|
||||
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1551505505 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_9 = E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv
|
||||
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551102643 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_10 = E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv
|
||||
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551090389 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_11 = E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv
|
||||
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1550846066 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_12 = E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv
|
||||
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_13 = E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
|
||||
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_14 = E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv
|
||||
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_15 = E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv
|
||||
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_16 = E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv
|
||||
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_File_17 = E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv
|
||||
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1551169276 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_Sim_Count = 0
|
||||
Project_Folder_Count = 0
|
||||
Echo_Compile_Output = 0
|
||||
Save_Compile_Report = 1
|
||||
Project_Opt_Count = 0
|
||||
ForceSoftPaths = 0
|
||||
ProjectStatusDelay = 5000
|
||||
VERILOG_DoubleClick = Edit
|
||||
VERILOG_CustomDoubleClick =
|
||||
SYSTEMVERILOG_DoubleClick = Edit
|
||||
SYSTEMVERILOG_CustomDoubleClick =
|
||||
VHDL_DoubleClick = Edit
|
||||
VHDL_CustomDoubleClick =
|
||||
PSL_DoubleClick = Edit
|
||||
PSL_CustomDoubleClick =
|
||||
TEXT_DoubleClick = Edit
|
||||
TEXT_CustomDoubleClick =
|
||||
SYSTEMC_DoubleClick = Edit
|
||||
SYSTEMC_CustomDoubleClick =
|
||||
TCL_DoubleClick = Edit
|
||||
TCL_CustomDoubleClick =
|
||||
MACRO_DoubleClick = Edit
|
||||
MACRO_CustomDoubleClick =
|
||||
VCD_DoubleClick = Edit
|
||||
VCD_CustomDoubleClick =
|
||||
SDF_DoubleClick = Edit
|
||||
SDF_CustomDoubleClick =
|
||||
XML_DoubleClick = Edit
|
||||
XML_CustomDoubleClick =
|
||||
LOGFILE_DoubleClick = Edit
|
||||
LOGFILE_CustomDoubleClick =
|
||||
UCDB_DoubleClick = Edit
|
||||
UCDB_CustomDoubleClick =
|
||||
UPF_DoubleClick = Edit
|
||||
UPF_CustomDoubleClick =
|
||||
PCF_DoubleClick = Edit
|
||||
PCF_CustomDoubleClick =
|
||||
PROJECT_DoubleClick = Edit
|
||||
PROJECT_CustomDoubleClick =
|
||||
VRM_DoubleClick = Edit
|
||||
VRM_CustomDoubleClick =
|
||||
DEBUGDATABASE_DoubleClick = Edit
|
||||
DEBUGDATABASE_CustomDoubleClick =
|
||||
DEBUGARCHIVE_DoubleClick = Edit
|
||||
DEBUGARCHIVE_CustomDoubleClick =
|
||||
Project_Major_Version = 10
|
||||
Project_Minor_Version = 1
|
||||
BIN
hardware/ModelSim/vsim.wlf
Normal file
BIN
hardware/ModelSim/vsim.wlf
Normal file
Binary file not shown.
468
hardware/ModelSim/work/_info
Normal file
468
hardware/ModelSim/work/_info
Normal file
@ -0,0 +1,468 @@
|
||||
m255
|
||||
K3
|
||||
13
|
||||
cModel Technology
|
||||
Z0 dC:\altera\13.1
|
||||
vchar8x16_rom
|
||||
Z1 DXx6 sv_std 3 std 0 22 F[19LRNL:5;XmIFh[XOPn1
|
||||
!i10b 1
|
||||
Z2 !s100 ;IlD4IOMGEYo80>^h^UhK3
|
||||
Z3 I<>FR1OkHc6KV4iK0a<Q?<0
|
||||
Z4 VN2h6;hjMc8b_1gne=2;Q10
|
||||
Z5 !s105 video_ram_sv_unit
|
||||
S1
|
||||
Z6 dE:\work-Lab\USTCRVSoC\hardware\ModelSim
|
||||
Z7 w1551166630
|
||||
Z8 8E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv
|
||||
Z9 FE:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv
|
||||
Z10 L0 202
|
||||
Z11 OV;L;10.1d;51
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
Z12 !s108 1551505561.076000
|
||||
Z13 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv|
|
||||
Z14 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv|
|
||||
!s101 -O0
|
||||
Z15 o-work work -sv -O0
|
||||
vcore_alu
|
||||
R1
|
||||
Z16 !s100 iCH1]MMmI?;=TKD:>Fe_b2
|
||||
Z17 I?HDS_jndEJ3e84j7B6zi00
|
||||
Z18 VCm9FCj0lB9T7DXWo]1;1f0
|
||||
Z19 !s105 core_alu_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z20 w1549876350
|
||||
Z21 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv
|
||||
Z22 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv
|
||||
L0 1
|
||||
R11
|
||||
r1
|
||||
31
|
||||
Z23 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv|
|
||||
R15
|
||||
Z24 !s108 1551505559.882000
|
||||
Z25 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vcore_bus_wrapper
|
||||
R1
|
||||
Z26 !s100 M_`JZE_P3V6d4RWWRY8751
|
||||
Z27 I4k_4?GVX@^QA>lfAA:7Ce3
|
||||
Z28 VmlnoE:bmH;9e3[Jfd^_M=3
|
||||
Z29 !s105 core_bus_wrapper_sv_unit
|
||||
S1
|
||||
R6
|
||||
R20
|
||||
Z30 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv
|
||||
Z31 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv
|
||||
L0 1
|
||||
R11
|
||||
r1
|
||||
31
|
||||
Z32 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv|
|
||||
R15
|
||||
Z33 !s108 1551505559.961000
|
||||
Z34 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vcore_ex_branch_judge
|
||||
R1
|
||||
Z35 !s100 e`[4=hnRGoQ8ei^3k>On51
|
||||
Z36 IJFElj3c9672KTjE9TR>LF1
|
||||
Z37 V@jT?>bnOD2?j_T4=3fkh_3
|
||||
Z38 !s105 core_ex_branch_judge_sv_unit
|
||||
S1
|
||||
R6
|
||||
R20
|
||||
Z39 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
|
||||
Z40 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
|
||||
L0 1
|
||||
R11
|
||||
r1
|
||||
31
|
||||
Z41 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv|
|
||||
R15
|
||||
Z42 !s108 1551505560.045000
|
||||
Z43 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vcore_id_stage
|
||||
R1
|
||||
Z44 !s100 kRDMIRciCbeOb5=R?37071
|
||||
Z45 Io4GObCTY4;CTKQ<HjO:=V3
|
||||
Z46 Vfo`K`XV=DajZ8Eb]j?gV:3
|
||||
Z47 !s105 core_id_stage_sv_unit
|
||||
S1
|
||||
R6
|
||||
R20
|
||||
Z48 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv
|
||||
Z49 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv
|
||||
L0 1
|
||||
R11
|
||||
r1
|
||||
31
|
||||
Z50 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv|
|
||||
R15
|
||||
Z51 !s108 1551505560.109000
|
||||
Z52 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vcore_regfile
|
||||
R1
|
||||
Z53 !s100 Dna_T_?^^W?K0@1mdN7?P2
|
||||
Z54 ID]n5X]WVRSDO5WE>0hl0]3
|
||||
Z55 VaXLkm<HFE<T[8I`oKbaaA1
|
||||
Z56 !s105 core_regfile_sv_unit
|
||||
S1
|
||||
R6
|
||||
R20
|
||||
Z57 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv
|
||||
Z58 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv
|
||||
L0 2
|
||||
R11
|
||||
r1
|
||||
31
|
||||
Z59 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv|
|
||||
R15
|
||||
Z60 !s108 1551505560.178000
|
||||
Z61 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vcore_top
|
||||
R1
|
||||
Z62 !s100 O2VJO7S?RbR=^Rj:fN=0`2
|
||||
Z63 I8?0idhHn?IYLgTaS3djD>3
|
||||
Z64 Vi7?O@h6m5O3BFF`kIdBUC2
|
||||
Z65 !s105 core_top_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z66 w1551169276
|
||||
Z67 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv
|
||||
Z68 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv
|
||||
L0 1
|
||||
R11
|
||||
r1
|
||||
31
|
||||
Z69 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv|
|
||||
R15
|
||||
Z70 !s108 1551505560.245000
|
||||
Z71 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vinstr_rom
|
||||
R1
|
||||
Z72 !s100 Bd]Z1a^3]kD30E<26M`Lm1
|
||||
Z73 IOc1Uo_kS08]?1_CKOHHU?0
|
||||
Z74 Vg27TzclZ3S3@lBLMlA`?L1
|
||||
Z75 !s105 instr_rom_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z76 w1551094921
|
||||
Z77 8E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv
|
||||
Z78 FE:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv
|
||||
L0 1
|
||||
R11
|
||||
r1
|
||||
31
|
||||
Z79 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv|
|
||||
R15
|
||||
Z80 !s108 1551505560.314000
|
||||
Z81 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
visp_uart
|
||||
R1
|
||||
Z82 !s100 @dmH];GG>K;lS7PljQ:Am1
|
||||
Z83 I_4gBZG2Ib<khkdHbSDz?I0
|
||||
Z84 V@@jZ3Y6;d=WD@H08`7cWF3
|
||||
Z85 !s105 isp_uart_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z86 w1551102643
|
||||
Z87 8E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv
|
||||
Z88 FE:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv
|
||||
L0 3
|
||||
R11
|
||||
r1
|
||||
31
|
||||
Z89 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv|
|
||||
R15
|
||||
Z90 !s108 1551505560.388000
|
||||
Z91 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
Ynaive_bus
|
||||
R1
|
||||
Z92 !s100 gFz59kzW]I]nGiaVoSo3O2
|
||||
Z93 Idj:03TOO?jDHzf[0c?lJ`2
|
||||
Z94 VKXR@0<URHIKN=UGzERidm1
|
||||
Z95 !s105 naive_bus_sv_unit
|
||||
S1
|
||||
R6
|
||||
R20
|
||||
Z96 8E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv
|
||||
Z97 FE:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv
|
||||
L0 4
|
||||
R11
|
||||
r1
|
||||
31
|
||||
Z98 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv|
|
||||
R15
|
||||
Z99 !s108 1551505560.458000
|
||||
Z100 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vnaive_bus_router
|
||||
R1
|
||||
Z101 !s100 nSRUejF=Q5]HdBmmdfzLA1
|
||||
Z102 I^NC0W49]?el6;z^6BojXI2
|
||||
Z103 VS<O=OM<>7@f0]AeUc<_5c0
|
||||
Z104 !s105 naive_bus_router_sv_unit
|
||||
S1
|
||||
R6
|
||||
R20
|
||||
Z105 8E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv
|
||||
Z106 FE:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv
|
||||
L0 1
|
||||
R11
|
||||
r1
|
||||
31
|
||||
Z107 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv|
|
||||
R15
|
||||
Z108 !s108 1551505560.524000
|
||||
Z109 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vram
|
||||
R1
|
||||
Z110 !s100 TMn[TG8XXmK^UL@k7`ikC0
|
||||
Z111 INIlD0C@nO9Rk96M@_1B?92
|
||||
Z112 VjLloJg4mGdQ3i@ojJbWma2
|
||||
Z113 !s105 ram_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z114 w1551090389
|
||||
Z115 8E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv
|
||||
Z116 FE:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv
|
||||
L0 1
|
||||
R11
|
||||
r1
|
||||
31
|
||||
Z117 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv|
|
||||
R15
|
||||
Z118 !s108 1551505560.595000
|
||||
Z119 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vram_bus_wrapper
|
||||
R1
|
||||
Z120 !s100 U?Io3WFYaekAS0T@dW=V43
|
||||
Z121 I?^eTo:Go<IUo<UVJm@aFd0
|
||||
Z122 V^7VeTGko3:7B>^H5Y:FP:1
|
||||
Z123 !s105 ram_bus_wrapper_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z124 w1550846066
|
||||
Z125 8E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv
|
||||
Z126 FE:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv
|
||||
L0 1
|
||||
R11
|
||||
r1
|
||||
31
|
||||
Z127 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv|
|
||||
R15
|
||||
Z128 !s108 1551505560.660000
|
||||
Z129 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vsoc_top
|
||||
R1
|
||||
Z130 IX85mf[[9oQ]V7eK[]II;01
|
||||
Z131 VQ=e`6`fzTCbZ78O>KAKe>2
|
||||
Z132 !s105 soc_top_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z133 w1551505505
|
||||
Z134 8E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv
|
||||
Z135 FE:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv
|
||||
L0 1
|
||||
R11
|
||||
r1
|
||||
31
|
||||
Z136 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv|
|
||||
R15
|
||||
Z137 !s100 LMhfd9`0AH32SARk[<Z470
|
||||
Z138 !s108 1551505560.725000
|
||||
Z139 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vsoc_top_tb
|
||||
R1
|
||||
Z140 I3jM5<::]YSG=2?]>]:L;L3
|
||||
Z141 VkLTgIQbfzI]@>Jm[T?T@F0
|
||||
Z142 !s105 soc_top_tb_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z143 w1551505557
|
||||
Z144 8E:\work-Lab\USTCRVSoC\hardware\RTL\soc_top_tb.sv
|
||||
Z145 FE:\work-Lab\USTCRVSoC\hardware\RTL\soc_top_tb.sv
|
||||
L0 1
|
||||
R11
|
||||
r1
|
||||
31
|
||||
R15
|
||||
Z146 !s100 [cOSC1Uh3BK?X?_L=Pb:d1
|
||||
Z147 !s108 1551505560.791000
|
||||
Z148 !s107 E:\work-Lab\USTCRVSoC\hardware\RTL\soc_top_tb.sv|
|
||||
Z149 !s90 -reportprogress|300|-work|work|-sv|E:\work-Lab\USTCRVSoC\hardware\RTL\soc_top_tb.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vuart_rx
|
||||
R1
|
||||
Z150 !s100 :`YDkKm;LaUQOjOXmaKB:0
|
||||
Z151 IL9Ji^>V6GeZ<;c7I`o3LQ1
|
||||
Z152 Vh0;PUSD9VYIXe2P@6jV9;0
|
||||
Z153 !s105 uart_rx_sv_unit
|
||||
S1
|
||||
R6
|
||||
R20
|
||||
Z154 8E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv
|
||||
Z155 FE:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv
|
||||
L0 1
|
||||
R11
|
||||
r1
|
||||
31
|
||||
Z156 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv|
|
||||
R15
|
||||
Z157 !s108 1551505560.871000
|
||||
Z158 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vuart_tx_line
|
||||
R1
|
||||
Z159 !s100 WEQ@68?0=RGj1iFdbOOcP2
|
||||
Z160 IK1;[1cPPe^6]7LKQ15Lf21
|
||||
Z161 VW`_FG<Oo:1]3K5g>fF=@_3
|
||||
Z162 !s105 uart_tx_line_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z163 w1551092170
|
||||
Z164 8E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv
|
||||
Z165 FE:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv
|
||||
L0 2
|
||||
R11
|
||||
r1
|
||||
31
|
||||
Z166 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv|
|
||||
R15
|
||||
Z167 !s108 1551505560.944000
|
||||
Z168 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vuser_uart_tx
|
||||
R1
|
||||
Z169 !s100 YA]KWMS3fOD:CQT@0Y9C83
|
||||
Z170 I0JOL7FjkENP;iNc25_jl92
|
||||
Z171 V<1FQ0oW1UA`j`9IX[bcdE1
|
||||
Z172 !s105 user_uart_tx_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z173 w1551167092
|
||||
Z174 8E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv
|
||||
Z175 FE:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv
|
||||
L0 2
|
||||
R11
|
||||
r1
|
||||
31
|
||||
Z176 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv|
|
||||
R15
|
||||
!i10b 1
|
||||
!s85 0
|
||||
Z177 !s108 1551505561.010000
|
||||
Z178 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv|
|
||||
!s101 -O0
|
||||
vvga
|
||||
R1
|
||||
!i10b 1
|
||||
Z179 !s100 9f0>Y=7iSmCK^QMkzVhdz2
|
||||
Z180 IK]n:1gV]8z:A^2D<Og@_H3
|
||||
Z181 VR^SlDkaag;z6W]0_6nChW1
|
||||
R5
|
||||
S1
|
||||
R6
|
||||
R7
|
||||
R8
|
||||
R9
|
||||
Z182 L0 147
|
||||
R11
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R12
|
||||
R13
|
||||
R14
|
||||
!s101 -O0
|
||||
R15
|
||||
vvgaChar98x36
|
||||
R1
|
||||
!i10b 1
|
||||
Z183 !s100 3ih;Pko8X4XgOhl5e4_Gh0
|
||||
Z184 IaM^Q2hPSE=jENCH[nQnb^0
|
||||
Z185 VkYR^g;?9@>9aFYMNc5Beh0
|
||||
R5
|
||||
S1
|
||||
R6
|
||||
R7
|
||||
R8
|
||||
R9
|
||||
L0 82
|
||||
R11
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R12
|
||||
R13
|
||||
R14
|
||||
!s101 -O0
|
||||
R15
|
||||
Z186 nvga@char98x36
|
||||
vvideo_ram
|
||||
R1
|
||||
!i10b 1
|
||||
Z187 !s100 `YSFQF4S?^]MHPKnUlGj:2
|
||||
Z188 IPVzCYEAl]UFiSXzJTNDQT3
|
||||
Z189 Vl^[jWF`OTazg>MX7@1zUi2
|
||||
R5
|
||||
S1
|
||||
R6
|
||||
R7
|
||||
R8
|
||||
R9
|
||||
L0 1
|
||||
R11
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R12
|
||||
R13
|
||||
R14
|
||||
!s101 -O0
|
||||
R15
|
||||
3
hardware/ModelSim/work/_vmake
Normal file
3
hardware/ModelSim/work/_vmake
Normal file
@ -0,0 +1,3 @@
|
||||
m255
|
||||
K3
|
||||
cModel Technology
|
||||
BIN
hardware/ModelSim/work/char8x16_rom/_primary.dat
Normal file
BIN
hardware/ModelSim/work/char8x16_rom/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/char8x16_rom/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/char8x16_rom/_primary.dbs
Normal file
Binary file not shown.
12
hardware/ModelSim/work/char8x16_rom/_primary.vhd
Normal file
12
hardware/ModelSim/work/char8x16_rom/_primary.vhd
Normal file
@ -0,0 +1,12 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity char8x16_rom is
|
||||
port(
|
||||
clk : in vl_logic;
|
||||
rst_n : in vl_logic;
|
||||
ascii : in vl_logic_vector(7 downto 0);
|
||||
x : in vl_logic_vector(2 downto 0);
|
||||
y : in vl_logic_vector(3 downto 0);
|
||||
b : out vl_logic
|
||||
);
|
||||
end char8x16_rom;
|
||||
BIN
hardware/ModelSim/work/char8x16_rom/verilog.prw
Normal file
BIN
hardware/ModelSim/work/char8x16_rom/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/char8x16_rom/verilog.psm
Normal file
BIN
hardware/ModelSim/work/char8x16_rom/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_alu/_primary.dat
Normal file
BIN
hardware/ModelSim/work/core_alu/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_alu/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/core_alu/_primary.dbs
Normal file
Binary file not shown.
13
hardware/ModelSim/work/core_alu/_primary.vhd
Normal file
13
hardware/ModelSim/work/core_alu/_primary.vhd
Normal file
@ -0,0 +1,13 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity core_alu is
|
||||
port(
|
||||
i_opcode : in vl_logic_vector(6 downto 0);
|
||||
i_funct7 : in vl_logic_vector(6 downto 0);
|
||||
i_funct3 : in vl_logic_vector(2 downto 0);
|
||||
i_num1u : in vl_logic_vector(31 downto 0);
|
||||
i_num2u : in vl_logic_vector(31 downto 0);
|
||||
i_immu : in vl_logic_vector(31 downto 0);
|
||||
o_res : out vl_logic_vector(31 downto 0)
|
||||
);
|
||||
end core_alu;
|
||||
BIN
hardware/ModelSim/work/core_alu/verilog.prw
Normal file
BIN
hardware/ModelSim/work/core_alu/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_alu/verilog.psm
Normal file
BIN
hardware/ModelSim/work/core_alu/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_bus_wrapper/_primary.dat
Normal file
BIN
hardware/ModelSim/work/core_bus_wrapper/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_bus_wrapper/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/core_bus_wrapper/_primary.dbs
Normal file
Binary file not shown.
16
hardware/ModelSim/work/core_bus_wrapper/_primary.vhd
Normal file
16
hardware/ModelSim/work/core_bus_wrapper/_primary.vhd
Normal file
@ -0,0 +1,16 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity core_bus_wrapper is
|
||||
port(
|
||||
clk : in vl_logic;
|
||||
rst_n : in vl_logic;
|
||||
i_re : in vl_logic;
|
||||
i_we : in vl_logic;
|
||||
o_conflict : out vl_logic;
|
||||
o_conflict_latch: out vl_logic;
|
||||
i_funct3 : in vl_logic_vector(2 downto 0);
|
||||
i_addr : in vl_logic_vector(31 downto 0);
|
||||
i_wdata : in vl_logic_vector(31 downto 0);
|
||||
o_rdata : out vl_logic_vector(31 downto 0)
|
||||
);
|
||||
end core_bus_wrapper;
|
||||
BIN
hardware/ModelSim/work/core_bus_wrapper/verilog.prw
Normal file
BIN
hardware/ModelSim/work/core_bus_wrapper/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_bus_wrapper/verilog.psm
Normal file
BIN
hardware/ModelSim/work/core_bus_wrapper/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_ex_branch_judge/_primary.dat
Normal file
BIN
hardware/ModelSim/work/core_ex_branch_judge/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_ex_branch_judge/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/core_ex_branch_judge/_primary.dbs
Normal file
Binary file not shown.
11
hardware/ModelSim/work/core_ex_branch_judge/_primary.vhd
Normal file
11
hardware/ModelSim/work/core_ex_branch_judge/_primary.vhd
Normal file
@ -0,0 +1,11 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity core_ex_branch_judge is
|
||||
port(
|
||||
i_branch : in vl_logic;
|
||||
i_num1u : in vl_logic_vector(31 downto 0);
|
||||
i_num2u : in vl_logic_vector(31 downto 0);
|
||||
i_funct3 : in vl_logic_vector(2 downto 0);
|
||||
o_branch : out vl_logic
|
||||
);
|
||||
end core_ex_branch_judge;
|
||||
BIN
hardware/ModelSim/work/core_ex_branch_judge/verilog.prw
Normal file
BIN
hardware/ModelSim/work/core_ex_branch_judge/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_ex_branch_judge/verilog.psm
Normal file
BIN
hardware/ModelSim/work/core_ex_branch_judge/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_id_stage/_primary.dat
Normal file
BIN
hardware/ModelSim/work/core_id_stage/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_id_stage/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/core_id_stage/_primary.dbs
Normal file
Binary file not shown.
26
hardware/ModelSim/work/core_id_stage/_primary.vhd
Normal file
26
hardware/ModelSim/work/core_id_stage/_primary.vhd
Normal file
@ -0,0 +1,26 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity core_id_stage is
|
||||
port(
|
||||
i_instr : in vl_logic_vector(31 downto 0);
|
||||
i_pc : in vl_logic_vector(31 downto 0);
|
||||
o_rs1_addr : out vl_logic_vector(4 downto 0);
|
||||
o_rs2_addr : out vl_logic_vector(4 downto 0);
|
||||
o_rs1_en : out vl_logic;
|
||||
o_rs2_en : out vl_logic;
|
||||
o_jal : out vl_logic;
|
||||
o_jalr : out vl_logic;
|
||||
o_branch_may : out vl_logic;
|
||||
o_nextpc2reg : out vl_logic;
|
||||
o_alures2reg : out vl_logic;
|
||||
o_memory2reg : out vl_logic;
|
||||
o_mem_write : out vl_logic;
|
||||
o_pc_plus_imm : out vl_logic_vector(31 downto 0);
|
||||
o_imm : out vl_logic_vector(31 downto 0);
|
||||
o_dst_reg_addr : out vl_logic_vector(4 downto 0);
|
||||
o_opcode : out vl_logic_vector(6 downto 0);
|
||||
o_funct7 : out vl_logic_vector(6 downto 0);
|
||||
o_funct3 : out vl_logic_vector(2 downto 0);
|
||||
o_next_pc : out vl_logic_vector(31 downto 0)
|
||||
);
|
||||
end core_id_stage;
|
||||
BIN
hardware/ModelSim/work/core_id_stage/verilog.prw
Normal file
BIN
hardware/ModelSim/work/core_id_stage/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_id_stage/verilog.psm
Normal file
BIN
hardware/ModelSim/work/core_id_stage/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_regfile/_primary.dat
Normal file
BIN
hardware/ModelSim/work/core_regfile/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_regfile/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/core_regfile/_primary.dbs
Normal file
Binary file not shown.
24
hardware/ModelSim/work/core_regfile/_primary.vhd
Normal file
24
hardware/ModelSim/work/core_regfile/_primary.vhd
Normal file
@ -0,0 +1,24 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity core_regfile is
|
||||
port(
|
||||
clk : in vl_logic;
|
||||
rst_n : in vl_logic;
|
||||
rd_latch : in vl_logic;
|
||||
i_re1 : in vl_logic;
|
||||
i_raddr1 : in vl_logic_vector(4 downto 0);
|
||||
o_rdata1 : out vl_logic_vector(31 downto 0);
|
||||
i_re2 : in vl_logic;
|
||||
i_raddr2 : in vl_logic_vector(4 downto 0);
|
||||
o_rdata2 : out vl_logic_vector(31 downto 0);
|
||||
i_we1 : in vl_logic;
|
||||
i_waddr1 : in vl_logic_vector(4 downto 0);
|
||||
i_wdata1 : in vl_logic_vector(31 downto 0);
|
||||
i_we2 : in vl_logic;
|
||||
i_waddr2 : in vl_logic_vector(4 downto 0);
|
||||
i_wdata2 : in vl_logic_vector(31 downto 0);
|
||||
i_we3 : in vl_logic;
|
||||
i_waddr3 : in vl_logic_vector(4 downto 0);
|
||||
i_wdata3 : in vl_logic_vector(31 downto 0)
|
||||
);
|
||||
end core_regfile;
|
||||
BIN
hardware/ModelSim/work/core_regfile/verilog.prw
Normal file
BIN
hardware/ModelSim/work/core_regfile/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_regfile/verilog.psm
Normal file
BIN
hardware/ModelSim/work/core_regfile/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_top/_primary.dat
Normal file
BIN
hardware/ModelSim/work/core_top/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_top/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/core_top/_primary.dbs
Normal file
Binary file not shown.
9
hardware/ModelSim/work/core_top/_primary.vhd
Normal file
9
hardware/ModelSim/work/core_top/_primary.vhd
Normal file
@ -0,0 +1,9 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity core_top is
|
||||
port(
|
||||
clk : in vl_logic;
|
||||
rst_n : in vl_logic;
|
||||
i_boot_addr : in vl_logic_vector(31 downto 0)
|
||||
);
|
||||
end core_top;
|
||||
BIN
hardware/ModelSim/work/core_top/verilog.prw
Normal file
BIN
hardware/ModelSim/work/core_top/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/core_top/verilog.psm
Normal file
BIN
hardware/ModelSim/work/core_top/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/instr_rom/_primary.dat
Normal file
BIN
hardware/ModelSim/work/instr_rom/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/instr_rom/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/instr_rom/_primary.dbs
Normal file
Binary file not shown.
8
hardware/ModelSim/work/instr_rom/_primary.vhd
Normal file
8
hardware/ModelSim/work/instr_rom/_primary.vhd
Normal file
@ -0,0 +1,8 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity instr_rom is
|
||||
port(
|
||||
clk : in vl_logic;
|
||||
rst_n : in vl_logic
|
||||
);
|
||||
end instr_rom;
|
||||
BIN
hardware/ModelSim/work/instr_rom/verilog.prw
Normal file
BIN
hardware/ModelSim/work/instr_rom/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/instr_rom/verilog.psm
Normal file
BIN
hardware/ModelSim/work/instr_rom/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/isp_uart/_primary.dat
Normal file
BIN
hardware/ModelSim/work/isp_uart/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/isp_uart/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/isp_uart/_primary.dbs
Normal file
Binary file not shown.
18
hardware/ModelSim/work/isp_uart/_primary.vhd
Normal file
18
hardware/ModelSim/work/isp_uart/_primary.vhd
Normal file
@ -0,0 +1,18 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity isp_uart is
|
||||
generic(
|
||||
UART_RX_CLK_DIV : integer := 108;
|
||||
UART_TX_CLK_DIV : integer := 434
|
||||
);
|
||||
port(
|
||||
clk : in vl_logic;
|
||||
i_uart_rx : in vl_logic;
|
||||
o_uart_tx : out vl_logic;
|
||||
o_rst_n : out vl_logic;
|
||||
o_boot_addr : out vl_logic_vector(31 downto 0)
|
||||
);
|
||||
attribute mti_svvh_generic_type : integer;
|
||||
attribute mti_svvh_generic_type of UART_RX_CLK_DIV : constant is 1;
|
||||
attribute mti_svvh_generic_type of UART_TX_CLK_DIV : constant is 1;
|
||||
end isp_uart;
|
||||
BIN
hardware/ModelSim/work/isp_uart/verilog.prw
Normal file
BIN
hardware/ModelSim/work/isp_uart/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/isp_uart/verilog.psm
Normal file
BIN
hardware/ModelSim/work/isp_uart/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/naive_bus/_primary.dat
Normal file
BIN
hardware/ModelSim/work/naive_bus/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/naive_bus/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/naive_bus/_primary.dbs
Normal file
Binary file not shown.
4
hardware/ModelSim/work/naive_bus/_primary.vhd
Normal file
4
hardware/ModelSim/work/naive_bus/_primary.vhd
Normal file
@ -0,0 +1,4 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity naive_bus is
|
||||
end naive_bus;
|
||||
BIN
hardware/ModelSim/work/naive_bus/verilog.prw
Normal file
BIN
hardware/ModelSim/work/naive_bus/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/naive_bus/verilog.psm
Normal file
BIN
hardware/ModelSim/work/naive_bus/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/naive_bus_router/_primary.dat
Normal file
BIN
hardware/ModelSim/work/naive_bus_router/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/naive_bus_router/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/naive_bus_router/_primary.dbs
Normal file
Binary file not shown.
19
hardware/ModelSim/work/naive_bus_router/_primary.vhd
Normal file
19
hardware/ModelSim/work/naive_bus_router/_primary.vhd
Normal file
@ -0,0 +1,19 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity naive_bus_router is
|
||||
generic(
|
||||
N_MASTER : vl_logic_vector(7 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1, Hi0);
|
||||
N_SLAVE : vl_logic_vector(7 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1, Hi1);
|
||||
SLAVES_MASK : vl_logic_vector;
|
||||
SLAVES_BASE : vl_logic_vector
|
||||
);
|
||||
port(
|
||||
clk : in vl_logic;
|
||||
rst_n : in vl_logic
|
||||
);
|
||||
attribute mti_svvh_generic_type : integer;
|
||||
attribute mti_svvh_generic_type of N_MASTER : constant is 2;
|
||||
attribute mti_svvh_generic_type of N_SLAVE : constant is 2;
|
||||
attribute mti_svvh_generic_type of SLAVES_MASK : constant is 4;
|
||||
attribute mti_svvh_generic_type of SLAVES_BASE : constant is 4;
|
||||
end naive_bus_router;
|
||||
BIN
hardware/ModelSim/work/naive_bus_router/verilog.prw
Normal file
BIN
hardware/ModelSim/work/naive_bus_router/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/naive_bus_router/verilog.psm
Normal file
BIN
hardware/ModelSim/work/naive_bus_router/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/ram/_primary.dat
Normal file
BIN
hardware/ModelSim/work/ram/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/ram/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/ram/_primary.dbs
Normal file
Binary file not shown.
12
hardware/ModelSim/work/ram/_primary.vhd
Normal file
12
hardware/ModelSim/work/ram/_primary.vhd
Normal file
@ -0,0 +1,12 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity ram is
|
||||
port(
|
||||
clk : in vl_logic;
|
||||
i_we : in vl_logic;
|
||||
i_waddr : in vl_logic_vector(9 downto 0);
|
||||
i_raddr : in vl_logic_vector(9 downto 0);
|
||||
i_wdata : in vl_logic_vector(7 downto 0);
|
||||
o_rdata : out vl_logic_vector(7 downto 0)
|
||||
);
|
||||
end ram;
|
||||
BIN
hardware/ModelSim/work/ram/verilog.prw
Normal file
BIN
hardware/ModelSim/work/ram/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/ram/verilog.psm
Normal file
BIN
hardware/ModelSim/work/ram/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/ram_bus_wrapper/_primary.dat
Normal file
BIN
hardware/ModelSim/work/ram_bus_wrapper/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/ram_bus_wrapper/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/ram_bus_wrapper/_primary.dbs
Normal file
Binary file not shown.
8
hardware/ModelSim/work/ram_bus_wrapper/_primary.vhd
Normal file
8
hardware/ModelSim/work/ram_bus_wrapper/_primary.vhd
Normal file
@ -0,0 +1,8 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity ram_bus_wrapper is
|
||||
port(
|
||||
clk : in vl_logic;
|
||||
rst_n : in vl_logic
|
||||
);
|
||||
end ram_bus_wrapper;
|
||||
BIN
hardware/ModelSim/work/ram_bus_wrapper/verilog.prw
Normal file
BIN
hardware/ModelSim/work/ram_bus_wrapper/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/ram_bus_wrapper/verilog.psm
Normal file
BIN
hardware/ModelSim/work/ram_bus_wrapper/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/soc_top/_primary.dat
Normal file
BIN
hardware/ModelSim/work/soc_top/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/soc_top/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/soc_top/_primary.dbs
Normal file
Binary file not shown.
19
hardware/ModelSim/work/soc_top/_primary.vhd
Normal file
19
hardware/ModelSim/work/soc_top/_primary.vhd
Normal file
@ -0,0 +1,19 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity soc_top is
|
||||
generic(
|
||||
UART_RX_CLK_DIV : integer := 108;
|
||||
UART_TX_CLK_DIV : integer := 434
|
||||
);
|
||||
port(
|
||||
clk : in vl_logic;
|
||||
isp_uart_rx : in vl_logic;
|
||||
isp_uart_tx : out vl_logic;
|
||||
vga_hsync : out vl_logic;
|
||||
vga_vsync : out vl_logic;
|
||||
vga_pixel : out vl_logic_vector(15 downto 0)
|
||||
);
|
||||
attribute mti_svvh_generic_type : integer;
|
||||
attribute mti_svvh_generic_type of UART_RX_CLK_DIV : constant is 1;
|
||||
attribute mti_svvh_generic_type of UART_TX_CLK_DIV : constant is 1;
|
||||
end soc_top;
|
||||
BIN
hardware/ModelSim/work/soc_top/verilog.prw
Normal file
BIN
hardware/ModelSim/work/soc_top/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/soc_top/verilog.psm
Normal file
BIN
hardware/ModelSim/work/soc_top/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/soc_top_tb/_primary.dat
Normal file
BIN
hardware/ModelSim/work/soc_top_tb/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/soc_top_tb/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/soc_top_tb/_primary.dbs
Normal file
Binary file not shown.
4
hardware/ModelSim/work/soc_top_tb/_primary.vhd
Normal file
4
hardware/ModelSim/work/soc_top_tb/_primary.vhd
Normal file
@ -0,0 +1,4 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity soc_top_tb is
|
||||
end soc_top_tb;
|
||||
BIN
hardware/ModelSim/work/soc_top_tb/verilog.prw
Normal file
BIN
hardware/ModelSim/work/soc_top_tb/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/soc_top_tb/verilog.psm
Normal file
BIN
hardware/ModelSim/work/soc_top_tb/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/uart_rx/_primary.dat
Normal file
BIN
hardware/ModelSim/work/uart_rx/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/uart_rx/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/uart_rx/_primary.dbs
Normal file
Binary file not shown.
15
hardware/ModelSim/work/uart_rx/_primary.vhd
Normal file
15
hardware/ModelSim/work/uart_rx/_primary.vhd
Normal file
@ -0,0 +1,15 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity uart_rx is
|
||||
generic(
|
||||
UART_RX_CLK_DIV : integer := 108
|
||||
);
|
||||
port(
|
||||
clk : in vl_logic;
|
||||
i_rx : in vl_logic;
|
||||
o_ready : out vl_logic;
|
||||
o_data : out vl_logic_vector(7 downto 0)
|
||||
);
|
||||
attribute mti_svvh_generic_type : integer;
|
||||
attribute mti_svvh_generic_type of UART_RX_CLK_DIV : constant is 1;
|
||||
end uart_rx;
|
||||
BIN
hardware/ModelSim/work/uart_rx/verilog.prw
Normal file
BIN
hardware/ModelSim/work/uart_rx/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/uart_rx/verilog.psm
Normal file
BIN
hardware/ModelSim/work/uart_rx/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/uart_tx_line/_primary.dat
Normal file
BIN
hardware/ModelSim/work/uart_tx_line/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/uart_tx_line/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/uart_tx_line/_primary.dbs
Normal file
Binary file not shown.
16
hardware/ModelSim/work/uart_tx_line/_primary.vhd
Normal file
16
hardware/ModelSim/work/uart_tx_line/_primary.vhd
Normal file
@ -0,0 +1,16 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity uart_tx_line is
|
||||
generic(
|
||||
UART_TX_CLK_DIV : integer := 434
|
||||
);
|
||||
port(
|
||||
clk : in vl_logic;
|
||||
o_tx : out vl_logic;
|
||||
i_start : in vl_logic;
|
||||
o_fin : out vl_logic;
|
||||
i_data : in vl_logic_vector(7 downto 0)
|
||||
);
|
||||
attribute mti_svvh_generic_type : integer;
|
||||
attribute mti_svvh_generic_type of UART_TX_CLK_DIV : constant is 1;
|
||||
end uart_tx_line;
|
||||
BIN
hardware/ModelSim/work/uart_tx_line/verilog.prw
Normal file
BIN
hardware/ModelSim/work/uart_tx_line/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/uart_tx_line/verilog.psm
Normal file
BIN
hardware/ModelSim/work/uart_tx_line/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/user_uart_tx/_primary.dat
Normal file
BIN
hardware/ModelSim/work/user_uart_tx/_primary.dat
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/user_uart_tx/_primary.dbs
Normal file
BIN
hardware/ModelSim/work/user_uart_tx/_primary.dbs
Normal file
Binary file not shown.
14
hardware/ModelSim/work/user_uart_tx/_primary.vhd
Normal file
14
hardware/ModelSim/work/user_uart_tx/_primary.vhd
Normal file
@ -0,0 +1,14 @@
|
||||
library verilog;
|
||||
use verilog.vl_types.all;
|
||||
entity user_uart_tx is
|
||||
generic(
|
||||
UART_TX_CLK_DIV : integer := 434
|
||||
);
|
||||
port(
|
||||
clk : in vl_logic;
|
||||
rst_n : in vl_logic;
|
||||
o_uart_tx : out vl_logic
|
||||
);
|
||||
attribute mti_svvh_generic_type : integer;
|
||||
attribute mti_svvh_generic_type of UART_TX_CLK_DIV : constant is 1;
|
||||
end user_uart_tx;
|
||||
BIN
hardware/ModelSim/work/user_uart_tx/verilog.prw
Normal file
BIN
hardware/ModelSim/work/user_uart_tx/verilog.prw
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/user_uart_tx/verilog.psm
Normal file
BIN
hardware/ModelSim/work/user_uart_tx/verilog.psm
Normal file
Binary file not shown.
BIN
hardware/ModelSim/work/vga/_primary.dat
Normal file
BIN
hardware/ModelSim/work/vga/_primary.dat
Normal file
Binary file not shown.
Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user