mirror of
https://github.com/WangXuan95/USTC-RVSoC.git
synced 2024-12-24 22:58:56 +08:00
add Arty7 Board
This commit is contained in:
WangXuan95
parent
b345b615e2
commit
fd2130f23d
45
README.md
45
README.md
@ -12,7 +12,8 @@ USTCRVSoC
|
||||
* [SoC结构](#SoC结构)
|
||||
* [CPU特性](#CPU特性)
|
||||
* [部署到FPGA](#部署到FPGA)
|
||||
* 部署到 Nexys4-DDR
|
||||
* 部署到 Nexys4
|
||||
* 部署到 Arty7
|
||||
* 部署到 DE0-Nano
|
||||
* 部署到其它开发板
|
||||
* [测试软件](#测试软件)
|
||||
@ -20,7 +21,9 @@ USTCRVSoC
|
||||
* 使用 UART 调试总线
|
||||
* 使用 VGA 屏幕
|
||||
* 使用工具：USTCRVSoC-tool
|
||||
* [RTL仿真](#RTL仿真)
|
||||
* [CPU仿真](#CPU仿真)
|
||||
* 进行仿真
|
||||
* [SoC仿真](#SoC仿真)
|
||||
* 进行仿真
|
||||
* 修改指令ROM
|
||||
|
||||
@ -68,7 +71,7 @@ USTCRVSoC
|
||||
|
||||
> LB, LH, LW, LBU, LHU, SB, SH, SW, ADD, ADDI, SUB, LUI, AUIPC, XOR, XORI, OR, ORI, AND, ANDI, SLL, SLLI, SRL, SRLI, SRA, SRAI, SLT, SLTI, SLTU, SLTIU, BEQ, BNE, BLT ,BGE, BLTU, BGEU, JAL, JALR
|
||||
|
||||
指令集方面，今后可能先考虑加入 **RV32IM** 中的乘除指令，再补全**RV32I**中未实现的指令
|
||||
指令集方面，今后可能先考虑加入 **RV32IM** 中的乘除指令。
|
||||
|
||||
CPU采用5段流水线，目前支持的流水线特性有：
|
||||
|
||||
@ -80,23 +83,27 @@ CPU采用5段流水线，目前支持的流水线特性有：
|
||||
|
||||
# 部署到FPGA
|
||||
|
||||
目前，我们提供了 Xilinx 的 **Nexys4-DDR** 开发板和 Altera 的 **DE0-Nano** 开发板的工程。
|
||||
目前，我们提供了 Xilinx 的 **Nexys4 开发板** 、 **Arty7 开发板** 和 Altera 的 **DE0-Nano 开发板** 的工程。
|
||||
|
||||
为了进行部署和测试，你需要准备以下的东西：
|
||||
|
||||
* 装有 **Windows7 系统** 或更高版本的 PC（如果使用 Linux 则很难用上我提供的几个C#编写的工具）
|
||||
* **Nexys4-DDR** 开发板或 **DE0-Nano** 开发板或其它 FPGA 开发板
|
||||
* 开发板对应的 **RTL 开发环境**，例如 Nexys4-DDR 对应 Vivado（推荐 Vivado 2017.4 或更高版本），DE0-Nano 对应 Quartus （推荐Quartus II 11.1 或更高版本）
|
||||
* 如果你的开发板没有自带 **USB转UART** 电路（例如 DE0-Nano 就不自带），则需要一个 **USB转UART模块**。
|
||||
* **Nexys4 开发板** 或 **Arty7 开发板** 或 **DE0-Nano 开发板** 或其它 FPGA 开发板
|
||||
* 开发板对应的 **RTL 开发环境**，例如 **Nexys4 开发板** 和 **Arty7 开发板** 对应 Vivado（推荐 Vivado 2018.3 或更高版本），DE0-Nano 对应 Quartus （推荐Quartus II 13.1 或更高版本）
|
||||
* 如果你的开发板没有自带 **USB转UART** 电路（例如 DE0-Nano），则需要一个 **USB转UART模块**。
|
||||
* **可选**：*屏幕、VGA线*
|
||||
|
||||
## 部署到 Nexys4-DDR
|
||||
## 部署到 Nexys4
|
||||
|
||||
|
||||
|
||||
1. **硬件连接**：如上图，Nexys4 开发板上有一个 USB 口，既可以用于 FPGA 烧录，也可以用于 UART 通信，我们需要连接该 USB 口到电脑。另外，VGA 的连接是可选的，你可以把它连接到屏幕上。
|
||||
2. **综合、烧写**：请用 Vivado 打开 **./hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr**。综合并烧写到开发板。
|
||||
2. **综合、烧写**：请用 Vivado 打开 **./hardware/Vivado/Nexys4/USTCRVSoC-nexys4.xpr**。综合并烧写到开发板。
|
||||
|
||||
## 部署到 Arty7
|
||||
|
||||
1. **硬件连接**：Arty7 开发板上有一个 USB 口，既可以用于 FPGA 烧录，也可以用于 UART 通信，我们需要连接该 USB 口到电脑。
|
||||
2. **综合、烧写**：请用 Vivado 打开 **./hardware/Vivado/Arty7/USTCRVSoC-Arty7.xpr**。综合并烧写到开发板。
|
||||
|
||||
## 部署到 DE0-Nano
|
||||
|
||||
@ -110,7 +117,7 @@ CPU采用5段流水线，目前支持的流水线特性有：
|
||||
|
||||
## 部署到其它开发板
|
||||
|
||||
如果很不幸，你手头的 FPGA 开发板既不是 Nexys4，也不是 DE0-Nano，则需要手动建立工程，连接信号到开发板顶层。分为以下步骤：
|
||||
如果很不幸，你手头的 FPGA 开发板不是上述开发板，则需要手动建立工程，连接信号到开发板顶层。分为以下步骤：
|
||||
|
||||
* **建立工程**：建立工程后，需要将 **./hardware/RTL/** 中的所有 .sv 文件添加进工程。
|
||||
* **编写顶层**：SoC 的顶层文件是 **./hardware/RTL/soc_top.sv**，你需要编写一个针对该开发板的顶层文件，调用 **soc_top**，并将 FPGA 的引脚连接到 **soc_top** 中。以下是对 **soc_top** 的信号说明。
|
||||
@ -255,20 +262,24 @@ UART 调试器有两种模式：
|
||||
> 关于**普林斯顿结构**：我们虽然区分了**指令RAM**、**数据RAM**、**显存RAM**，但这写存储器在普林斯顿结构中都没有区别。你可以把指令烧写到**数据RAM**、**显存RAM**中去运行，也可以把变量放在**指令RAM**中。甚至，指令和数据都可以放在**数据RAM**中，只要地址别冲突，程序也能正常运行。但是这样的运行效率就会降低，因为CPU的**指令接口**和**数据接口**会**争抢总线**。
|
||||
|
||||
|
||||
# CPU仿真
|
||||
|
||||
# RTL仿真
|
||||
|
||||
该仓库提供了 **Vivado** 和 **ModelSim-Altera** 两种仿真环境的仿真工程
|
||||
为了验证 CPU 能够正确的支持 RV32I 指令集，改仓库使用RiscV官方的指令集测试，提供针对了 CPU 仿真工程。
|
||||
|
||||
### 进行仿真
|
||||
|
||||
* 如果你用 **Vivado** ，请打开工程 **./hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr** ，工程已经选择了 **soc_top_tb.sv** 作为仿真的顶层，可以直接进行**行为仿真**。
|
||||
* 如果你用 **Quartus** ，请确认你也有 **ModelSim-Altera** 组件。使用 **ModelSim-Altera** 打开 **./hardware/ModelSim/USTCRVSoC.mpf**，编译之后请对**soc_top_tb**进行仿真。
|
||||
* 用 **Vivado** 打开工程 **./hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.xpr** ，可看见顶层文件为 **tb_core.sv** ，然后按照注释的指示进行仿真即可。
|
||||
|
||||
# SoC仿真
|
||||
|
||||
该仓库提供了 SoC 的整体仿真。
|
||||
|
||||
### 进行仿真
|
||||
|
||||
* 用 **Vivado** 打开工程 **./hardware/Simulation_SoC/Vivado_Simulation/Simulation_SoC.xpr** ，工程已经选择了 **tb_soc.sv** 作为仿真的顶层，可以直接进行**行为仿真**。
|
||||
|
||||
仿真时运行的指令流来自**指令ROM**，如果你还没修改过**指令ROM**，则仿真时可以看到 **uart_tx** 信号出现 **uart** 发送的波形，这是它在打印 **hello**。
|
||||
|
||||
> 提示：通常，安装 **Quartus** 时，如果不是刻意的不勾选，都会自动安装上 **ModelSim-Altera**
|
||||
|
||||
### 修改指令ROM
|
||||
|
||||
如果你想仿真某个指令流，需要对**指令ROM**进行修改。
|
||||
|
||||
@ -1,543 +0,0 @@
|
||||
; Copyright 1991-2009 Mentor Graphics Corporation
|
||||
;
|
||||
; All Rights Reserved.
|
||||
;
|
||||
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
|
||||
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
;
|
||||
|
||||
[Library]
|
||||
std = $MODEL_TECH/../std
|
||||
ieee = $MODEL_TECH/../ieee
|
||||
verilog = $MODEL_TECH/../verilog
|
||||
vital2000 = $MODEL_TECH/../vital2000
|
||||
std_developerskit = $MODEL_TECH/../std_developerskit
|
||||
synopsys = $MODEL_TECH/../synopsys
|
||||
modelsim_lib = $MODEL_TECH/../modelsim_lib
|
||||
sv_std = $MODEL_TECH/../sv_std
|
||||
|
||||
; Altera Primitive libraries
|
||||
;
|
||||
; VHDL Section
|
||||
;
|
||||
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
|
||||
altera = $MODEL_TECH/../altera/vhdl/altera
|
||||
altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
|
||||
lpm = $MODEL_TECH/../altera/vhdl/220model
|
||||
220model = $MODEL_TECH/../altera/vhdl/220model
|
||||
max = $MODEL_TECH/../altera/vhdl/max
|
||||
maxii = $MODEL_TECH/../altera/vhdl/maxii
|
||||
maxv = $MODEL_TECH/../altera/vhdl/maxv
|
||||
stratix = $MODEL_TECH/../altera/vhdl/stratix
|
||||
stratixii = $MODEL_TECH/../altera/vhdl/stratixii
|
||||
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
|
||||
hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii
|
||||
hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii
|
||||
hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv
|
||||
cyclone = $MODEL_TECH/../altera/vhdl/cyclone
|
||||
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
|
||||
cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii
|
||||
cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils
|
||||
sgate = $MODEL_TECH/../altera/vhdl/sgate
|
||||
stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx
|
||||
altgxb = $MODEL_TECH/../altera/vhdl/altgxb
|
||||
stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb
|
||||
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
|
||||
arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi
|
||||
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
|
||||
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
|
||||
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
|
||||
arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
|
||||
arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
|
||||
arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
|
||||
arriagx = $MODEL_TECH/../altera/vhdl/arriagx
|
||||
altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb
|
||||
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
|
||||
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
|
||||
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
|
||||
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
|
||||
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
|
||||
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
|
||||
cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
|
||||
hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi
|
||||
hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip
|
||||
stratixv = $MODEL_TECH/../altera/vhdl/stratixv
|
||||
stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
|
||||
stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
|
||||
arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
|
||||
arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
|
||||
arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
|
||||
arriav = $MODEL_TECH/../altera/vhdl/arriav
|
||||
cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
|
||||
twentynm = $MODEL_TECH/../altera/vhdl/twentynm
|
||||
twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
|
||||
twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
|
||||
;
|
||||
; Verilog Section
|
||||
;
|
||||
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
|
||||
altera_ver = $MODEL_TECH/../altera/verilog/altera
|
||||
altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
|
||||
lpm_ver = $MODEL_TECH/../altera/verilog/220model
|
||||
220model_ver = $MODEL_TECH/../altera/verilog/220model
|
||||
max_ver = $MODEL_TECH/../altera/verilog/max
|
||||
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
|
||||
maxv_ver = $MODEL_TECH/../altera/verilog/maxv
|
||||
stratix_ver = $MODEL_TECH/../altera/verilog/stratix
|
||||
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
|
||||
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
|
||||
arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx
|
||||
hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii
|
||||
hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii
|
||||
hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv
|
||||
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
|
||||
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
|
||||
cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii
|
||||
cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils
|
||||
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
|
||||
stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx
|
||||
altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb
|
||||
stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb
|
||||
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
|
||||
arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi
|
||||
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
|
||||
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
|
||||
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
|
||||
arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
|
||||
arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
|
||||
arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
|
||||
stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
|
||||
stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
|
||||
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
|
||||
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
|
||||
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
|
||||
stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
|
||||
stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
|
||||
stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
|
||||
arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
|
||||
arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
|
||||
arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
|
||||
arriav_ver = $MODEL_TECH/../altera/verilog/arriav
|
||||
arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
|
||||
arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
|
||||
cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
|
||||
cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
|
||||
cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
|
||||
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
|
||||
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
|
||||
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
|
||||
cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
|
||||
hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi
|
||||
hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip
|
||||
twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
|
||||
twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
|
||||
twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
|
||||
|
||||
work = work
|
||||
[vcom]
|
||||
; VHDL93 variable selects language version as the default.
|
||||
; Default is VHDL-2002.
|
||||
; Value of 0 or 1987 for VHDL-1987.
|
||||
; Value of 1 or 1993 for VHDL-1993.
|
||||
; Default or value of 2 or 2002 for VHDL-2002.
|
||||
; Default or value of 3 or 2008 for VHDL-2008.
|
||||
VHDL93 = 2002
|
||||
|
||||
; Show source line containing error. Default is off.
|
||||
; Show_source = 1
|
||||
|
||||
; Turn off unbound-component warnings. Default is on.
|
||||
; Show_Warning1 = 0
|
||||
|
||||
; Turn off process-without-a-wait-statement warnings. Default is on.
|
||||
; Show_Warning2 = 0
|
||||
|
||||
; Turn off null-range warnings. Default is on.
|
||||
; Show_Warning3 = 0
|
||||
|
||||
; Turn off no-space-in-time-literal warnings. Default is on.
|
||||
; Show_Warning4 = 0
|
||||
|
||||
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
||||
; Show_Warning5 = 0
|
||||
|
||||
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
||||
; Optimize_1164 = 0
|
||||
|
||||
; Turn on resolving of ambiguous function overloading in favor of the
|
||||
; "explicit" function declaration (not the one automatically created by
|
||||
; the compiler for each type declaration). Default is off.
|
||||
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
|
||||
; will match the behavior of synthesis tools.
|
||||
Explicit = 1
|
||||
|
||||
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
||||
; NoVital = 1
|
||||
|
||||
; Turn off VITAL compliance checking. Default is checking on.
|
||||
; NoVitalCheck = 1
|
||||
|
||||
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
||||
; IgnoreVitalErrors = 1
|
||||
|
||||
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
||||
; Show_VitalChecksWarnings = 0
|
||||
|
||||
; Keep silent about case statement static warnings.
|
||||
; Default is to give a warning.
|
||||
; NoCaseStaticError = 1
|
||||
|
||||
; Keep silent about warnings caused by aggregates that are not locally static.
|
||||
; Default is to give a warning.
|
||||
; NoOthersStaticError = 1
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "Loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on some limited synthesis rule compliance checking. Checks only:
|
||||
; -- signals used (read) by a process must be in the sensitivity list
|
||||
; CheckSynthesis = 1
|
||||
|
||||
; Activate optimizations on expressions that do not involve signals,
|
||||
; waits, or function/procedure/task invocations. Default is off.
|
||||
; ScalarOpts = 1
|
||||
|
||||
; Require the user to specify a configuration for all bindings,
|
||||
; and do not generate a compile time default binding for the
|
||||
; component. This will result in an elaboration error of
|
||||
; 'component not bound' if the user fails to do so. Avoids the rare
|
||||
; issue of a false dependency upon the unused default binding.
|
||||
; RequireConfigForAllDefaultBinding = 1
|
||||
|
||||
; Inhibit range checking on subscripts of arrays. Range checking on
|
||||
; scalars defined with subtypes is inhibited by default.
|
||||
; NoIndexCheck = 1
|
||||
|
||||
; Inhibit range checks on all (implicit and explicit) assignments to
|
||||
; scalar objects defined with subtypes.
|
||||
; NoRangeCheck = 1
|
||||
|
||||
[vlog]
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
||||
; Default is off.
|
||||
; Hazard = 1
|
||||
|
||||
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
||||
; insensitivity for module names. Default is no conversion.
|
||||
; UpCase = 1
|
||||
|
||||
; Turn on incremental compilation of modules. Default is off.
|
||||
; Incremental = 1
|
||||
|
||||
; Turns on lint-style checking.
|
||||
; Show_Lint = 1
|
||||
|
||||
[vsim]
|
||||
; Simulator resolution
|
||||
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
||||
Resolution = ps
|
||||
|
||||
; User time unit for run commands
|
||||
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
||||
; unit specified for Resolution. For example, if Resolution is 100ps,
|
||||
; then UserTimeUnit defaults to ps.
|
||||
; Should generally be set to default.
|
||||
UserTimeUnit = default
|
||||
|
||||
; Default run length
|
||||
RunLength = 100 ps
|
||||
|
||||
; Maximum iterations that can be run without advancing simulation time
|
||||
IterationLimit = 5000
|
||||
|
||||
; Directive to license manager:
|
||||
; vhdl Immediately reserve a VHDL license
|
||||
; vlog Immediately reserve a Verilog license
|
||||
; plus Immediately reserve a VHDL and Verilog license
|
||||
; nomgc Do not look for Mentor Graphics Licenses
|
||||
; nomti Do not look for Model Technology Licenses
|
||||
; noqueue Do not wait in the license queue when a license isn't available
|
||||
; viewsim Try for viewer license but accept simulator license(s) instead
|
||||
; of queuing for viewer license
|
||||
; License = plus
|
||||
|
||||
; Stop the simulator after a VHDL/Verilog assertion message
|
||||
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
||||
BreakOnAssertion = 3
|
||||
|
||||
; Assertion Message Format
|
||||
; %S - Severity Level
|
||||
; %R - Report Message
|
||||
; %T - Time of assertion
|
||||
; %D - Delta
|
||||
; %I - Instance or Region pathname (if available)
|
||||
; %% - print '%' character
|
||||
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||
|
||||
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
|
||||
; AssertFile = assert.log
|
||||
|
||||
; Default radix for all windows and commands...
|
||||
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
||||
DefaultRadix = symbolic
|
||||
|
||||
; VSIM Startup command
|
||||
; Startup = do startup.do
|
||||
|
||||
; File for saving command transcript
|
||||
TranscriptFile = transcript
|
||||
|
||||
; File for saving command history
|
||||
; CommandHistory = cmdhist.log
|
||||
|
||||
; Specify whether paths in simulator commands should be described
|
||||
; in VHDL or Verilog format.
|
||||
; For VHDL, PathSeparator = /
|
||||
; For Verilog, PathSeparator = .
|
||||
; Must not be the same character as DatasetSeparator.
|
||||
PathSeparator = /
|
||||
|
||||
; Specify the dataset separator for fully rooted contexts.
|
||||
; The default is ':'. For example, sim:/top
|
||||
; Must not be the same character as PathSeparator.
|
||||
DatasetSeparator = :
|
||||
|
||||
; Disable VHDL assertion messages
|
||||
; IgnoreNote = 1
|
||||
; IgnoreWarning = 1
|
||||
; IgnoreError = 1
|
||||
; IgnoreFailure = 1
|
||||
|
||||
; Default force kind. May be freeze, drive, deposit, or default
|
||||
; or in other terms, fixed, wired, or charged.
|
||||
; A value of "default" will use the signal kind to determine the
|
||||
; force kind, drive for resolved signals, freeze for unresolved signals
|
||||
; DefaultForceKind = freeze
|
||||
|
||||
; If zero, open files when elaborated; otherwise, open files on
|
||||
; first read or write. Default is 0.
|
||||
; DelayFileOpen = 1
|
||||
|
||||
; Control VHDL files opened for write.
|
||||
; 0 = Buffered, 1 = Unbuffered
|
||||
UnbufferedOutput = 0
|
||||
|
||||
; Control the number of VHDL files open concurrently.
|
||||
; This number should always be less than the current ulimit
|
||||
; setting for max file descriptors.
|
||||
; 0 = unlimited
|
||||
ConcurrentFileLimit = 40
|
||||
|
||||
; Control the number of hierarchical regions displayed as
|
||||
; part of a signal name shown in the Wave window.
|
||||
; A value of zero tells VSIM to display the full name.
|
||||
; The default is 0.
|
||||
; WaveSignalNameWidth = 0
|
||||
|
||||
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
||||
; and std_logic_signed packages.
|
||||
; StdArithNoWarnings = 1
|
||||
|
||||
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
||||
; NumericStdNoWarnings = 1
|
||||
|
||||
; Control the format of the (VHDL) FOR generate statement label
|
||||
; for each iteration. Do not quote it.
|
||||
; The format string here must contain the conversion codes %s and %d,
|
||||
; in that order, and no other conversion codes. The %s represents
|
||||
; the generate_label; the %d represents the generate parameter value
|
||||
; at a particular generate iteration (this is the position number if
|
||||
; the generate parameter is of an enumeration type). Embedded whitespace
|
||||
; is allowed (but discouraged); leading and trailing whitespace is ignored.
|
||||
; Application of the format must result in a unique scope name over all
|
||||
; such names in the design so that name lookup can function properly.
|
||||
; GenerateFormat = %s__%d
|
||||
|
||||
; Specify whether checkpoint files should be compressed.
|
||||
; The default is 1 (compressed).
|
||||
; CheckpointCompressMode = 0
|
||||
|
||||
; List of dynamically loaded objects for Verilog PLI applications
|
||||
; Veriuser = veriuser.sl
|
||||
|
||||
; Specify default options for the restart command. Options can be one
|
||||
; or more of: -force -nobreakpoint -nolist -nolog -nowave
|
||||
; DefaultRestartOptions = -force
|
||||
|
||||
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
||||
; (> 500 megabyte memory footprint). Default is disabled.
|
||||
; Specify number of megabytes to lock.
|
||||
; LockedMemory = 1000
|
||||
|
||||
; Turn on (1) or off (0) WLF file compression.
|
||||
; The default is 1 (compress WLF file).
|
||||
; WLFCompress = 0
|
||||
|
||||
; Specify whether to save all design hierarchy (1) in the WLF file
|
||||
; or only regions containing logged signals (0).
|
||||
; The default is 0 (save only regions with logged signals).
|
||||
; WLFSaveAllRegions = 1
|
||||
|
||||
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
||||
; to the specified amount of simulation time. When the limit is exceeded
|
||||
; the earliest times get truncated from the file.
|
||||
; If both time and size limits are specified the most restrictive is used.
|
||||
; UserTimeUnits are used if time units are not specified.
|
||||
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
|
||||
; WLFTimeLimit = 0
|
||||
|
||||
; WLF file size limit. Limit WLF file size, as closely as possible,
|
||||
; to the specified number of megabytes. If both time and size limits
|
||||
; are specified then the most restrictive is used.
|
||||
; The default is 0 (no limit).
|
||||
; WLFSizeLimit = 1000
|
||||
|
||||
; Specify whether or not a WLF file should be deleted when the
|
||||
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
||||
; The default is 0 (do not delete WLF file when simulation ends).
|
||||
; WLFDeleteOnQuit = 1
|
||||
|
||||
; Automatic SDF compilation
|
||||
; Disables automatic compilation of SDF files in flows that support it.
|
||||
; Default is on, uncomment to turn off.
|
||||
; NoAutoSDFCompile = 1
|
||||
|
||||
[lmc]
|
||||
|
||||
[msg_system]
|
||||
; Change a message severity or suppress a message.
|
||||
; The format is: <msg directive> = <msg number>[,<msg number>...]
|
||||
; Examples:
|
||||
; note = 3009
|
||||
; warning = 3033
|
||||
; error = 3010,3016
|
||||
; fatal = 3016,3033
|
||||
; suppress = 3009,3016,3043
|
||||
; The command verror <msg number> can be used to get the complete
|
||||
; description of a message.
|
||||
|
||||
; Control transcripting of elaboration/runtime messages.
|
||||
; The default is to have messages appear in the transcript and
|
||||
; recorded in the wlf file (messages that are recorded in the
|
||||
; wlf file can be viewed in the MsgViewer). The other settings
|
||||
; are to send messages only to the transcript or only to the
|
||||
; wlf file. The valid values are
|
||||
; both {default}
|
||||
; tran {transcript only}
|
||||
; wlf {wlf file only}
|
||||
; msgmode = both
|
||||
[Project]
|
||||
; Warning -- Do not edit the project properties directly.
|
||||
; Property names are dynamic in nature and property
|
||||
; values have special syntax. Changing property data directly
|
||||
; can result in a corrupt MPF file. All project properties
|
||||
; can be modified through project window dialogs.
|
||||
Project_Version = 6
|
||||
Project_DefaultLib = work
|
||||
Project_SortMethod = unused
|
||||
Project_Files_Count = 22
|
||||
Project_File_0 = ../RTL/vga_char_86x32.sv
|
||||
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551536388 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_1 = ../RTL/dual_read_port_ram_32x32.sv
|
||||
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551597268 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_2 = ../RTL/uart_rx.sv
|
||||
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_3 = ../RTL/ram128B.sv
|
||||
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551597237 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_4 = ../RTL/instr_rom.sv
|
||||
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1552416592 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_5 = ../RTL/video_ram.sv
|
||||
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551536461 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 21 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_6 = ../RTL/soc_top.sv
|
||||
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1552152562 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_7 = ../RTL/ram.sv
|
||||
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551597245 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_8 = ../RTL/ram_bus_wrapper.sv
|
||||
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1550846066 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_9 = ../RTL/core_bus_wrapper.sv
|
||||
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1552153482 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_10 = ../RTL/core_alu.sv
|
||||
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1552301004 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_11 = ../RTL/char8x16_rom.sv
|
||||
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551539060 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_12 = ../RTL/core_top.sv
|
||||
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1552364652 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_13 = ../RTL/soc_top_tb.sv
|
||||
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551980366 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_14 = ../RTL/user_uart_tx.sv
|
||||
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551512538 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_15 = ../RTL/core_regfile.sv
|
||||
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551587650 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_16 = ../RTL/uart_tx_line.sv
|
||||
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1551092170 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 18 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_17 = ../RTL/isp_uart.sv
|
||||
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1553085889 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_18 = ../RTL/core_id_stage.sv
|
||||
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1552301088 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_19 = ../RTL/core_id_segreg.sv
|
||||
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1552291334 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_20 = ../RTL/naive_bus.sv
|
||||
Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_21 = ../RTL/naive_bus_router.sv
|
||||
Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1549876350 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_Sim_Count = 0
|
||||
Project_Folder_Count = 0
|
||||
Echo_Compile_Output = 0
|
||||
Save_Compile_Report = 1
|
||||
Project_Opt_Count = 0
|
||||
ForceSoftPaths = 0
|
||||
ProjectStatusDelay = 5000
|
||||
VERILOG_DoubleClick = Edit
|
||||
VERILOG_CustomDoubleClick =
|
||||
SYSTEMVERILOG_DoubleClick = Edit
|
||||
SYSTEMVERILOG_CustomDoubleClick =
|
||||
VHDL_DoubleClick = Edit
|
||||
VHDL_CustomDoubleClick =
|
||||
PSL_DoubleClick = Edit
|
||||
PSL_CustomDoubleClick =
|
||||
TEXT_DoubleClick = Edit
|
||||
TEXT_CustomDoubleClick =
|
||||
SYSTEMC_DoubleClick = Edit
|
||||
SYSTEMC_CustomDoubleClick =
|
||||
TCL_DoubleClick = Edit
|
||||
TCL_CustomDoubleClick =
|
||||
MACRO_DoubleClick = Edit
|
||||
MACRO_CustomDoubleClick =
|
||||
VCD_DoubleClick = Edit
|
||||
VCD_CustomDoubleClick =
|
||||
SDF_DoubleClick = Edit
|
||||
SDF_CustomDoubleClick =
|
||||
XML_DoubleClick = Edit
|
||||
XML_CustomDoubleClick =
|
||||
LOGFILE_DoubleClick = Edit
|
||||
LOGFILE_CustomDoubleClick =
|
||||
UCDB_DoubleClick = Edit
|
||||
UCDB_CustomDoubleClick =
|
||||
TDB_DoubleClick = Edit
|
||||
TDB_CustomDoubleClick =
|
||||
UPF_DoubleClick = Edit
|
||||
UPF_CustomDoubleClick =
|
||||
PCF_DoubleClick = Edit
|
||||
PCF_CustomDoubleClick =
|
||||
PROJECT_DoubleClick = Edit
|
||||
PROJECT_CustomDoubleClick =
|
||||
VRM_DoubleClick = Edit
|
||||
VRM_CustomDoubleClick =
|
||||
DEBUGDATABASE_DoubleClick = Edit
|
||||
DEBUGDATABASE_CustomDoubleClick =
|
||||
DEBUGARCHIVE_DoubleClick = Edit
|
||||
DEBUGARCHIVE_CustomDoubleClick =
|
||||
Project_Major_Version = 10
|
||||
Project_Minor_Version = 6
|
||||
Binary file not shown.
@ -1,557 +0,0 @@
|
||||
m255
|
||||
K3
|
||||
13
|
||||
cModel Technology
|
||||
Z0 dC:\altera\13.1
|
||||
vchar8x16_rom
|
||||
Z1 DXx6 sv_std 3 std 0 22 F[19LRNL:5;XmIFh[XOPn1
|
||||
Z2 !s100 o2f[Z63nVmj1LkXUR2gYV2
|
||||
Z3 IfWD6eSM90m?f<@dU`0I=z1
|
||||
Z4 Va@LVMQ5NRI<^Z9ol70R>72
|
||||
Z5 !s105 char8x16_rom_sv_unit
|
||||
S1
|
||||
Z6 dE:\work-Lab\USTCRVSoC\hardware\ModelSim
|
||||
Z7 w1551539060
|
||||
Z8 8E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv
|
||||
Z9 FE:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv
|
||||
L0 11
|
||||
Z10 OV;L;10.1d;51
|
||||
r1
|
||||
31
|
||||
Z11 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv|
|
||||
Z12 o-work work -sv -O0
|
||||
Z13 !s108 1553097470.195000
|
||||
Z14 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vcore_alu
|
||||
R1
|
||||
Z15 !s100 Hk4ZKglo9R?FEGTlHS?RS3
|
||||
Z16 I;?0dB;^d2>`WcPoRi]9DM2
|
||||
Z17 V2=z`kD:UDa0dmK04A[zc03
|
||||
Z18 !s105 core_alu_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z19 w1552301004
|
||||
Z20 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv
|
||||
Z21 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z22 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv|
|
||||
R12
|
||||
Z23 !s108 1553097470.274000
|
||||
Z24 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vcore_bus_wrapper
|
||||
R1
|
||||
Z25 !s100 bLMJ?e2PRUSXIh?omY=o21
|
||||
Z26 I8?8blM:QBgboQ>cD^WDQ[2
|
||||
Z27 VbfmG<WkNEmK@hoVE9k?R90
|
||||
Z28 !s105 core_bus_wrapper_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z29 w1552153482
|
||||
Z30 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv
|
||||
Z31 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z32 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv|
|
||||
R12
|
||||
Z33 !s108 1553097470.345000
|
||||
Z34 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vcore_ex_branch_judge
|
||||
R1
|
||||
Z35 !s100 e`[4=hnRGoQ8ei^3k>On51
|
||||
Z36 IJFElj3c9672KTjE9TR>LF1
|
||||
Z37 V@jT?>bnOD2?j_T4=3fkh_3
|
||||
Z38 !s105 core_ex_branch_judge_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z39 w1549876350
|
||||
Z40 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
|
||||
Z41 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z42 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv|
|
||||
R12
|
||||
Z43 !s108 1551863114.833000
|
||||
Z44 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vcore_id_segreg
|
||||
R1
|
||||
Z45 !s100 NmNT@]NH@0I`ElC3^a=Lo0
|
||||
Z46 In63?fN7CjS8LQG3S<]G]A3
|
||||
Z47 V2S>Ne5nzezO5JlAB96g8>0
|
||||
Z48 !s105 core_id_segreg_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z49 w1552291334
|
||||
Z50 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv
|
||||
Z51 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv
|
||||
L0 2
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z52 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv|
|
||||
R12
|
||||
Z53 !s108 1553097470.416000
|
||||
Z54 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vcore_id_stage
|
||||
R1
|
||||
Z55 !s100 GJfVNLR7z^<kiCg<4L]b^1
|
||||
Z56 IW2gE_DGf2`B1c4gHVRl[>1
|
||||
Z57 VndjbGAd]39<]>2=o9ZJ:=1
|
||||
Z58 !s105 core_id_stage_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z59 w1552301088
|
||||
Z60 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv
|
||||
Z61 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z62 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv|
|
||||
R12
|
||||
Z63 !s108 1553097470.490000
|
||||
Z64 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vcore_regfile
|
||||
R1
|
||||
Z65 !s100 I^YE54Zo0N7Mh6`QiI<Oz3
|
||||
Z66 IoCmXUMJPHAOdI=TTQ4@AZ1
|
||||
Z67 VYWbXWbbKF]m<1R3jXPAMb3
|
||||
Z68 !s105 core_regfile_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z69 w1551587650
|
||||
Z70 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv
|
||||
Z71 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv
|
||||
L0 2
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z72 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv|
|
||||
R12
|
||||
Z73 !s108 1553097470.561000
|
||||
Z74 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vcore_top
|
||||
R1
|
||||
Z75 !s100 Zo9bz^7ThnSCB?@jM>2<z2
|
||||
Z76 IHiI>OZW_a7lHo3m1FDmQG2
|
||||
Z77 Vi7?O@h6m5O3BFF`kIdBUC2
|
||||
Z78 !s105 core_top_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z79 w1552364652
|
||||
Z80 8E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv
|
||||
Z81 FE:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z82 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv|
|
||||
R12
|
||||
Z83 !s108 1553097470.631000
|
||||
Z84 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vdual_read_port_ram_32x32
|
||||
R1
|
||||
Z85 !s100 fdb;joBRd?Kbjj708`H@K2
|
||||
Z86 IPRWQ3P[Jk_E9z0fS4::gE0
|
||||
Z87 Vl@[MQJH:k3R5DJ2AcgRCH1
|
||||
Z88 !s105 dual_read_port_ram_32x32_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z89 w1551597268
|
||||
Z90 8E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv
|
||||
Z91 FE:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z92 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv|
|
||||
R12
|
||||
Z93 !s108 1553097470.710000
|
||||
Z94 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vinstr_rom
|
||||
R1
|
||||
Z95 !s100 Bd]Z1a^3]kD30E<26M`Lm1
|
||||
Z96 IOc1Uo_kS08]?1_CKOHHU?0
|
||||
Z97 Vg27TzclZ3S3@lBLMlA`?L1
|
||||
Z98 !s105 instr_rom_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z99 w1552416592
|
||||
Z100 8E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv
|
||||
Z101 FE:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z102 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv|
|
||||
R12
|
||||
Z103 !s108 1553097470.788000
|
||||
Z104 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
visp_uart
|
||||
R1
|
||||
Z105 !s100 [9[iR_cBcg;?;bX>dKeaB0
|
||||
Z106 ICh9mFzgfo8b@4QmO624@U1
|
||||
Z107 V@@jZ3Y6;d=WD@H08`7cWF3
|
||||
Z108 !s105 isp_uart_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z109 w1553085889
|
||||
Z110 8E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv
|
||||
Z111 FE:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv
|
||||
L0 3
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z112 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv|
|
||||
R12
|
||||
Z113 !s108 1553097470.870000
|
||||
Z114 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
Ynaive_bus
|
||||
R1
|
||||
Z115 !s100 gFz59kzW]I]nGiaVoSo3O2
|
||||
Z116 Idj:03TOO?jDHzf[0c?lJ`2
|
||||
Z117 VKXR@0<URHIKN=UGzERidm1
|
||||
Z118 !s105 naive_bus_sv_unit
|
||||
S1
|
||||
R6
|
||||
R39
|
||||
Z119 8E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv
|
||||
Z120 FE:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv
|
||||
L0 4
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z121 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv|
|
||||
R12
|
||||
Z122 !s108 1553097470.946000
|
||||
Z123 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vnaive_bus_router
|
||||
R1
|
||||
Z124 !s100 nSRUejF=Q5]HdBmmdfzLA1
|
||||
Z125 I^NC0W49]?el6;z^6BojXI2
|
||||
Z126 VS<O=OM<>7@f0]AeUc<_5c0
|
||||
Z127 !s105 naive_bus_router_sv_unit
|
||||
S1
|
||||
R6
|
||||
R39
|
||||
Z128 8E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv
|
||||
Z129 FE:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z130 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv|
|
||||
R12
|
||||
Z131 !s108 1553097471.014000
|
||||
Z132 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vram
|
||||
R1
|
||||
Z133 !s100 TMn[TG8XXmK^UL@k7`ikC0
|
||||
Z134 INIlD0C@nO9Rk96M@_1B?92
|
||||
Z135 VjLloJg4mGdQ3i@ojJbWma2
|
||||
Z136 !s105 ram_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z137 w1551597245
|
||||
Z138 8E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv
|
||||
Z139 FE:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z140 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv|
|
||||
R12
|
||||
Z141 !s108 1553097471.091000
|
||||
Z142 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vram128B
|
||||
R1
|
||||
Z143 !s100 fJC_h9DFSL4_5I>=K<7NW1
|
||||
Z144 Il^2=EAV5B4zF?@PSE:S;I3
|
||||
Z145 V5VITH=L0J_KXn908[zCL23
|
||||
Z146 !s105 ram128B_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z147 w1551597237
|
||||
Z148 8E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv
|
||||
Z149 FE:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z150 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv|
|
||||
R12
|
||||
Z151 nram128@b
|
||||
Z152 !s108 1553097471.234000
|
||||
Z153 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vram_bus_wrapper
|
||||
R1
|
||||
Z154 !s100 U?Io3WFYaekAS0T@dW=V43
|
||||
Z155 I?^eTo:Go<IUo<UVJm@aFd0
|
||||
Z156 V^7VeTGko3:7B>^H5Y:FP:1
|
||||
Z157 !s105 ram_bus_wrapper_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z158 w1550846066
|
||||
Z159 8E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv
|
||||
Z160 FE:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z161 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv|
|
||||
R12
|
||||
Z162 !s108 1553097471.164000
|
||||
Z163 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vsoc_top
|
||||
R1
|
||||
Z164 !s100 c7@DJ3i4aKznCaD6`OcAf2
|
||||
Z165 IY3<DJCiMG<UdHWc8M42J[2
|
||||
Z166 VNE4E5g0B?BmQN]T>5NoOT3
|
||||
Z167 !s105 soc_top_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z168 w1552152562
|
||||
Z169 8E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv
|
||||
Z170 FE:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z171 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv|
|
||||
R12
|
||||
Z172 !s108 1553097471.329000
|
||||
Z173 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vsoc_top_tb
|
||||
R1
|
||||
Z174 !s100 >5zad59i52f<6jYFNl[UE2
|
||||
Z175 I7hf=@mlD?E>:AKDSDL2O]1
|
||||
Z176 VkLTgIQbfzI]@>Jm[T?T@F0
|
||||
Z177 !s105 soc_top_tb_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z178 w1551980366
|
||||
Z179 8E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv
|
||||
Z180 FE:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z181 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv|
|
||||
R12
|
||||
Z182 !s108 1553097471.403000
|
||||
Z183 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vuart_rx
|
||||
R1
|
||||
Z184 !s100 :`YDkKm;LaUQOjOXmaKB:0
|
||||
Z185 IL9Ji^>V6GeZ<;c7I`o3LQ1
|
||||
Z186 Vh0;PUSD9VYIXe2P@6jV9;0
|
||||
Z187 !s105 uart_rx_sv_unit
|
||||
S1
|
||||
R6
|
||||
R39
|
||||
Z188 8E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv
|
||||
Z189 FE:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z190 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv|
|
||||
R12
|
||||
Z191 !s108 1553097471.473000
|
||||
Z192 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vuart_tx_line
|
||||
R1
|
||||
Z193 !s100 WEQ@68?0=RGj1iFdbOOcP2
|
||||
Z194 IK1;[1cPPe^6]7LKQ15Lf21
|
||||
Z195 VW`_FG<Oo:1]3K5g>fF=@_3
|
||||
Z196 !s105 uart_tx_line_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z197 w1551092170
|
||||
Z198 8E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv
|
||||
Z199 FE:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv
|
||||
L0 2
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z200 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv|
|
||||
R12
|
||||
Z201 !s108 1553097471.550000
|
||||
Z202 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vuser_uart_tx
|
||||
R1
|
||||
Z203 !s100 YA]KWMS3fOD:CQT@0Y9C83
|
||||
Z204 I0JOL7FjkENP;iNc25_jl92
|
||||
Z205 V<1FQ0oW1UA`j`9IX[bcdE1
|
||||
Z206 !s105 user_uart_tx_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z207 w1551512538
|
||||
Z208 8E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv
|
||||
Z209 FE:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv
|
||||
L0 2
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z210 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv|
|
||||
R12
|
||||
Z211 !s108 1553097471.620000
|
||||
Z212 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv|
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vvga
|
||||
R1
|
||||
Z213 !s100 9f0>Y=7iSmCK^QMkzVhdz2
|
||||
Z214 IK]n:1gV]8z:A^2D<Og@_H3
|
||||
Z215 VR^SlDkaag;z6W]0_6nChW1
|
||||
Z216 !s105 video_ram_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z217 w1551166630
|
||||
Z218 8E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv
|
||||
Z219 FE:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv
|
||||
Z220 L0 147
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z221 !s108 1551505561.076000
|
||||
Z222 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv|
|
||||
Z223 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv|
|
||||
R12
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vvga_char_86x32
|
||||
R1
|
||||
Z224 !s100 c>9AM[`i8>D>79]^5c=iL3
|
||||
Z225 IXCM=P_6km0Hk^IPzU0S0N1
|
||||
Z226 VE<z=Jzg_7oWJ0YmQX2]MU3
|
||||
Z227 !s105 vga_char_86x32_sv_unit
|
||||
S1
|
||||
R6
|
||||
Z228 w1551536388
|
||||
Z229 8E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv
|
||||
Z230 FE:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
31
|
||||
Z231 !s90 -reportprogress|300|-work|work|-sv|E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv|
|
||||
R12
|
||||
!i10b 1
|
||||
!s85 0
|
||||
Z232 !s108 1553097471.696000
|
||||
Z233 !s107 E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv|
|
||||
!s101 -O0
|
||||
vvgaChar98x36
|
||||
R1
|
||||
Z234 !s100 3ih;Pko8X4XgOhl5e4_Gh0
|
||||
Z235 IaM^Q2hPSE=jENCH[nQnb^0
|
||||
Z236 VkYR^g;?9@>9aFYMNc5Beh0
|
||||
R216
|
||||
S1
|
||||
R6
|
||||
R217
|
||||
R218
|
||||
R219
|
||||
L0 82
|
||||
R10
|
||||
r1
|
||||
31
|
||||
R221
|
||||
R222
|
||||
R223
|
||||
R12
|
||||
Z237 nvga@char98x36
|
||||
!i10b 1
|
||||
!s85 0
|
||||
!s101 -O0
|
||||
vvideo_ram
|
||||
R1
|
||||
!i10b 1
|
||||
Z238 !s100 5Km:lJ5=^^Z=H?Vg4dnQM0
|
||||
Z239 I8o<maB2Sg[@UYiL96IX_I3
|
||||
Z240 V5JnUKWk;WPc^ACUnLK1_E3
|
||||
R216
|
||||
S1
|
||||
R6
|
||||
Z241 w1551536461
|
||||
R218
|
||||
R219
|
||||
L0 1
|
||||
R10
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
!s108 1553097471.776000
|
||||
!s107 E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv|
|
||||
R223
|
||||
!s101 -O0
|
||||
R12
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1,3 +0,0 @@
|
||||
m255
|
||||
K3
|
||||
cModel Technology
|
||||
@ -277,7 +277,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/char8x16_rom.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/ram128B.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_top.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_regfile.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_id_segreg.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_instr_bus_adapter.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_id_stage.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_alu.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../../RTL/core_bus_wrapper.sv
|
||||
|
||||
@ -1,12 +1,12 @@
|
||||
module DE0Nano_USTCRVSoC_top(
|
||||
//////////// CLOCK //////////
|
||||
//////////// CLOCK //////////
|
||||
input CLOCK_50,
|
||||
//////////// LED, KEY, Switch //////////
|
||||
output [7:0] LED,
|
||||
//////////// GPIO Header 1 //////////
|
||||
input [1:0] GPIO_0_IN,
|
||||
output [ 7:0] LED,
|
||||
//////////// GPIO Header 1 //////////
|
||||
input [ 1:0] GPIO_0_IN,
|
||||
inout [33:0] GPIO_0,
|
||||
input [1:0] GPIO_1_IN,
|
||||
input [ 1:0] GPIO_1_IN,
|
||||
inout [33:0] GPIO_1
|
||||
);
|
||||
|
||||
|
||||
@ -1,14 +0,0 @@
|
||||
quit -sim
|
||||
|
||||
|
||||
#工程所需要的文件
|
||||
vlog -sv -incr ../RTL/*.sv
|
||||
|
||||
vsim -t ps -voptargs="+acc" work.soc_top_tb
|
||||
|
||||
log -r /*
|
||||
radix 16
|
||||
|
||||
do wave.do
|
||||
|
||||
run 20us
|
||||
@ -1,7 +1,8 @@
|
||||
# USTCRVSoC 硬件
|
||||
|
||||
> * ./RTL 目录中是 SoC 全部的 SystemVerilog 代码。
|
||||
> * ./Quartus 目录中是基于 Altera FPGA 的工程，目前只有 DE0-Nano 开发板。
|
||||
> * ./Vivado 目录中是基于 Xilinx FPGA 的工程，目前只有 Nexys4 开发板。
|
||||
> * ./ModelSim 目录是基于 ModelSim 的仿真工程。
|
||||
> * 请注意，后三者的工程共用 ./RTL 目录，因此在一个工程里修改 SoC 代码也会导致其它工程中的代码发生变化
|
||||
> * ./Quartus 目录中是基于 Altera FPGA 的工程，目前有 DE0-Nano 开发板。
|
||||
> * ./Vivado 目录中是基于 Xilinx FPGA 的工程，目前有 Arty-7 开发板和 Nexys4 开发板。
|
||||
> * ./Simulation_SoC 目录是对整个 SoC 的仿真工程
|
||||
> * ./Simulation_RiscvCPU 目录是对 RiscV-CPU 进行的指令集测试仿真（使用RiscV官方测试）
|
||||
> * 请注意，所有工程共用 ./RTL 目录，因此在一个工程里修改 SoC 代码也会导致其它工程中的代码发生变化
|
||||
|
||||
34
hardware/RTL/.vscode/tasks.json
vendored
34
hardware/RTL/.vscode/tasks.json
vendored
@ -1,34 +0,0 @@
|
||||
{
|
||||
// See https://go.microsoft.com/fwlink/?LinkId=733558
|
||||
// for the documentation about the tasks.json format
|
||||
"version": "2.0.0",
|
||||
"tasks": [
|
||||
{
|
||||
"label": "Compile Verilog File",
|
||||
"type": "shell",
|
||||
"command": "cd ${fileDirname} ; iverilog -o ${fileBasename}.vvp ${fileBasename} ; vvp -N ${fileBasename}.vvp"
|
||||
},
|
||||
{
|
||||
"label": "Run GTKWave",
|
||||
"type": "shell",
|
||||
"command": "cd ${fileDirname} ; gtkwave out.vcd"
|
||||
}
|
||||
{
|
||||
"label": "build",
|
||||
"type": "shell",
|
||||
"command": "msbuild",
|
||||
"args": [
|
||||
// Ask msbuild to generate full paths for file names.
|
||||
"/property:GenerateFullPaths=true",
|
||||
"/t:build"
|
||||
],
|
||||
"group": "build",
|
||||
"presentation": {
|
||||
// Reveal the output only if unrecognized errors occur.
|
||||
"reveal": "silent"
|
||||
},
|
||||
// Use the standard MS compiler pattern to detect errors, warnings and infos
|
||||
"problemMatcher": "$msCompile"
|
||||
}
|
||||
]
|
||||
}
|
||||
@ -23,7 +23,7 @@ always_comb
|
||||
o_branch_jalr <= 1'b1;
|
||||
o_branch_jalr_target <= num1_plus_imm;
|
||||
end
|
||||
7'b1100011 : begin // BRANCH类
|
||||
7'b1100011 : begin // BRANCH<EFBFBD><EFBFBD>?
|
||||
case(i_funct3)
|
||||
3'b000 : o_branch_jalr <= (i_num1u == i_num2u); // BEQ
|
||||
3'b001 : o_branch_jalr <= (i_num1u != i_num2u); // BNE
|
||||
@ -35,7 +35,7 @@ always_comb
|
||||
endcase
|
||||
o_branch_jalr_target <= pc_plus_imm;
|
||||
end
|
||||
default : begin // 不跳转
|
||||
default : begin // 不跳<EFBFBD><EFBFBD>?
|
||||
o_branch_jalr <= 1'b0;
|
||||
o_branch_jalr_target <= 0;
|
||||
end
|
||||
@ -43,36 +43,42 @@ always_comb
|
||||
|
||||
always_comb
|
||||
casex({i_funct7,i_funct3,i_opcode})
|
||||
// JAL类与JALR类
|
||||
// JAL类与JALR<EFBFBD><EFBFBD>?
|
||||
17'bxxxxxxx_xxx_110x111 : o_res <= i_pc + 4; // JAL, JALR
|
||||
// LUI类
|
||||
// LUI<EFBFBD><EFBFBD>?
|
||||
17'bxxxxxxx_xxx_0110111 : o_res <= i_immu; // LUI
|
||||
// AUIPC类
|
||||
// AUIPC<EFBFBD><EFBFBD>?
|
||||
17'bxxxxxxx_xxx_0010111 : o_res <= pc_plus_imm ; // AUIPC
|
||||
// 算术类
|
||||
// 算术<EFBFBD><EFBFBD>?
|
||||
17'b0000000_000_0110011 : o_res <= i_num1u + i_num2u; // ADD
|
||||
17'bxxxxxxx_000_0010011 : o_res <= num1_plus_imm ; // ADDI
|
||||
17'b0100000_000_0110011 : o_res <= i_num1u - i_num2u; // SUB
|
||||
// 逻辑类
|
||||
// 逻辑<EFBFBD><EFBFBD>?
|
||||
17'b0000000_100_0110011 : o_res <= i_num1u ^ i_num2u; // XOR
|
||||
17'bxxxxxxx_100_0010011 : o_res <= i_num1u ^ i_immu ; // XORI
|
||||
17'b0000000_110_0110011 : o_res <= i_num1u | i_num2u; // OR
|
||||
17'bxxxxxxx_110_0010011 : o_res <= i_num1u | i_immu ; // ORI
|
||||
17'b0000000_111_0110011 : o_res <= i_num1u & i_num2u; // AND
|
||||
17'bxxxxxxx_111_0010011 : o_res <= i_num1u & i_immu ; // ANDI
|
||||
// 位移类
|
||||
// 位移<EFBFBD><EFBFBD>?
|
||||
17'b0000000_001_0110011 : o_res <= i_num1u << shamt_rs ; // SLL
|
||||
17'b0000000_001_0010011 : o_res <= i_num1u << shamt_imm; // SLLI
|
||||
17'b0000000_101_0110011 : o_res <= i_num1u >> shamt_rs ; // SRL
|
||||
17'b0000000_101_0010011 : o_res <= i_num1u >> shamt_imm; // SRL
|
||||
17'b0100000_101_0110011 : o_res <= i_num1s >> shamt_rs ; // SRA
|
||||
17'b0100000_101_0010011 : o_res <= i_num1s >> shamt_imm; // SRAI
|
||||
// 比较类
|
||||
17'b0100000_101_0110011 : begin // SRA
|
||||
o_res <= i_num1u >> shamt_rs;
|
||||
for(int i=0;i< shamt_rs;i++) o_res[31-i] <= i_num1u[31];
|
||||
end
|
||||
17'b0100000_101_0010011 : begin // SRAI
|
||||
o_res <= i_num1u >> shamt_imm;
|
||||
for(int i=0;i<shamt_imm;i++) o_res[31-i] <= i_num1u[31];
|
||||
end
|
||||
// 比较<E6AF94><E8BE83>?
|
||||
17'b0000000_010_0110011 : o_res <= (i_num1s < i_num2s) ? 1 : 0; // SLT
|
||||
17'bxxxxxxx_010_0010011 : o_res <= (i_num1s < i_imms ) ? 1 : 0; // SLTI
|
||||
17'b0000000_011_0110011 : o_res <= (i_num1u < i_num2u) ? 1 : 0; // SLTU
|
||||
17'bxxxxxxx_011_0010011 : o_res <= (i_num1u < i_immu ) ? 1 : 0; // SLTIU
|
||||
// 无操作
|
||||
// 无操<EFBFBD><EFBFBD>?
|
||||
default : o_res <= 0;
|
||||
endcase
|
||||
|
||||
|
||||
@ -1,60 +0,0 @@
|
||||
|
||||
module core_id_segreg(
|
||||
input logic clk, rst_n,
|
||||
input logic [31:0] i_boot_addr,
|
||||
input logic i_en, i_re, i_ex_jmp, i_id_jmp,
|
||||
input logic [31:0] i_ex_jmp_target, i_id_jmp_target,
|
||||
output logic [31:0] o_pc, o_instr,
|
||||
|
||||
naive_bus.master bus_master
|
||||
);
|
||||
logic [31:0] target_pc, instr_latch=0;
|
||||
logic conflict, conflict_latch=1'b0, instr_hold_n = 1'b0;
|
||||
|
||||
initial begin o_pc=0; end
|
||||
|
||||
assign bus_master.wr_req = 1'b0; // core never write instruction ram
|
||||
assign bus_master.wr_be = 4'h0;
|
||||
assign bus_master.wr_addr = 0;
|
||||
assign bus_master.wr_data = 0;
|
||||
assign bus_master.rd_req = i_re;
|
||||
assign bus_master.rd_be = {4{i_re}};
|
||||
assign bus_master.rd_addr = i_re ? target_pc : 0;
|
||||
assign conflict = (bus_master.rd_req & ~bus_master.rd_gnt);
|
||||
|
||||
always_comb
|
||||
if(i_ex_jmp)
|
||||
target_pc <= i_ex_jmp_target;
|
||||
else if(i_id_jmp)
|
||||
target_pc <= i_id_jmp_target;
|
||||
else if( ~(i_re) | conflict_latch)
|
||||
target_pc <= o_pc;
|
||||
else
|
||||
target_pc <= o_pc + 4;
|
||||
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if(~rst_n) begin
|
||||
instr_hold_n <= 1'b0;
|
||||
conflict_latch <= 1'b0;
|
||||
instr_latch <= 0;
|
||||
end else begin
|
||||
instr_hold_n <= i_re & i_en;
|
||||
conflict_latch <= conflict;
|
||||
instr_latch <= o_instr;
|
||||
end
|
||||
|
||||
always_comb
|
||||
if(~instr_hold_n)
|
||||
o_instr <= instr_latch;
|
||||
else if(i_ex_jmp | conflict_latch)
|
||||
o_instr <= 0;
|
||||
else
|
||||
o_instr <= bus_master.rd_data;
|
||||
|
||||
always @ (posedge clk)
|
||||
if(~rst_n)
|
||||
o_pc <= {i_boot_addr[31:2],2'b00} - 4;
|
||||
else
|
||||
o_pc <= target_pc;
|
||||
|
||||
endmodule
|
||||
@ -37,7 +37,7 @@ always_comb // calculate instruction type
|
||||
OPCODE_JALR : instr_type <= I_TYPE;
|
||||
OPCODE_BRANCH : instr_type <= B_TYPE;
|
||||
OPCODE_LUI : instr_type <= U_TYPE;
|
||||
OPCODE_ALI : instr_type <= (o_funct3==3'b011) ? IZ_TYPE : I_TYPE;
|
||||
OPCODE_ALI : instr_type <= I_TYPE;
|
||||
OPCODE_ALR : instr_type <= R_TYPE;
|
||||
OPCODE_LOAD : instr_type <= I_TYPE;
|
||||
OPCODE_STORE : instr_type <= S_TYPE;
|
||||
|
||||
61
hardware/RTL/core_instr_bus_adapter.sv
Normal file
61
hardware/RTL/core_instr_bus_adapter.sv
Normal file
@ -0,0 +1,61 @@
|
||||
|
||||
module core_instr_bus_adapter(
|
||||
input logic clk, rst_n,
|
||||
input logic [31:0] i_boot_addr,
|
||||
input logic i_stall, i_bus_disable,
|
||||
input logic i_ex_jmp, i_id_jmp,
|
||||
input logic [31:0] i_ex_target, i_id_target,
|
||||
output logic [31:0] o_pc, o_instr,
|
||||
|
||||
naive_bus.master bus_master
|
||||
);
|
||||
logic [31:0] npc, instr_hold=0;
|
||||
logic bus_busy=1'b0, stall_n = 1'b0;
|
||||
|
||||
initial o_pc=0;
|
||||
|
||||
assign bus_master.wr_req = 1'b0; // core never write via instruction bus
|
||||
assign bus_master.wr_be = 4'h0;
|
||||
assign bus_master.wr_addr = 0;
|
||||
assign bus_master.wr_data = 0;
|
||||
|
||||
assign bus_master.rd_req = ~i_bus_disable;
|
||||
assign bus_master.rd_be = {4{~i_bus_disable}};
|
||||
assign bus_master.rd_addr = npc;
|
||||
|
||||
always_comb
|
||||
if(i_ex_jmp)
|
||||
npc <= i_ex_target;
|
||||
else if(i_id_jmp)
|
||||
npc <= i_id_target;
|
||||
else if( i_bus_disable | bus_busy )
|
||||
npc <= o_pc;
|
||||
else
|
||||
npc <= o_pc + 4;
|
||||
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if(~rst_n) begin
|
||||
stall_n <= 1'b0;
|
||||
bus_busy <= 1'b0;
|
||||
instr_hold <= 0;
|
||||
end else begin
|
||||
stall_n <= ~i_stall;
|
||||
bus_busy <= (bus_master.rd_req & ~bus_master.rd_gnt);
|
||||
instr_hold <= o_instr;
|
||||
end
|
||||
|
||||
always_comb
|
||||
if(~stall_n)
|
||||
o_instr <= instr_hold;
|
||||
else if(i_ex_jmp | bus_busy)
|
||||
o_instr <= 0;
|
||||
else
|
||||
o_instr <= bus_master.rd_data;
|
||||
|
||||
always @ (posedge clk)
|
||||
if(~rst_n)
|
||||
o_pc <= {i_boot_addr[31:2],2'b00} - 4;
|
||||
else
|
||||
o_pc <= npc;
|
||||
|
||||
endmodule
|
||||
@ -51,19 +51,20 @@ assign loaduse =
|
||||
(id_src1_reg_en & mem_memory2reg & (id_src1_reg_addr==mem_dst_reg_addr) ) |
|
||||
(id_src2_reg_en & mem_memory2reg & (id_src2_reg_addr==mem_dst_reg_addr) ) ;
|
||||
|
||||
|
||||
// -------------------------------------------------------------------------------
|
||||
// PC controller - timing logic
|
||||
// Instruction Bus Adapter - timing logic
|
||||
// -------------------------------------------------------------------------------
|
||||
core_id_segreg core_id_segreg_inst(
|
||||
core_instr_bus_adapter core_instr_bus_adapter_i(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
.i_boot_addr ( i_boot_addr ),
|
||||
.i_en ( ~id_stall ),
|
||||
.i_re ( ~id_read_disable ),
|
||||
.i_stall ( id_read_disable | id_stall ),
|
||||
.i_bus_disable ( id_read_disable ),
|
||||
.i_ex_jmp ( ex_branch_jalr ),
|
||||
.i_ex_jmp_target ( ex_branch_jalr_target ),
|
||||
.i_ex_target ( ex_branch_jalr_target ),
|
||||
.i_id_jmp ( id_jal ),
|
||||
.i_id_jmp_target ( id_pc + id_imm ),
|
||||
.i_id_target ( id_pc + id_imm ),
|
||||
.o_pc ( id_pc ),
|
||||
.o_instr ( id_instr ),
|
||||
.bus_master ( instr_master )
|
||||
|
||||
@ -1,5 +1,3 @@
|
||||
`ifndef NAIVE_BUS_SV
|
||||
`define NAIVE_BUS_SV
|
||||
|
||||
interface naive_bus();
|
||||
// read interface
|
||||
@ -26,5 +24,3 @@ interface naive_bus();
|
||||
);
|
||||
|
||||
endinterface
|
||||
|
||||
`endif
|
||||
2722
hardware/Simulation_RiscvCPU/RISCV_RV32I_Test/testA_Assembly.txt
Normal file
2722
hardware/Simulation_RiscvCPU/RISCV_RV32I_Test/testA_Assembly.txt
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
3296
hardware/Simulation_RiscvCPU/RISCV_RV32I_Test/testB_Assembly.txt
Normal file
3296
hardware/Simulation_RiscvCPU/RISCV_RV32I_Test/testB_Assembly.txt
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
3549
hardware/Simulation_RiscvCPU/RISCV_RV32I_Test/testC_Assembly.txt
Normal file
3549
hardware/Simulation_RiscvCPU/RISCV_RV32I_Test/testC_Assembly.txt
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,33 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f74797065:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3139:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f696e:3133:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f6f7574:3436:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72657374617274:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72756e:3233:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72656c61756e6368:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f7265736574:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f63686f6f73655f70726f6a6563745f6c6f636174696f6e:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72646976696577735f77617665666f726d5f766965776572:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e6f626a6563747370616e656c5f73696d756c6174696f6e5f6f626a656374735f747265655f7461626c65:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e73636f70657370616e656c5f73696d756c6174655f73636f70655f7461626c65:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74636c636f6e736f6c65766965775f74636c5f636f6e736f6c655f636f64655f656469746f72:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6e616d65747265655f77617665666f726d5f6e616d655f74726565:31:00:00
|
||||
eof:3134170508
|
||||
@ -0,0 +1,8 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72656c61756e6368:3134:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72657374617274:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e666f7274696d65:3233:00:00
|
||||
eof:3163366878
|
||||
@ -0,0 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:1
|
||||
eof:
|
||||
@ -1,4 +1,4 @@
|
||||
version:1
|
||||
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
|
||||
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
|
||||
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
|
||||
eof:241934075
|
||||
eof:2427094519
|
||||
@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
@ -0,0 +1,72 @@
|
||||
//--------------------------------------------------------------------------------------------------------------
|
||||
// This project runs RISC-V official ISA test
|
||||
// see https://github.com/riscv/riscv-tests
|
||||
//--------------------------------------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module tb_core #(
|
||||
// Specify the instruction&data stream file to be tested here
|
||||
// We modified RISC-V official ISA test into 3 small tests (In path USTCRVSoC/hardware/Simulation_RiscvCPU/RISCV_RV32I_Test)
|
||||
|
||||
// notice: this is the file-path in my computer, dont forget to modify it
|
||||
parameter INSTRUCTION_STREAM_FILE = "E:\\FPGAcommon\\USTCRVSoC\\hardware\\Simulation_RiscvCPU\\RISCV_RV32I_Test\\testA_InstructionStream.txt"
|
||||
// "E:\\FPGAcommon\\USTCRVSoC\\hardware\\Simulation_RiscvCPU\\RISCV_RV32I_Test\\testB_InstructionStream.txt"
|
||||
// "E:\\FPGAcommon\\USTCRVSoC\\hardware\\Simulation_RiscvCPU\\RISCV_RV32I_Test\\testC_InstructionStream.txt"
|
||||
)();
|
||||
|
||||
logic [31:0] ram [4096]; // this ram stores both instruction and data
|
||||
|
||||
initial $readmemh(INSTRUCTION_STREAM_FILE, ram);
|
||||
|
||||
logic clk = 1'b1, rst_n = 1'b0;
|
||||
always #5 clk = ~clk; // 100MHz clock
|
||||
initial #40 rst_n = 1'b1;
|
||||
|
||||
naive_bus bus_masters[2]();
|
||||
naive_bus bus_slaves [1]();
|
||||
|
||||
// RV32I Core
|
||||
core_top core_top_inst(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
.i_boot_addr ( 0 ),
|
||||
.instr_master ( bus_masters[1] ),
|
||||
.data_master ( bus_masters[0] )
|
||||
);
|
||||
|
||||
naive_bus_router #(
|
||||
.N_MASTER ( 2 ),
|
||||
.N_SLAVE ( 1 ),
|
||||
.SLAVES_MASK ( { 32'h0000_ffff } ),
|
||||
.SLAVES_BASE ( { 32'h0000_0000 } )
|
||||
) soc_bus_router_inst (
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
.masters ( bus_masters ),
|
||||
.slaves ( bus_slaves )
|
||||
);
|
||||
|
||||
assign bus_slaves[0].rd_gnt = 1'b1;
|
||||
assign bus_slaves[0].wr_gnt = 1'b1;
|
||||
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if(~rst_n)
|
||||
bus_slaves[0].rd_data <= 0;
|
||||
else
|
||||
bus_slaves[0].rd_data <= ram[bus_slaves[0].rd_addr[14:2]];
|
||||
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if(~rst_n) begin
|
||||
end else begin
|
||||
if(bus_slaves[0].wr_be[0])
|
||||
ram[bus_slaves[0].wr_addr[14:2]][ 7: 0] <= bus_slaves[0].wr_data[ 7: 0];
|
||||
if(bus_slaves[0].wr_be[1])
|
||||
ram[bus_slaves[0].wr_addr[14:2]][15: 8] <= bus_slaves[0].wr_data[15: 8];
|
||||
if(bus_slaves[0].wr_be[2])
|
||||
ram[bus_slaves[0].wr_addr[14:2]][23:16] <= bus_slaves[0].wr_data[23:16];
|
||||
if(bus_slaves[0].wr_be[3])
|
||||
ram[bus_slaves[0].wr_addr[14:2]][31:24] <= bus_slaves[0].wr_data[31:24];
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,242 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="39" Path="E:/FPGAcommon/USTCRVSoC/hardware/Simulation_RiscvCPU/Vivado_Simulation/Simulation_RiscvCPU.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="e372d57f71614fa1a85b5802b90dfd55"/>
|
||||
<Option Name="Part" Val="xc7a35ticsg324-1L"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="31"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<File Path="$PPRDIR/../../RTL/core_alu.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/core_bus_wrapper.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/core_id_stage.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/core_instr_bus_adapter.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/core_regfile.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/core_top.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/dual_read_port_ram_32x32.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/naive_bus.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/naive_bus_router.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_core.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="tb_core"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters/>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
13
hardware/Simulation_SoC/Questsim/demo.tcl
Normal file
13
hardware/Simulation_SoC/Questsim/demo.tcl
Normal file
@ -0,0 +1,13 @@
|
||||
quit -sim
|
||||
|
||||
# source files
|
||||
vlog -sv -incr tb_soc.sv ../../RTL/*.sv
|
||||
|
||||
vsim -t ps -voptargs="+acc" work.tb_soc
|
||||
|
||||
log -r /*
|
||||
radix 16
|
||||
|
||||
do wave.do
|
||||
|
||||
run 20us
|
||||
@ -1,16 +1,17 @@
|
||||
module soc_top_tb();
|
||||
`timescale 1ns/1ns
|
||||
|
||||
logic clk;
|
||||
initial clk = 1'b1;
|
||||
always #1 clk = ~clk;
|
||||
module tb_soc();
|
||||
|
||||
wire isp_uart_tx, vga_hsync, vga_vsync;
|
||||
logic clk = 1'b1;
|
||||
always #5 clk = ~clk; // 100MHz clock
|
||||
|
||||
wire uart_tx, vga_hsync, vga_vsync;
|
||||
wire [ 2:0] vga_pixel;
|
||||
|
||||
soc_top soc_inst(
|
||||
.clk ( clk ),
|
||||
.isp_uart_rx ( 1'b1 ),
|
||||
.isp_uart_tx ( isp_uart_tx ),
|
||||
.isp_uart_tx ( uart_tx ),
|
||||
.vga_hsync ( vga_hsync ),
|
||||
.vga_vsync ( vga_vsync ),
|
||||
.vga_red ( vga_pixel[2] ),
|
||||
@ -18,6 +19,6 @@ soc_top soc_inst(
|
||||
.vga_blue ( vga_pixel[0] )
|
||||
);
|
||||
|
||||
initial #1000 $stop;
|
||||
initial #800000 $stop;
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,26 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f74797065:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f6f7574:3134:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e657770726f6a65637477697a6172645f646f5f6e6f745f737065636966795f736f75726365735f61745f746869735f74696d65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6e65775f70726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72756e:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72656c61756e6368:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f7265736574:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f63686f6f73655f70726f6a6563745f6c6f636174696f6e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:32:00:00
|
||||
eof:3418869837
|
||||
@ -0,0 +1,7 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72656c61756e6368:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e666f7274696d65:33:00:00
|
||||
eof:3580635558
|
||||
@ -0,0 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:1
|
||||
eof:
|
||||
@ -0,0 +1,4 @@
|
||||
version:1
|
||||
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
|
||||
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
|
||||
eof:2427094519
|
||||
@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
@ -0,0 +1 @@
|
||||
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
|
||||
@ -0,0 +1,24 @@
|
||||
`timescale 1ns/1ns
|
||||
|
||||
module tb_soc();
|
||||
|
||||
logic clk = 1'b1;
|
||||
always #5 clk = ~clk; // 100MHz clock
|
||||
|
||||
wire uart_tx, vga_hsync, vga_vsync;
|
||||
wire [ 2:0] vga_pixel;
|
||||
|
||||
soc_top soc_inst(
|
||||
.clk ( clk ),
|
||||
.isp_uart_rx ( 1'b1 ),
|
||||
.isp_uart_tx ( uart_tx ),
|
||||
.vga_hsync ( vga_hsync ),
|
||||
.vga_vsync ( vga_vsync ),
|
||||
.vga_red ( vga_pixel[2] ),
|
||||
.vga_green ( vga_pixel[1] ),
|
||||
.vga_blue ( vga_pixel[0] )
|
||||
);
|
||||
|
||||
initial #800000 $stop;
|
||||
|
||||
endmodule
|
||||
326
hardware/Simulation_SoC/Vivado_Simulation/Simulation_SoC.xpr
Normal file
326
hardware/Simulation_SoC/Vivado_Simulation/Simulation_SoC.xpr
Normal file
@ -0,0 +1,326 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="39" Path="E:/FPGAcommon/USTCRVSoC/hardware/Simulation_SoC/Vivado_Simulation/Simulation_SoC.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="6bcec6d9390e4db5bc5d5e1d4ecf8359"/>
|
||||
<Option Name="Part" Val="xc7a35ticsg324-1L"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="3"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<File Path="$PPRDIR/../../RTL/char8x16_rom.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/core_alu.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/core_bus_wrapper.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/core_id_stage.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/core_instr_bus_adapter.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/core_regfile.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/core_top.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/dual_read_port_ram_32x32.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/instr_rom.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/isp_uart.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/naive_bus.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/naive_bus_router.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/ram.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/ram128B.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/ram_bus_wrapper.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/soc_top.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/uart_rx.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/uart_tx_line.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/user_uart_tx.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/vga_char_86x32.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/video_ram.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_soc.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="tb_soc"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters/>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@ -0,0 +1,31 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f6f725f6372656174655f636f6e73747261696e745f66696c6573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:637265617465636f6e73747261696e747366696c6570616e656c5f66696c655f6e616d65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f74797065:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3631:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e746f6f6c6261726d67725f72756e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f62697467656e:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7365745f61735f746f70:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f737065636966795f62697473747265616d5f66696c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f63686f6f73655f70726f6a6563745f6c6f636174696f6e:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f6372656174655f70726f6a6563745f7375626469726563746f7279:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726366696c6570726f7070616e656c735f73696d756c6174696f6e:3233:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:32:00:00
|
||||
eof:219087460
|
||||
@ -0,0 +1,11 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574746f706e6f6465:31:00:00
|
||||
eof:3044315420
|
||||
@ -0,0 +1,4 @@
|
||||
version:1
|
||||
57656254616c6b5472616e736d697373696f6e417474656d70746564:2
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:1
|
||||
eof:
|
||||
39
hardware/Vivado/Arty7/USTCRVSoC-Arty7.cache/wt/synthesis.wdf
Normal file
39
hardware/Vivado/Arty7/USTCRVSoC-Arty7.cache/wt/synthesis.wdf
Normal file
@ -0,0 +1,39 @@
|
||||
version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78633761333574696373673332342d314c:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:41727479375f555354435256536f435f746f70:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a323873:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313032312e3830394d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3639392e3838334d42:00:00
|
||||
eof:3717510150
|
||||
@ -0,0 +1,8 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0">
|
||||
<HWSession Dir="hw_1" File="hw.xml"/>
|
||||
</labtools>
|
||||
@ -0,0 +1,35 @@
|
||||
|
||||
## Clock signal
|
||||
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
|
||||
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];
|
||||
|
||||
##RGB LEDs
|
||||
set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { LEDB[0] }]; #IO_L18N_T2_35 Sch=led0_b
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { LEDG[0] }]; #IO_L19N_T3_VREF_35 Sch=led0_g
|
||||
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { LEDR[0] }]; #IO_L19P_T3_35 Sch=led0_r
|
||||
set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { LEDB[1] }]; #IO_L20P_T3_35 Sch=led1_b
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { LEDG[1] }]; #IO_L21P_T3_DQS_35 Sch=led1_g
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { LEDR[1] }]; #IO_L20N_T3_35 Sch=led1_r
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { LEDB[2] }]; #IO_L21N_T3_DQS_35 Sch=led2_b
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { LEDG[2] }]; #IO_L22N_T3_35 Sch=led2_g
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { LEDR[2] }]; #IO_L22P_T3_35 Sch=led2_r
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { LEDB[3] }]; #IO_L23P_T3_35 Sch=led3_b
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { LEDG[3] }]; #IO_L24P_T3_35 Sch=led3_g
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { LEDR[3] }]; #IO_L23N_T3_35 Sch=led3_r
|
||||
|
||||
##LEDs
|
||||
set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L24N_T3_35 Sch=led[4]
|
||||
set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_25_35 Sch=led[5]
|
||||
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
|
||||
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
|
||||
|
||||
##USB-UART Interface
|
||||
set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { UART_TX }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
|
||||
set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { UART_RX }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
|
||||
|
||||
##Quad SPI Flash
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { FLASH_CS }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { FLASH_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { FLASH_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { FLASH_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { FLASH_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
@ -0,0 +1,45 @@
|
||||
|
||||
module Arty7_USTCRVSoC_top(
|
||||
input logic CLK100MHZ,
|
||||
output logic [3:0] LED,
|
||||
output logic [1:0] LEDB,
|
||||
output logic UART_TX,
|
||||
input logic UART_RX
|
||||
);
|
||||
|
||||
logic [26:0] cnt = 22'h0;
|
||||
|
||||
soc_top #(
|
||||
.UART_RX_CLK_DIV ( 217 ),
|
||||
.UART_TX_CLK_DIV ( 868 ),
|
||||
.VGA_CLK_DIV ( 2 )
|
||||
)soc_inst (
|
||||
.clk ( CLK100MHZ ),
|
||||
.isp_uart_rx ( UART_RX ),
|
||||
.isp_uart_tx ( UART_TX ),
|
||||
.vga_hsync ( ), // there is no VGA port on Arty-7
|
||||
.vga_vsync ( ), // so leave these pins float
|
||||
.vga_red ( ),
|
||||
.vga_green ( ),
|
||||
.vga_blue ( )
|
||||
);
|
||||
|
||||
// show UART on blue LED (RGB LED on Arty-7)
|
||||
assign LEDB = ~{UART_RX, UART_TX};
|
||||
|
||||
// blink leds to show that the clock is working
|
||||
always @ (posedge CLK100MHZ) begin
|
||||
case(cnt[26:24])
|
||||
3'd0 : LED <= 4'b0001;
|
||||
3'd1 : LED <= 4'b0010;
|
||||
3'd2 : LED <= 4'b0100;
|
||||
3'd3 : LED <= 4'b1000;
|
||||
3'd4 : LED <= 4'b1000;
|
||||
3'd5 : LED <= 4'b0100;
|
||||
3'd6 : LED <= 4'b0010;
|
||||
3'd7 : LED <= 4'b0001;
|
||||
endcase
|
||||
cnt++;
|
||||
end
|
||||
|
||||
endmodule
|
||||
310
hardware/Vivado/Arty7/USTCRVSoC-Arty7.xpr
Normal file
310
hardware/Vivado/Arty7/USTCRVSoC-Arty7.xpr
Normal file
@ -0,0 +1,310 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="39" Path="E:/FPGAcommon/USTCRVSoC/hardware/Vivado/Arty7/USTCRVSoC-Arty7.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="c2573b9a7fc0486c86ecf427da721e59"/>
|
||||
<Option Name="Part" Val="xc7a35ticsg324-1L"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../RTL/char8x16_rom.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/core_alu.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/core_bus_wrapper.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/core_id_stage.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/core_instr_bus_adapter.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/core_regfile.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/core_top.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/dual_read_port_ram_32x32.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/instr_rom.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/isp_uart.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/naive_bus.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/naive_bus_router.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/ram.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/ram128B.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/ram_bus_wrapper.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/soc_top.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/uart_rx.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/uart_tx_line.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/user_uart_tx.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/vga_char_86x32.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../RTL/video_ram.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Arty7_USTCRVSoC_top.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="Arty7_USTCRVSoC_top"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/new/Arty7.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35ticsg324-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters/>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@ -2,32 +2,34 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f73696d756c6174696f6e5f73706563696669635f68646c5f66696c6573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3332:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3430:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7265747265657461626c6570616e656c5f636f72655f747265655f7461626c65:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:637265617465636f6e73747261696e747366696c6570616e656c5f66696c655f6e616d65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f74797065:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f74797065:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:323037:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3733:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:333239:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3738:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f6f7574:3133:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f696e:3338:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f6f7574:313035:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68617264776172657472656570616e656c5f68617264776172655f747265655f7461626c65:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6970636f7265766965775f7461626265645f70616e65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c6f676d6f6e69746f725f6d6f6e69746f72:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f666c6f77:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f68656c70:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f7265706f7274:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746f6f6c73:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f76696577:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f77696e646f77:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e746f6f6c6261726d67725f72756e:3236:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e746f6f6c6261726d67725f72756e:3237:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e77696e6d656e756d67725f6c61796f7574:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d657373616765776974686f7074696f6e6469616c6f675f646f6e745f73686f775f746869735f6469616c6f675f616761696e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f7365766572697479:32:00:00
|
||||
@ -35,22 +37,29 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f637269746963616c5f7761726e696e6773:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f7761726e696e675f6d65737361676573:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e65746c69737474726565766965775f6e65746c6973745f74726565:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:3134:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:3233:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f736572766572:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f676f746f5f6e65746c6973745f64657369676e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6c6963656e73655f6d616e616765:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f70726f6a6563745f73756d6d617279:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7265706f7274735f77696e646f77:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f62697467656e:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f62697467656e:3139:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f696d706c656d656e746174696f6e:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72756e5f73796e746865736973:3230:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7365745f61735f746f70:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72756e:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7365745f61735f746f70:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f627265616b:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72657374617274:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72756e:3635:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72656c61756e6368:3139:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f7265736574:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:3232:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f646576696365:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061727463686f6f7365725f66616d696c795f63686f6f736572:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061727463686f6f7365725f7061727473:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:3236:00:00
|
||||
@ -62,23 +71,28 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d61727974696d696e6770616e656c5f70726f6a6563745f73756d6d6172795f74696d696e675f70616e656c5f746162626564:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d6172797574696c697a6174696f6e6761646765745f70726f6a6563745f73756d6d6172795f7574696c697a6174696f6e5f6761646765745f746162626564:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473756d6d6172797574696c697a6174696f6e70616e656c5f70726f6a6563745f73756d6d6172795f7574696c697a6174696f6e5f70616e656c5f746162626564:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f70726f70657274696573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f70726f70657274696573:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f73657474696e6773:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72646976696577735f77617665666f726d5f766965776572:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72646976696577735f77617665666f726d5f766965776572:3735:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f72756e5f6761646765745f7461626265645f70616e65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f73686f775f6572726f72:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72756e6761646765745f73686f775f7761726e696e675f616e645f6572726f725f6d657373616765735f696e5f6d65737361676573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f63616e63656c:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:3134:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e6c69766572756e666f72636f6d705f737065636966795f74696d655f616e645f756e697473:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e6f626a6563747370616e656c5f73696d756c6174696f6e5f6f626a656374735f747265655f7461626c65:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e73636f70657370616e656c5f73696d756c6174655f73636f70655f7461626c65:3430:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726366696c6570726f7070616e656c735f73696d756c6174696f6e:3234:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:3233:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f726566726573685f686965726172636879:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7374616c6572756e6469616c6f675f796573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73746174656d6f6e69746f725f72657365745f72756e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:746f756368706f696e747375727665796469616c6f675f6e6f:31:00:00
|
||||
eof:2155422609
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6e616d65747265655f77617665666f726d5f6e616d655f74726565:3135:00:00
|
||||
eof:921471974
|
||||
@ -1,27 +1,31 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:3134:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:3136:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f7365736572766572:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f726576696577:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697470726f70657274696573:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:3131:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697470726f70657274696573:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:3534:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:3230:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:3239:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6a65637473756d6d617279:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265706f72747574696c697a6174696f6e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:3230:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766566696c6570726f787968616e646c6572:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574746f706e6f6465:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574746f706e6f6465:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e666f7274696d65:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e627265616b:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72656c61756e6368:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72657374617274:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e666f7274696d65:3633:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7570646174657265676964:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b73796e746865736973:32:00:00
|
||||
eof:1799701292
|
||||
eof:2572897370
|
||||
@ -0,0 +1,4 @@
|
||||
version:1
|
||||
57656254616c6b5472616e736d697373696f6e417474656d70746564:13
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:26
|
||||
eof:
|
||||
@ -34,6 +34,6 @@ version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a333073:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313034382e3330354d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3735392e3538324d42:00:00
|
||||
eof:759944584
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313034342e3336374d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3732322e3134354d42:00:00
|
||||
eof:1614001231
|
||||
@ -0,0 +1,3 @@
|
||||
version:1
|
||||
73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
|
||||
eof:2511430288
|
||||
@ -0,0 +1,4 @@
|
||||
version:1
|
||||
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
|
||||
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
|
||||
eof:2427094519
|
||||
@ -0,0 +1 @@
|
||||
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
|
||||
@ -7,25 +7,6 @@
|
||||
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
|
||||
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
|
||||
|
||||
|
||||
##Switches
|
||||
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
|
||||
set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
|
||||
## LEDs
|
||||
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
@ -37,12 +18,12 @@ set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6]
|
||||
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b
|
||||
@ -180,8 +161,8 @@ set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
|
||||
|
||||
##USB-RS232 Interface
|
||||
set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_RX }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_TX }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
|
||||
|
||||
@ -0,0 +1,43 @@
|
||||
|
||||
module Nexys4_USTCRVSoC_top(
|
||||
input logic CLK100MHZ,
|
||||
output logic [9:0] LED,
|
||||
output logic UART_TX,
|
||||
input logic UART_RX,
|
||||
output logic VGA_HS, VGA_VS,
|
||||
output logic [3:0] VGA_R, VGA_G, VGA_B
|
||||
);
|
||||
|
||||
logic vga_red, vga_green, vga_blue;
|
||||
assign {VGA_R, VGA_G, VGA_B} = {{4{vga_red}}, {4{vga_green}}, {4{vga_blue}}};
|
||||
|
||||
soc_top #(
|
||||
.UART_RX_CLK_DIV ( 217 ),
|
||||
.UART_TX_CLK_DIV ( 868 ),
|
||||
.VGA_CLK_DIV ( 2 )
|
||||
) soc_inst (
|
||||
.clk ( CLK100MHZ ),
|
||||
.isp_uart_rx ( UART_RX ),
|
||||
.isp_uart_tx ( UART_TX ),
|
||||
.vga_hsync ( VGA_HS ),
|
||||
.vga_vsync ( VGA_VS ),
|
||||
.vga_red ( vga_red ),
|
||||
.vga_green ( vga_green ),
|
||||
.vga_blue ( vga_blue )
|
||||
);
|
||||
|
||||
// Show UART on LED
|
||||
assign LED[9:8] = ~{UART_RX, UART_TX};
|
||||
|
||||
// blink LED to show that clock is running
|
||||
reg [21:0] cnt = 22'h0;
|
||||
reg [ 7:0] flow = 7'h0;
|
||||
always @ (posedge CLK100MHZ) begin
|
||||
cnt <= cnt + 22'h1;
|
||||
if(cnt==22'h0)
|
||||
flow <= {flow[6:0], ~flow[7]};
|
||||
end
|
||||
|
||||
assign LED[7:0] = flow;
|
||||
|
||||
endmodule
|
||||
@ -1,9 +1,9 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2017.4 (64-bit) -->
|
||||
<!-- Product Version: Vivado v2018.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="35" Path="E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr">
|
||||
<Project Version="7" Minor="39" Path="E:/FPGAcommon/USTCRVSoC/hardware/Vivado/Nexys4/USTCRVSoC-nexys4.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="ddc8340f1eba4b8bbb076a11b9b82028"/>
|
||||
@ -31,7 +31,7 @@
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="1"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="40"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
@ -51,162 +51,141 @@
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../../RTL/char8x16_rom.sv">
|
||||
<File Path="$PPRDIR/../../RTL/char8x16_rom.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_alu.sv">
|
||||
<File Path="$PPRDIR/../../RTL/core_alu.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_bus_wrapper.sv">
|
||||
<File Path="$PPRDIR/../../RTL/core_bus_wrapper.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_id_segreg.sv">
|
||||
<File Path="$PPRDIR/../../RTL/core_id_stage.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_id_stage.sv">
|
||||
<File Path="$PPRDIR/../../RTL/core_instr_bus_adapter.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_regfile.sv">
|
||||
<File Path="$PPRDIR/../../RTL/core_regfile.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/core_top.sv">
|
||||
<File Path="$PPRDIR/../../RTL/core_top.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/dual_read_port_ram_32x32.sv">
|
||||
<File Path="$PPRDIR/../../RTL/dual_read_port_ram_32x32.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/instr_rom.sv">
|
||||
<File Path="$PPRDIR/../../RTL/instr_rom.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/isp_uart.sv">
|
||||
<File Path="$PPRDIR/../../RTL/isp_uart.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/naive_bus.sv">
|
||||
<File Path="$PPRDIR/../../RTL/naive_bus.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/naive_bus_router.sv">
|
||||
<File Path="$PPRDIR/../../RTL/naive_bus_router.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/ram.sv">
|
||||
<File Path="$PPRDIR/../../RTL/ram.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/ram128B.sv">
|
||||
<File Path="$PPRDIR/../../RTL/ram128B.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/ram_bus_wrapper.sv">
|
||||
<File Path="$PPRDIR/../../RTL/ram_bus_wrapper.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/soc_top.sv">
|
||||
<File Path="$PPRDIR/../../RTL/soc_top.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/uart_rx.sv">
|
||||
<File Path="$PPRDIR/../../RTL/uart_rx.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/uart_tx_line.sv">
|
||||
<File Path="$PPRDIR/../../RTL/uart_tx_line.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/user_uart_tx.sv">
|
||||
<File Path="$PPRDIR/../../RTL/user_uart_tx.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/vga_char_86x32.sv">
|
||||
<File Path="$PPRDIR/../../RTL/vga_char_86x32.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../RTL/video_ram.sv">
|
||||
<File Path="$PPRDIR/../../RTL/video_ram.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/Nexys4_USTCRVSoC_top.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
@ -228,22 +207,20 @@
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../../RTL/soc_top_tb.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="soc_top_tb"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
@ -264,7 +241,7 @@
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
|
||||
<Step Id="synth_design"/>
|
||||
@ -273,7 +250,7 @@
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
|
||||
<Step Id="init_design"/>
|
||||
@ -292,4 +269,36 @@
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters/>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
14
hardware/Vivado/Nexys4/vivado.jou
Normal file
14
hardware/Vivado/Nexys4/vivado.jou
Normal file
@ -0,0 +1,14 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Sun Sep 1 20:20:24 2019
|
||||
# Process ID: 14792
|
||||
# Current directory: E:/FPGAcommon/USTCRVSoC/hardware/Vivado/Nexys4
|
||||
# Command line: vivado.exe E:\FPGAcommon\USTCRVSoC\hardware\Vivado\Nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/FPGAcommon/USTCRVSoC/hardware/Vivado/Nexys4/vivado.log
|
||||
# Journal file: E:/FPGAcommon/USTCRVSoC/hardware/Vivado/Nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/FPGAcommon/USTCRVSoC/hardware/Vivado/Nexys4/USTCRVSoC-nexys4.xpr
|
||||
update_compile_order -fileset sources_1
|
||||
65
hardware/Vivado/Nexys4/vivado.log
Normal file
65
hardware/Vivado/Nexys4/vivado.log
Normal file
@ -0,0 +1,65 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Sun Sep 1 20:20:24 2019
|
||||
# Process ID: 14792
|
||||
# Current directory: E:/FPGAcommon/USTCRVSoC/hardware/Vivado/Nexys4
|
||||
# Command line: vivado.exe E:\FPGAcommon\USTCRVSoC\hardware\Vivado\Nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/FPGAcommon/USTCRVSoC/hardware/Vivado/Nexys4/vivado.log
|
||||
# Journal file: E:/FPGAcommon/USTCRVSoC/hardware/Vivado/Nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/FPGAcommon/USTCRVSoC/hardware/Vivado/Nexys4/USTCRVSoC-nexys4.xpr
|
||||
INFO: [Project 1-313] Project file moved from 'E:/FPGAcommon/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4' since last save.
|
||||
Scanning sources...
|
||||
Finished scanning sources
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/char8x16_rom.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/char8x16_rom.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/core_alu.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/core_alu.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/core_bus_wrapper.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/core_id_stage.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/core_id_stage.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/core_instr_bus_adapter.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/core_instr_bus_adapter.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/core_regfile.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/core_regfile.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/core_top.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/core_top.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/dual_read_port_ram_32x32.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/instr_rom.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/instr_rom.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/isp_uart.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/isp_uart.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/naive_bus.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/naive_bus.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/naive_bus_router.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/naive_bus_router.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/ram.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/ram.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/ram128B.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/ram128B.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/ram_bus_wrapper.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/soc_top.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/soc_top.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/uart_rx.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/uart_rx.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/uart_tx_line.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/uart_tx_line.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/user_uart_tx.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/user_uart_tx.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/vga_char_86x32.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/vga_char_86x32.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/video_ram.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/video_ram.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/char8x16_rom.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/char8x16_rom.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/core_alu.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/core_alu.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/core_bus_wrapper.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/core_id_stage.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/core_id_stage.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/core_instr_bus_adapter.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/core_instr_bus_adapter.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/core_regfile.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/core_regfile.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/core_top.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/core_top.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/dual_read_port_ram_32x32.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/instr_rom.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/instr_rom.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/isp_uart.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/isp_uart.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/naive_bus.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/naive_bus.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/naive_bus_router.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/naive_bus_router.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/ram.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/ram.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/ram128B.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/ram128B.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/ram_bus_wrapper.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/soc_top.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/soc_top.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/uart_rx.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/uart_rx.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/uart_tx_line.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/uart_tx_line.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/user_uart_tx.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/user_uart_tx.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/vga_char_86x32.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/vga_char_86x32.sv' instead.
|
||||
WARNING: [Project 1-312] File not found as 'E:/FPGAcommon/USTCRVSoC/RTL/video_ram.sv'; using path 'E:/FPGAcommon/USTCRVSoC/hardware/RTL/video_ram.sv' instead.
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'H:/Vivado2018/Vivado/2018.3/data/ip'.
|
||||
open_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:06 . Memory (MB): peak = 779.813 ; gain = 151.820
|
||||
update_compile_order -fileset sources_1
|
||||
exit
|
||||
INFO: [Common 17-206] Exiting Vivado at Sun Sep 1 20:21:31 2019...
|
||||
70
hardware/Vivado/Nexys4/vivado_12448.backup.log
Normal file
70
hardware/Vivado/Nexys4/vivado_12448.backup.log
Normal file
@ -0,0 +1,70 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Mon Mar 11 16:18:42 2019
|
||||
# Process ID: 12448
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent12796 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
Scanning sources...
|
||||
Finished scanning sources
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
|
||||
open_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 852.980 ; gain = 139.285
|
||||
update_compile_order -fileset sources_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 8
|
||||
[Mon Mar 11 16:19:50 2019] Launched synth_1...
|
||||
Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1/runme.log
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 8
|
||||
[Mon Mar 11 16:21:52 2019] Launched synth_1...
|
||||
Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1/runme.log
|
||||
launch_runs impl_1 -jobs 8
|
||||
[Mon Mar 11 16:24:05 2019] Launched impl_1...
|
||||
Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/runme.log
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
[Mon Mar 11 16:26:31 2019] Launched impl_1...
|
||||
Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/runme.log
|
||||
open_hw
|
||||
connect_hw_server
|
||||
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
|
||||
INFO: [Labtools 27-2222] Launching hw_server...
|
||||
INFO: [Labtools 27-2221] Launch Output:
|
||||
|
||||
****** Xilinx hw_server v2017.4
|
||||
**** Build date : Dec 15 2017-21:08:27
|
||||
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
open_hw_target
|
||||
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A8B5DFA
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
current_hw_device [get_hw_devices xc7a100t_0]
|
||||
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
||||
WARNING: [Labtools 27-3361] The debug hub core was not detected.
|
||||
Resolution:
|
||||
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
|
||||
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
|
||||
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
|
||||
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
program_hw_devices [get_hw_devices xc7a100t_0]
|
||||
INFO: [Labtools 27-3164] End of startup status: HIGH
|
||||
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
||||
WARNING: [Labtools 27-3361] The debug hub core was not detected.
|
||||
Resolution:
|
||||
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
|
||||
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
|
||||
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
|
||||
exit
|
||||
INFO: [Common 17-206] Exiting Vivado at Mon Mar 11 16:29:40 2019...
|
||||
46
hardware/Vivado/Nexys4/vivado_17980.backup.log
Normal file
46
hardware/Vivado/Nexys4/vivado_17980.backup.log
Normal file
@ -0,0 +1,46 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Tue Mar 12 00:06:43 2019
|
||||
# Process ID: 17980
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent15368 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
CRITICAL WARNING: [Project 1-19] Could not find the file 'E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv'.
|
||||
Scanning sources...
|
||||
Finished scanning sources
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
|
||||
open_project: Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 862.133 ; gain = 140.059
|
||||
update_compile_order -fileset sources_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 8
|
||||
[Tue Mar 12 00:07:28 2019] Launched synth_1...
|
||||
Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1/runme.log
|
||||
export_ip_user_files -of_objects [get_files E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv] -no_script -reset -force -quiet
|
||||
remove_files E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
|
||||
launch_runs impl_1 -jobs 8
|
||||
[Tue Mar 12 00:09:58 2019] Launched impl_1...
|
||||
Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/runme.log
|
||||
add_files -norecurse E:/work-Lab/RISCV-Pipline-CPU/1_VerilogSourceCode/1_CPUCore_src/BRAMModule/FakeCache.v
|
||||
update_compile_order -fileset sources_1
|
||||
export_ip_user_files -of_objects [get_files E:/work-Lab/RISCV-Pipline-CPU/1_VerilogSourceCode/1_CPUCore_src/BRAMModule/FakeCache.v] -no_script -reset -force -quiet
|
||||
remove_files E:/work-Lab/RISCV-Pipline-CPU/1_VerilogSourceCode/1_CPUCore_src/BRAMModule/FakeCache.v
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 8
|
||||
[Tue Mar 12 00:22:48 2019] Launched synth_1...
|
||||
Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1/runme.log
|
||||
launch_runs impl_1 -jobs 8
|
||||
[Tue Mar 12 00:31:54 2019] Launched impl_1...
|
||||
Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/runme.log
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
[Tue Mar 12 00:43:16 2019] Launched impl_1...
|
||||
Run output will be captured here: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/runme.log
|
||||
exit
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Mar 12 13:15:09 2019...
|
||||
23
hardware/Vivado/Nexys4/vivado_20220.backup.log
Normal file
23
hardware/Vivado/Nexys4/vivado_20220.backup.log
Normal file
@ -0,0 +1,23 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Sat Jul 20 15:34:02 2019
|
||||
# Process ID: 20220
|
||||
# Current directory: E:/FPGAcommon/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent17164 E:\FPGAcommon\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/FPGAcommon/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
# Journal file: E:/FPGAcommon/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/FPGAcommon/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
INFO: [Project 1-313] Project file moved from 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4' since last save.
|
||||
Scanning sources...
|
||||
Finished scanning sources
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'H:/Xilinx/Vivado/2017.4/data/ip'.
|
||||
open_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 827.039 ; gain = 88.969
|
||||
update_compile_order -fileset sources_1
|
||||
exit
|
||||
INFO: [Common 17-206] Exiting Vivado at Sat Jul 20 15:35:08 2019...
|
||||
170
hardware/Vivado/Nexys4/vivado_27748.backup.log
Normal file
170
hardware/Vivado/Nexys4/vivado_27748.backup.log
Normal file
@ -0,0 +1,170 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Thu Apr 11 23:30:43 2019
|
||||
# Process ID: 27748
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent69896 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
Scanning sources...
|
||||
Finished scanning sources
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'H:/Xilinx/Vivado/2017.4/data/ip'.
|
||||
open_project: Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 786.871 ; gain = 115.031
|
||||
update_compile_order -fileset sources_1
|
||||
open_hw
|
||||
connect_hw_server
|
||||
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
|
||||
INFO: [Labtools 27-2222] Launching hw_server...
|
||||
INFO: [Labtools 27-2221] Launch Output:
|
||||
|
||||
****** Xilinx hw_server v2017.4
|
||||
**** Build date : Dec 15 2017-21:08:27
|
||||
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
open_hw_target
|
||||
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
current_hw_device [get_hw_devices xc7a100t_0]
|
||||
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
||||
WARNING: [Labtools 27-3361] The debug hub core was not detected.
|
||||
Resolution:
|
||||
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
|
||||
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
|
||||
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
|
||||
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
program_hw_devices [get_hw_devices xc7a100t_0]
|
||||
INFO: [Labtools 27-3164] End of startup status: HIGH
|
||||
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
||||
WARNING: [Labtools 27-3361] The debug hub core was not detected.
|
||||
Resolution:
|
||||
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
|
||||
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
|
||||
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
|
||||
disconnect_hw_server localhost:3121
|
||||
connect_hw_server
|
||||
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
|
||||
INFO: [Labtools 27-2222] Launching hw_server...
|
||||
INFO: [Labtools 27-2221] Launch Output:
|
||||
|
||||
****** Xilinx hw_server v2017.4
|
||||
**** Build date : Dec 15 2017-21:08:27
|
||||
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
open_hw_target
|
||||
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
current_hw_device [get_hw_devices xc6slx16_0]
|
||||
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc6slx16_0] 0]
|
||||
INFO: [Labtools 27-1434] Device xc6slx16 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
||||
WARNING: [Labtools 27-3361] The debug hub core was not detected.
|
||||
Resolution:
|
||||
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
|
||||
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
|
||||
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
|
||||
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
INFO: [Labtools 27-1434] Device xc6slx16 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
||||
WARNING: [Labtools 27-3361] The debug hub core was not detected.
|
||||
Resolution:
|
||||
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
|
||||
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
|
||||
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
|
||||
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
|
||||
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
ERROR: [Labtools 27-2312] Device xc6slx16_0 is no longer available.
|
||||
Check cable connectivity and that the target board is powered up then
|
||||
use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target.
|
||||
Use open_hw_target to re-register the hardware device.
|
||||
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
|
||||
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
INFO: [Labtools 27-1434] Device xc6slx16 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
||||
WARNING: [Labtools 27-3361] The debug hub core was not detected.
|
||||
Resolution:
|
||||
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
|
||||
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
|
||||
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
|
||||
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
|
||||
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
disconnect_hw_server localhost:3121
|
||||
connect_hw_server
|
||||
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
|
||||
open_hw_target
|
||||
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A.
|
||||
Check cable connectivity and that the target board is powered up then
|
||||
use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
|
||||
ERROR: [Common 17-39] 'open_hw_target' failed due to earlier errors.
|
||||
disconnect_hw_server localhost:3121
|
||||
connect_hw_server
|
||||
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
|
||||
open_hw_target
|
||||
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A.
|
||||
Check cable connectivity and that the target board is powered up then
|
||||
use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
|
||||
ERROR: [Common 17-39] 'open_hw_target' failed due to earlier errors.
|
||||
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
INFO: [Labtools 27-1434] Device xc6slx16 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
||||
WARNING: [Labtools 27-3361] The debug hub core was not detected.
|
||||
Resolution:
|
||||
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
|
||||
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
|
||||
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
|
||||
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
|
||||
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
INFO: [Labtools 27-1434] Device xc6slx16 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
||||
WARNING: [Labtools 27-3361] The debug hub core was not detected.
|
||||
Resolution:
|
||||
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
|
||||
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
|
||||
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
|
||||
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
|
||||
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
||||
WARNING: [Labtools 27-3361] The debug hub core was not detected.
|
||||
Resolution:
|
||||
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
|
||||
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
|
||||
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
|
||||
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
|
||||
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
||||
WARNING: [Labtools 27-3361] The debug hub core was not detected.
|
||||
Resolution:
|
||||
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
|
||||
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
|
||||
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
|
||||
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
|
||||
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
|
||||
set_property PROGRAM.FILE {E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1/Nexys4_USTCRVSoC_top.bit} [get_hw_devices xc7a100t_0]
|
||||
program_hw_devices [get_hw_devices xc7a100t_0]
|
||||
INFO: [Labtools 27-3164] End of startup status: HIGH
|
||||
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
|
||||
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
||||
WARNING: [Labtools 27-3361] The debug hub core was not detected.
|
||||
Resolution:
|
||||
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
|
||||
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
|
||||
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
|
||||
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210292A8B2C7A
|
||||
exit
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri Apr 12 00:38:39 2019...
|
||||
22
hardware/Vivado/Nexys4/vivado_8068.backup.log
Normal file
22
hardware/Vivado/Nexys4/vivado_8068.backup.log
Normal file
@ -0,0 +1,22 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Sat Jul 20 15:35:22 2019
|
||||
# Process ID: 8068
|
||||
# Current directory: E:/FPGAcommon/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent20140 E:\FPGAcommon\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/FPGAcommon/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
# Journal file: E:/FPGAcommon/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/FPGAcommon/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
INFO: [Project 1-313] Project file moved from 'E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4' since last save.
|
||||
Scanning sources...
|
||||
Finished scanning sources
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'H:/Xilinx/Vivado/2017.4/data/ip'.
|
||||
update_compile_order -fileset sources_1
|
||||
exit
|
||||
INFO: [Common 17-206] Exiting Vivado at Sat Jul 20 16:01:36 2019...
|
||||
@ -1,4 +0,0 @@
|
||||
version:1
|
||||
57656254616c6b5472616e736d697373696f6e417474656d70746564:12
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:23
|
||||
eof:
|
||||
@ -1,137 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<document>
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Sat Jul 20 16:01:34 2019">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="802f49394334431ea9abba122e836e9e" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="33" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
|
||||
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
|
||||
<property name="DesignMode" value="RTL" type="DesignMode"/>
|
||||
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
|
||||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddSources" value="11" type="JavaHandler"/>
|
||||
<property name="AutoConnectTarget" value="16" type="JavaHandler"/>
|
||||
<property name="CloseServer" value="2" type="JavaHandler"/>
|
||||
<property name="CoreView" value="1" type="JavaHandler"/>
|
||||
<property name="CustomizeCore" value="1" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="7" type="JavaHandler"/>
|
||||
<property name="EditProperties" value="1" type="JavaHandler"/>
|
||||
<property name="LaunchProgramFpga" value="28" type="JavaHandler"/>
|
||||
<property name="NewProject" value="1" type="JavaHandler"/>
|
||||
<property name="OpenHardwareManager" value="54" type="JavaHandler"/>
|
||||
<property name="OpenRecentTarget" value="20" type="JavaHandler"/>
|
||||
<property name="ProgramDevice" value="29" type="JavaHandler"/>
|
||||
<property name="ProjectSummary" value="1" type="JavaHandler"/>
|
||||
<property name="ReportUtilization" value="1" type="JavaHandler"/>
|
||||
<property name="RunBitgen" value="17" type="JavaHandler"/>
|
||||
<property name="RunImplementation" value="15" type="JavaHandler"/>
|
||||
<property name="RunSynthesis" value="20" type="JavaHandler"/>
|
||||
<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/>
|
||||
<property name="SetTopNode" value="3" type="JavaHandler"/>
|
||||
<property name="ShowView" value="10" type="JavaHandler"/>
|
||||
<property name="SimulationRun" value="1" type="JavaHandler"/>
|
||||
<property name="SimulationRunForTime" value="9" type="JavaHandler"/>
|
||||
<property name="ToolsSettings" value="1" type="JavaHandler"/>
|
||||
<property name="UpdateRegId" value="1" type="JavaHandler"/>
|
||||
<property name="ViewTaskSynthesis" value="2" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="AddSrcWizard_SPECIFY_HDL_NETLIST_BLOCK_DESIGN" value="2" type="GuiHandlerData"/>
|
||||
<property name="AddSrcWizard_SPECIFY_SIMULATION_SPECIFIC_HDL_FILES" value="1" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CANCEL" value="5" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="32" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="3" type="GuiHandlerData"/>
|
||||
<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="2" type="GuiHandlerData"/>
|
||||
<property name="ConstraintsChooserPanel_ADD_FILES" value="1" type="GuiHandlerData"/>
|
||||
<property name="ConstraintsChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="3" type="GuiHandlerData"/>
|
||||
<property name="CreateConstraintsFilePanel_FILE_NAME" value="2" type="GuiHandlerData"/>
|
||||
<property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="CreateSrcFileDialog_FILE_TYPE" value="1" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="207" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="73" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="GraphicalView_ZOOM_OUT" value="13" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="8" type="GuiHandlerData"/>
|
||||
<property name="HardwareTreePanel_HARDWARE_TREE_TABLE" value="4" type="GuiHandlerData"/>
|
||||
<property name="IPCoreView_TABBED_PANE" value="2" type="GuiHandlerData"/>
|
||||
<property name="LogMonitor_MONITOR" value="4" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FLOW" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_HELP" value="4" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_REPORT" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_TOOLS" value="7" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_VIEW" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_WINDOW" value="8" type="GuiHandlerData"/>
|
||||
<property name="MainToolbarMgr_RUN" value="26" type="GuiHandlerData"/>
|
||||
<property name="MainWinMenuMgr_LAYOUT" value="2" type="GuiHandlerData"/>
|
||||
<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_SEVERITY" value="2" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="65" type="GuiHandlerData"/>
|
||||
<property name="MsgView_CRITICAL_WARNINGS" value="6" type="GuiHandlerData"/>
|
||||
<property name="MsgView_WARNING_MESSAGES" value="2" type="GuiHandlerData"/>
|
||||
<property name="NetlistTreeView_NETLIST_TREE" value="15" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_SOURCES" value="11" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_CONNECT_TARGET" value="18" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_UPDATE_HIER" value="17" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_CLOSE_SERVER" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GOTO_NETLIST_DESIGN" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_LICENSE_MANAGE" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_PROJECT_SUMMARY" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_REPORTS_WINDOW" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_BITGEN" value="18" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_IMPLEMENTATION" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RUN_SYNTHESIS" value="20" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SET_AS_TOP" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SIMULATION_LIVE_RUN" value="9" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="1" type="GuiHandlerData"/>
|
||||
<property name="PAViews_CODE" value="11" type="GuiHandlerData"/>
|
||||
<property name="PAViews_DEVICE" value="2" type="GuiHandlerData"/>
|
||||
<property name="PartChooser_FAMILY_CHOOSER" value="1" type="GuiHandlerData"/>
|
||||
<property name="PartChooser_PARTS" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProgramFpgaDialog_PROGRAM" value="26" type="GuiHandlerData"/>
|
||||
<property name="ProgramFpgaDialog_SPECIFY_BITSTREAM_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_PROJECT_NAME" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProjectSummaryTimingPanel_PROJECT_SUMMARY_TIMING_PANEL_TABBED" value="17" type="GuiHandlerData"/>
|
||||
<property name="ProjectSummaryUtilizationGadget_PROJECT_SUMMARY_UTILIZATION_GADGET_TABBED" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProjectSummaryUtilizationPanel_PROJECT_SUMMARY_UTILIZATION_PANEL_TABBED" value="5" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_DELETE" value="7" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_PROPERTIES" value="1" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_SETTINGS" value="1" type="GuiHandlerData"/>
|
||||
<property name="RDIViews_WAVEFORM_VIEWER" value="5" type="GuiHandlerData"/>
|
||||
<property name="RunGadget_RUN_GADGET_TABBED_PANE" value="1" type="GuiHandlerData"/>
|
||||
<property name="RunGadget_SHOW_ERROR" value="2" type="GuiHandlerData"/>
|
||||
<property name="RunGadget_SHOW_WARNING_AND_ERROR_MESSAGES_IN_MESSAGES" value="1" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_SAVE" value="5" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="7" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_HIERARCHY" value="14" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_REFRESH_HIERARCHY" value="1" type="GuiHandlerData"/>
|
||||
<property name="StaleRunDialog_YES" value="1" type="GuiHandlerData"/>
|
||||
<property name="StateMonitor_RESET_RUN" value="1" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="10" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaStateMonitor_CANCEL" value="3" type="GuiHandlerData"/>
|
||||
<property name="TaskBanner_CLOSE" value="3" type="GuiHandlerData"/>
|
||||
<property name="TouchpointSurveyDialog_NO" value="1" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="137" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="109" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
@ -1,17 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2017.4 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<hwsession version="1" minor="2">
|
||||
<device name="xc7a100t_0" gui_info=""/>
|
||||
<ObjectList object_type="hw_device" gui_info="">
|
||||
<Object name="xc7a100t_0" gui_info="">
|
||||
<Properties Property="FULL_PROBES.FILE" value=""/>
|
||||
<Properties Property="PROBES.FILE" value=""/>
|
||||
<Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/Nexys4_USTCRVSoC_top.bit"/>
|
||||
<Properties Property="SLR.COUNT" value="1"/>
|
||||
</Object>
|
||||
</ObjectList>
|
||||
<probeset name="hw project" active="false"/>
|
||||
</hwsession>
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
</Runs>
|
||||
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
|
||||
</Runs>
|
||||
|
||||
@ -1,8 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
|
||||
<Parent Id="synth_1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
</Runs>
|
||||
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
|
||||
</Runs>
|
||||
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
|
||||
</Runs>
|
||||
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
|
||||
</Runs>
|
||||
|
||||
@ -1,8 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
|
||||
<Parent Id="synth_1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
</Runs>
|
||||
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
</Runs>
|
||||
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
|
||||
</Runs>
|
||||
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
|
||||
</Runs>
|
||||
|
||||
@ -1,8 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
|
||||
<Parent Id="synth_1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
|
||||
</Runs>
|
||||
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
</Runs>
|
||||
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="impl_1" LaunchDir="E:/work-Lab/USTCRVSoC/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
|
||||
</Runs>
|
||||
|
||||
@ -1,44 +0,0 @@
|
||||
|
||||
module Nexys4_USTCRVSoC_top(
|
||||
input logic CLK100MHZ,
|
||||
input logic [15:0] SW,
|
||||
output logic [15:0] LED,
|
||||
output logic UART_RXD_OUT,
|
||||
input logic UART_TXD_IN,
|
||||
output logic VGA_HS, VGA_VS,
|
||||
output logic [3:0] VGA_R, VGA_G, VGA_B
|
||||
);
|
||||
|
||||
logic vga_red, vga_green, vga_blue;
|
||||
assign {VGA_R, VGA_G, VGA_B} = {{4{vga_red}}, {4{vga_green}}, {4{vga_blue}}};
|
||||
|
||||
soc_top #(
|
||||
.UART_RX_CLK_DIV ( 217 ),
|
||||
.UART_TX_CLK_DIV ( 868 ),
|
||||
.VGA_CLK_DIV ( 2 )
|
||||
)soc_inst (
|
||||
.clk ( CLK100MHZ ),
|
||||
.isp_uart_rx ( UART_TXD_IN ),
|
||||
.isp_uart_tx ( UART_RXD_OUT ),
|
||||
.vga_hsync ( VGA_HS ),
|
||||
.vga_vsync ( VGA_VS ),
|
||||
.vga_red ( vga_red ),
|
||||
.vga_green ( vga_green ),
|
||||
.vga_blue ( vga_blue )
|
||||
);
|
||||
|
||||
// <20>ڿ<EFBFBD><DABF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>LED<45><44><EFBFBD><EFBFBD>ʾISP-UART<52>ķ<EFBFBD><C4B7>͵ƺͽ<C6BA><CDBD>յ<EFBFBD>
|
||||
assign LED[15:14] = ~{UART_TXD_IN, UART_RXD_OUT};
|
||||
|
||||
// <20><>ˮ<EFBFBD>ƣ<EFBFBD>ָʾSoC<6F><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
reg [21:0] cnt = 22'h0;
|
||||
reg [ 7:0] flow = 7'h0;
|
||||
always @ (posedge CLK100MHZ) begin
|
||||
cnt <= cnt + 22'h1;
|
||||
if(cnt==22'h0)
|
||||
flow <= {flow[6:0], ~flow[7]};
|
||||
end
|
||||
|
||||
assign LED[7:0] = flow;
|
||||
|
||||
endmodule
|
||||
@ -1,23 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2017.4 (64-bit)
|
||||
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
|
||||
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
||||
# Start of session at: Sun Mar 10 22:06:31 2019
|
||||
# Process ID: 17240
|
||||
# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
|
||||
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11140 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
|
||||
# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
|
||||
# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
|
||||
update_compile_order -fileset sources_1
|
||||
add_files -norecurse E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_segreg.sv
|
||||
update_compile_order -fileset sources_1
|
||||
reset_run synth_1
|
||||
launch_runs synth_1 -jobs 8
|
||||
wait_on_run synth_1
|
||||
launch_runs impl_1 -jobs 8
|
||||
wait_on_run impl_1
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 8
|
||||
wait_on_run impl_1
|
||||
Loading…
x
Reference in New Issue
Block a user