优化regfile资源占用

hardware/ModelSim/USTCRVSoC.cr.mti

@@ -1,215 +0,0 @@
-../RTL/dual_read_port_ram_32x32.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/dual_read_port_ram_32x32.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module dual_read_port_ram_32x32
-
-Top level modules:
-	dual_read_port_ram_32x32
-
-} {} {}} ../RTL/vga_char_86x32.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/vga_char_86x32.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module vga_char_86x32
-
-Top level modules:
-	vga_char_86x32
-
-} {} {}} ../RTL/ram128B.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram128B.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module ram128B
-
-Top level modules:
-	ram128B
-
-} {} {}} ../RTL/uart_rx.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/uart_rx.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module uart_rx
-
-Top level modules:
-	uart_rx
-
-} {} {}} ../RTL/instr_rom.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/instr_rom.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module instr_rom
-
-Top level modules:
-	instr_rom
-
-} {} {}} ../RTL/video_ram.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/video_ram.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module video_ram
-
-Top level modules:
-	video_ram
-
-} {} {}} ../RTL/soc_top.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module soc_top
-
-Top level modules:
-	soc_top
-
-} {} {}} ../RTL/core_ex_branch_judge.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module core_ex_branch_judge
-
-Top level modules:
-	core_ex_branch_judge
-
-} {} {}} ../RTL/ram.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module ram
-
-Top level modules:
-	ram
-
-} {} {}} ../RTL/ram_bus_wrapper.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/ram_bus_wrapper.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module ram_bus_wrapper
-
-Top level modules:
-	ram_bus_wrapper
-
-} {} {}} ../RTL/core_alu.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_alu.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module core_alu
-
-Top level modules:
-	core_alu
-
-} {} {}} ../RTL/core_bus_wrapper.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_bus_wrapper.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module core_bus_wrapper
-
-Top level modules:
-	core_bus_wrapper
-
-} {} {}} ../RTL/char8x16_rom.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/char8x16_rom.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module char8x16_rom
-
-Top level modules:
-	char8x16_rom
-
-} {} {}} ../RTL/core_top.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_top.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module core_top
-
-Top level modules:
-	core_top
-
-} {} {}} ../RTL/soc_top_tb.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/soc_top_tb.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module soc_top_tb
-
-Top level modules:
-	soc_top_tb
-
-} {} {}} ../RTL/user_uart_tx.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/user_uart_tx.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module user_uart_tx
-
-Top level modules:
-	user_uart_tx
-
-} {} {}} ../RTL/uart_tx_line.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/uart_tx_line.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module uart_tx_line
-
-Top level modules:
-	uart_tx_line
-
-} {} {}} ../RTL/core_regfile.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_regfile.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module core_regfile
-
-Top level modules:
-	core_regfile
-
-} {} {}} ../RTL/isp_uart.sv {2 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module isp_uart
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv(92): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/isp_uart.sv(94): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-
-Top level modules:
-	isp_uart
-
-} {} {}} ../RTL/core_id_stage.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/core_id_stage.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module core_id_stage
-
-Top level modules:
-	core_id_stage
-
-} {} {}} ../RTL/naive_bus.sv {1 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling interface naive_bus
-
-Top level modules:
-	--none--
-
-} {} {}} ../RTL/naive_bus_router.sv {2 {vlog -work work -sv E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv
-Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
--- Compiling module naive_bus_router
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(64): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(65): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(66): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(67): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(68): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(69): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(70): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(71): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(72): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(73): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(73): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(75): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(76): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(77): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(78): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(81): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(82): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(83): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(84): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(85): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(96): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(97): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(98): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(99): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(99): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(101): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(102): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-** Warning: E:/work-Lab/USTCRVSoC/hardware/RTL/naive_bus_router.sv(105): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
-
-
-Top level modules:
-	naive_bus_router
-
-} {} {}}

hardware/ModelSim/work/char8x16_rom/_primary.vhd

@@ -1,9 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity char8x16_rom is
-    port(
-        clk             : in     vl_logic;
-        addr            : in     vl_logic_vector(11 downto 0);
-        data            : out    vl_logic_vector(7 downto 0)
-    );
-end char8x16_rom;

hardware/ModelSim/work/core_alu/_primary.vhd

@@ -1,14 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity core_alu is
-    port(
-        i_opcode        : in     vl_logic_vector(6 downto 0);
-        i_funct7        : in     vl_logic_vector(6 downto 0);
-        i_funct3        : in     vl_logic_vector(2 downto 0);
-        i_num1u         : in     vl_logic_vector(31 downto 0);
-        i_num2u         : in     vl_logic_vector(31 downto 0);
-        i_immu          : in     vl_logic_vector(31 downto 0);
-        i_pc_immu       : in     vl_logic_vector(31 downto 0);
-        o_res           : out    vl_logic_vector(31 downto 0)
-    );
-end core_alu;

hardware/ModelSim/work/core_bus_wrapper/_primary.vhd

@@ -1,17 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity core_bus_wrapper is
-    port(
-        clk             : in     vl_logic;
-        rst_n           : in     vl_logic;
-        i_en_n          : in     vl_logic;
-        i_re            : in     vl_logic;
-        i_we            : in     vl_logic;
-        o_conflict      : out    vl_logic;
-        o_conflict_latch: out    vl_logic;
-        i_funct3        : in     vl_logic_vector(2 downto 0);
-        i_addr          : in     vl_logic_vector(31 downto 0);
-        i_wdata         : in     vl_logic_vector(31 downto 0);
-        o_rdata         : out    vl_logic_vector(31 downto 0)
-    );
-end core_bus_wrapper;

hardware/ModelSim/work/core_ex_branch_judge/_primary.vhd

@@ -1,11 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity core_ex_branch_judge is
-    port(
-        i_branch        : in     vl_logic;
-        i_num1u         : in     vl_logic_vector(31 downto 0);
-        i_num2u         : in     vl_logic_vector(31 downto 0);
-        i_funct3        : in     vl_logic_vector(2 downto 0);
-        o_branch        : out    vl_logic
-    );
-end core_ex_branch_judge;

hardware/ModelSim/work/core_id_stage/_primary.vhd

@@ -1,26 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity core_id_stage is
-    port(
-        i_instr         : in     vl_logic_vector(31 downto 0);
-        i_pc            : in     vl_logic_vector(31 downto 0);
-        o_rs1_addr      : out    vl_logic_vector(4 downto 0);
-        o_rs2_addr      : out    vl_logic_vector(4 downto 0);
-        o_rs1_en        : out    vl_logic;
-        o_rs2_en        : out    vl_logic;
-        o_jal           : out    vl_logic;
-        o_jalr          : out    vl_logic;
-        o_branch_may    : out    vl_logic;
-        o_nextpc2reg    : out    vl_logic;
-        o_alures2reg    : out    vl_logic;
-        o_memory2reg    : out    vl_logic;
-        o_mem_write     : out    vl_logic;
-        o_pc_plus_imm   : out    vl_logic_vector(31 downto 0);
-        o_imm           : out    vl_logic_vector(31 downto 0);
-        o_dst_reg_addr  : out    vl_logic_vector(4 downto 0);
-        o_opcode        : out    vl_logic_vector(6 downto 0);
-        o_funct7        : out    vl_logic_vector(6 downto 0);
-        o_funct3        : out    vl_logic_vector(2 downto 0);
-        o_next_pc       : out    vl_logic_vector(31 downto 0)
-    );
-end core_id_stage;

hardware/ModelSim/work/core_regfile/_primary.vhd

@@ -1,24 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity core_regfile is
-    port(
-        clk             : in     vl_logic;
-        rst_n           : in     vl_logic;
-        rd_latch        : in     vl_logic;
-        i_re1           : in     vl_logic;
-        i_raddr1        : in     vl_logic_vector(4 downto 0);
-        o_rdata1        : out    vl_logic_vector(31 downto 0);
-        i_re2           : in     vl_logic;
-        i_raddr2        : in     vl_logic_vector(4 downto 0);
-        o_rdata2        : out    vl_logic_vector(31 downto 0);
-        i_forward1      : in     vl_logic;
-        i_faddr1        : in     vl_logic_vector(4 downto 0);
-        i_fdata1        : in     vl_logic_vector(31 downto 0);
-        i_forward2      : in     vl_logic;
-        i_faddr2        : in     vl_logic_vector(4 downto 0);
-        i_fdata2        : in     vl_logic_vector(31 downto 0);
-        i_we            : in     vl_logic;
-        i_waddr         : in     vl_logic_vector(4 downto 0);
-        i_wdata         : in     vl_logic_vector(31 downto 0)
-    );
-end core_regfile;

hardware/ModelSim/work/core_top/_primary.vhd

@@ -1,9 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity core_top is
-    port(
-        clk             : in     vl_logic;
-        rst_n           : in     vl_logic;
-        i_boot_addr     : in     vl_logic_vector(31 downto 0)
-    );
-end core_top;

hardware/ModelSim/work/instr_rom/_primary.vhd

@@ -1,8 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity instr_rom is
-    port(
-        clk             : in     vl_logic;
-        rst_n           : in     vl_logic
-    );
-end instr_rom;

hardware/ModelSim/work/isp_uart/_primary.vhd

@@ -1,18 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity isp_uart is
-    generic(
-        UART_RX_CLK_DIV : integer := 108;
-        UART_TX_CLK_DIV : integer := 434
-    );
-    port(
-        clk             : in     vl_logic;
-        i_uart_rx       : in     vl_logic;
-        o_uart_tx       : out    vl_logic;
-        o_rst_n         : out    vl_logic;
-        o_boot_addr     : out    vl_logic_vector(31 downto 0)
-    );
-    attribute mti_svvh_generic_type : integer;
-    attribute mti_svvh_generic_type of UART_RX_CLK_DIV : constant is 1;
-    attribute mti_svvh_generic_type of UART_TX_CLK_DIV : constant is 1;
-end isp_uart;

hardware/ModelSim/work/naive_bus/_primary.vhd

@@ -1,4 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity naive_bus is
-end naive_bus;

hardware/ModelSim/work/naive_bus_router/_primary.vhd

@@ -1,19 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity naive_bus_router is
-    generic(
-        N_MASTER        : vl_logic_vector(7 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1, Hi0);
-        N_SLAVE         : vl_logic_vector(7 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1, Hi1);
-        SLAVES_MASK     : vl_logic_vector;
-        SLAVES_BASE     : vl_logic_vector
-    );
-    port(
-        clk             : in     vl_logic;
-        rst_n           : in     vl_logic
-    );
-    attribute mti_svvh_generic_type : integer;
-    attribute mti_svvh_generic_type of N_MASTER : constant is 2;
-    attribute mti_svvh_generic_type of N_SLAVE : constant is 2;
-    attribute mti_svvh_generic_type of SLAVES_MASK : constant is 4;
-    attribute mti_svvh_generic_type of SLAVES_BASE : constant is 4;
-end naive_bus_router;

hardware/ModelSim/work/ram/_primary.vhd

@@ -1,12 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity ram is
-    port(
-        clk             : in     vl_logic;
-        i_we            : in     vl_logic;
-        i_waddr         : in     vl_logic_vector(9 downto 0);
-        i_raddr         : in     vl_logic_vector(9 downto 0);
-        i_wdata         : in     vl_logic_vector(7 downto 0);
-        o_rdata         : out    vl_logic_vector(7 downto 0)
-    );
-end ram;

hardware/ModelSim/work/ram_bus_wrapper/_primary.vhd

@@ -1,8 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity ram_bus_wrapper is
-    port(
-        clk             : in     vl_logic;
-        rst_n           : in     vl_logic
-    );
-end ram_bus_wrapper;

hardware/ModelSim/work/soc_top/_primary.vhd

@@ -1,23 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity soc_top is
-    generic(
-        UART_RX_CLK_DIV : integer := 108;
-        UART_TX_CLK_DIV : integer := 434;
-        VGA_CLK_DIV     : integer := 1
-    );
-    port(
-        clk             : in     vl_logic;
-        isp_uart_rx     : in     vl_logic;
-        isp_uart_tx     : out    vl_logic;
-        vga_hsync       : out    vl_logic;
-        vga_vsync       : out    vl_logic;
-        vga_red         : out    vl_logic;
-        vga_green       : out    vl_logic;
-        vga_blue        : out    vl_logic
-    );
-    attribute mti_svvh_generic_type : integer;
-    attribute mti_svvh_generic_type of UART_RX_CLK_DIV : constant is 1;
-    attribute mti_svvh_generic_type of UART_TX_CLK_DIV : constant is 1;
-    attribute mti_svvh_generic_type of VGA_CLK_DIV : constant is 1;
-end soc_top;

hardware/ModelSim/work/soc_top_tb/_primary.vhd

@@ -1,4 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity soc_top_tb is
-end soc_top_tb;

hardware/ModelSim/work/uart_rx/_primary.vhd

@@ -1,15 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity uart_rx is
-    generic(
-        UART_RX_CLK_DIV : integer := 108
-    );
-    port(
-        clk             : in     vl_logic;
-        i_rx            : in     vl_logic;
-        o_ready         : out    vl_logic;
-        o_data          : out    vl_logic_vector(7 downto 0)
-    );
-    attribute mti_svvh_generic_type : integer;
-    attribute mti_svvh_generic_type of UART_RX_CLK_DIV : constant is 1;
-end uart_rx;

hardware/ModelSim/work/uart_tx_line/_primary.vhd

@@ -1,16 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity uart_tx_line is
-    generic(
-        UART_TX_CLK_DIV : integer := 434
-    );
-    port(
-        clk             : in     vl_logic;
-        o_tx            : out    vl_logic;
-        i_start         : in     vl_logic;
-        o_fin           : out    vl_logic;
-        i_data          : in     vl_logic_vector(7 downto 0)
-    );
-    attribute mti_svvh_generic_type : integer;
-    attribute mti_svvh_generic_type of UART_TX_CLK_DIV : constant is 1;
-end uart_tx_line;

hardware/ModelSim/work/user_uart_tx/_primary.vhd

@@ -1,14 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity user_uart_tx is
-    generic(
-        UART_TX_CLK_DIV : integer := 434
-    );
-    port(
-        clk             : in     vl_logic;
-        rst_n           : in     vl_logic;
-        o_uart_tx       : out    vl_logic
-    );
-    attribute mti_svvh_generic_type : integer;
-    attribute mti_svvh_generic_type of UART_TX_CLK_DIV : constant is 1;
-end user_uart_tx;

hardware/ModelSim/work/vga/_primary.vhd

@@ -1,14 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity vga is
-    port(
-        clk             : in     vl_logic;
-        hsync           : out    vl_logic;
-        vsync           : out    vl_logic;
-        pixel           : out    vl_logic_vector(15 downto 0);
-        req             : out    vl_logic;
-        x               : out    vl_logic_vector(9 downto 0);
-        y               : out    vl_logic_vector(9 downto 0);
-        req_pixel       : in     vl_logic_vector(15 downto 0)
-    );
-end vga;

hardware/ModelSim/work/vga@char98x36/_primary.vhd

@@ -1,13 +0,0 @@
-library verilog;
-use verilog.vl_types.all;
-entity vgaChar98x36 is
-    port(
-        clk             : in     vl_logic;
-        rst_n           : in     vl_logic;
-        hsync           : out    vl_logic;
-        vsync           : out    vl_logic;
-        pixel           : out    vl_logic_vector(15 downto 0);
-        addr            : out    vl_logic_vector(11 downto 0);
-        ascii           : in     vl_logic_vector(7 downto 0)
-    );
-end vgaChar98x36;