FPGA/USTC-RVSoC
1
0
Fork 0
mirror of https://github.com/WangXuan95/USTC-RVSoC.git synced 2024-12-24 22:58:56 +08:00
Code Issues Projects Releases Wiki Activity
66 Commits 1 Branch 0 Tags
Commit Graph

66 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
WangXuan95
3b027a9e58 add license 2023-09-14 21:00:15 +08:00
WangXuan95
d781b88ce1 update 2022-04-17 19:07:27 +08:00
WangXuan95
ceda0f04c3 update 2022-04-08 14:24:46 +08:00
WangXuan95
69f9d22ffa rm .gitignore 2022-04-07 17:17:41 +08:00
WangXuan95
7b3af4c460 update 2022-04-07 17:12:33 +08:00
WangXuan95
ce41504ca2 update readme 2022-04-01 00:35:49 +08:00
X.Wang
d6bd312793
Update README.md 2022-03-05 14:55:33 +08:00
X.Wang
7e476f5948
Update README.md 2022-03-05 14:50:36 +08:00
X.Wang
0de5ca4e7a
Delete LICENSE 2021-10-27 14:44:22 +08:00
WangXuan95
fd2130f23d add Arty7 Board 2019-09-01 21:51:23 +08:00
WangXuan95
b345b615e2 Merge branch 'master' of https://github.com/WangXuan95/USTCRVSoC 2019-08-25 19:08:52 +08:00
WangXuan95
024bb0fd33 update README 2019-08-03 23:13:56 +08:00
王轩
a4c4d4f804
Update README.md 2019-07-09 15:30:30 +08:00
王轩
e20c1f6442
Update README.md 2019-07-09 15:28:57 +08:00
王轩
b907a107ac
Update README.md 2019-07-09 15:16:16 +08:00
王轩
577c1620de
Create LICENSE 2019-06-08 13:39:50 +08:00
王轩
78c1b78bd6
Merge pull request #1 from kdurant/master 
chore: 添加modelsim和quartus工程的gitignore
 2019-04-22 22:31:06 +08:00
kdurant_h
17e71956c6 chore: questa10.6c仿真环境 2019-04-22 22:11:21 +08:00
kdurant_h
cac1b99f6e chore: 添加modelsim和quartus工程的gitignore 2019-04-22 22:02:50 +08:00
WangXuan95
df43dd1898 完善README 2019-03-21 10:25:47 +08:00
WangXuan95
8fa76aa015 完善README 2019-03-21 10:05:29 +08:00
WangXuan95
60d9f5d53d 删除多余目录 2019-03-21 02:17:45 +08:00
WangXuan95
5c9244f6b3 重构图片 2019-03-21 01:46:26 +08:00
WangXuan95
c85a8428bf 完善README 2019-03-21 01:43:09 +08:00
WangXuan95
d4859ffd77 完善README 2019-03-21 01:41:55 +08:00
WangXuan95
6c395afde1 完善README 2019-03-21 01:33:47 +08:00
WangXuan95
b48d610c63 完善README 2019-03-21 01:28:31 +08:00
WangXuan95
56f1f735da 完善README 2019-03-21 00:14:36 +08:00
WangXuan95
62ae41de46 完善README 2019-03-21 00:12:09 +08:00
WangXuan95
4ee38db502 简化流水线 2019-03-13 02:49:52 +08:00
WangXuan95
51c599dc7c 简化指令总线接口 2019-03-10 22:42:33 +08:00
WangXuan95
52b5e214bc 简化指令总线接口 2019-03-10 22:41:16 +08:00
WangXuan95
87e580c4af 修正forward与branch同时发生时的bug 2019-03-08 02:34:24 +08:00
WangXuan95
192393aab3 添加一些汇编测试样例 2019-03-06 18:39:59 +08:00
WangXuan95
9dc7bb0145 优化regfile资源占用 2019-03-04 13:19:13 +08:00
WangXuan95
c5d3b371e2 delete .suo 2019-03-04 13:17:09 +08:00
WangXuan95
97fc852568 优化regfile资源占用 2019-03-03 16:02:00 +08:00
WangXuan95
fda5b623ec 优化regfile资源占用 2019-03-03 16:01:25 +08:00
WangXuan95
fee391c8f5 优化regfile资源占用 2019-03-03 16:00:37 +08:00
WangXuan95
72108ce6b6 优化regfile资源占用 2019-03-03 15:58:27 +08:00
WangXuan95
337027642b 优化Core和VGA的资源消耗 2019-03-03 02:44:10 +08:00
WangXuan95
e36557d90f 优化Core和VGA的资源消耗 2019-03-03 02:42:38 +08:00
WangXuan95
6ac644f407 修正readme 2019-02-28 13:47:08 +08:00
WangXuan95
d575a41c58 remove test 2019-02-26 20:01:54 +08:00
WangXuan95
dfb750b8d5 合并ISP-UART和USER-UART，添加Nexys4开发板工程 2019-02-26 19:50:47 +08:00
WangXuan95
0840f54aa6 合并ISP-UART和USER-UART，添加Nexys4开发板工程 2019-02-26 19:45:11 +08:00
WangXuan95
b5c93cb6ce 合并ISP-UART和USER-UART，添加Nexys4开发板工程 2019-02-26 19:36:30 +08:00
WangXuan95
61656055c5 add USTCRVSoC-tool source files 2019-02-16 15:12:48 +08:00
WangXuan95
3c5624a703 add USTCRVSoC-tool source files 2019-02-16 15:12:18 +08:00
WangXuan95
ccb6d06344 add USTCRVSoC-tool source files 2019-02-16 15:10:01 +08:00