FPGA/USTC-RVSoC
1
0
Fork 0
mirror of https://github.com/WangXuan95/USTC-RVSoC.git synced 2024-12-24 22:58:56 +08:00
Code Issues Projects Releases Wiki Activity
66 Commits 1 Branch 0 Tags
Commit Graph

11 Commits

Author SHA1 Message Date
WangXuan95
ceda0f04c3 update 2022-04-08 14:24:46 +08:00
WangXuan95
7b3af4c460 update 2022-04-07 17:12:33 +08:00
WangXuan95
dfb750b8d5 合并ISP-UART和USER-UART，添加Nexys4开发板工程 2019-02-26 19:50:47 +08:00
WangXuan95
f341b05171 add USTCRVSoC source code 2019-02-16 15:05:52 +08:00
WangXuan95
03c5b6e19a add USTCRVSoC-tool 2019-02-11 16:56:18 +08:00
WangXuan95
60629d6755 add instr ram 2019-02-08 00:38:18 +08:00
WangXuan95
1bde11bf98 modify readme 2019-02-07 19:36:33 +08:00
WangXuan95
f7afec8097 优化VGA电路面积、并向ISP-UART中加入设置boot-addr的功能 2019-02-07 15:30:28 +08:00
WangXuan95
e48645e52a add readme 2019-02-05 21:24:26 +08:00
WangXuan95
95111fe668 add readme 2019-02-05 17:00:24 +08:00
WangXuan95
d12408b6d7 first commit 2019-02-05 16:19:46 +08:00