FPGA/USTC-RVSoC
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6 Commits

Author SHA1 Message Date
WangXuan95
ceda0f04c3 update 2022-04-08 14:24:46 +08:00
WangXuan95
7b3af4c460 update 2022-04-07 17:12:33 +08:00
WangXuan95
dfb750b8d5 合并ISP-UART和USER-UART，添加Nexys4开发板工程 2019-02-26 19:50:47 +08:00
WangXuan95
1bde11bf98 modify readme 2019-02-07 19:36:33 +08:00
WangXuan95
f7afec8097 优化VGA电路面积、并向ISP-UART中加入设置boot-addr的功能 2019-02-07 15:30:28 +08:00
WangXuan95
d12408b6d7 first commit 2019-02-05 16:19:46 +08:00