FPGA/USTC-RVSoC
1
0
Fork 0
mirror of https://github.com/WangXuan95/USTC-RVSoC.git synced 2025-01-30 23:02:55 +08:00
Code Issues Projects Releases Wiki Activity
45 Commits 1 Branch 0 Tags
Commit Graph

5 Commits

Author SHA1 Message Date
WangXuan95
62ae41de46 完善README 2019-03-21 00:12:09 +08:00
WangXuan95
4ee38db502 简化流水线 2019-03-13 02:49:52 +08:00
WangXuan95
52b5e214bc 简化指令总线接口 2019-03-10 22:41:16 +08:00
WangXuan95
72108ce6b6 优化regfile资源占用 2019-03-03 15:58:27 +08:00
WangXuan95
b5c93cb6ce 合并ISP-UART和USER-UART，添加Nexys4开发板工程 2019-02-26 19:36:30 +08:00