FPGA/USTC-RVSoC
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7 Commits

Author SHA1 Message Date
WangXuan95
b48d610c63 完善README 2019-03-21 01:28:31 +08:00
WangXuan95
62ae41de46 完善README 2019-03-21 00:12:09 +08:00
WangXuan95
b5c93cb6ce 合并ISP-UART和USER-UART，添加Nexys4开发板工程 2019-02-26 19:36:30 +08:00
WangXuan95
7ca3838f7c new readme 2019-02-11 21:50:31 +08:00
WangXuan95
5d06a5f041 new readme 2019-02-11 21:40:34 +08:00
WangXuan95
03c5b6e19a add USTCRVSoC-tool 2019-02-11 16:56:18 +08:00
WangXuan95
60629d6755 add instr ram 2019-02-08 00:38:18 +08:00