FPGA/USTC-RVSoC
1
0
Fork 0
mirror of https://github.com/WangXuan95/USTC-RVSoC.git synced 2025-01-30 23:02:55 +08:00
Code Issues Projects Releases Wiki Activity
20 Commits 1 Branch 0 Tags
Commit Graph

2 Commits

Author SHA1 Message Date
WangXuan95
b5c93cb6ce 合并ISP-UART和USER-UART，添加Nexys4开发板工程 2019-02-26 19:36:30 +08:00
WangXuan95
60629d6755 add instr ram 2019-02-08 00:38:18 +08:00