FPGA/USTC-RVSoC
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2 Commits

Author SHA1 Message Date
WangXuan95
72108ce6b6 优化regfile资源占用 2019-03-03 15:58:27 +08:00
WangXuan95
b5c93cb6ce 合并ISP-UART和USER-UART，添加Nexys4开发板工程 2019-02-26 19:36:30 +08:00