FPGA/USTC-RVSoC
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5 Commits

Author SHA1 Message Date
WangXuan95
e36557d90f 优化Core和VGA的资源消耗 2019-03-03 02:42:38 +08:00
WangXuan95
6ac644f407 修正readme 2019-02-28 13:47:08 +08:00
WangXuan95
d575a41c58 remove test 2019-02-26 20:01:54 +08:00
WangXuan95
0840f54aa6 合并ISP-UART和USER-UART，添加Nexys4开发板工程 2019-02-26 19:45:11 +08:00
WangXuan95
b5c93cb6ce 合并ISP-UART和USER-UART，添加Nexys4开发板工程 2019-02-26 19:36:30 +08:00