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  • ba33e9136b
         Merge 49eb022d52577c840e883cbc5b23e21e398e3cfe into 3b027a9e5876cba234182a3885181514208c2a26 Wu 2023-09-22 21:14:06 -07:00
  • 9de9477f87
         Merge 464f955305d36945563f958384a40a9452c060c9 into 3b027a9e5876cba234182a3885181514208c2a26 Jonathan_Wen 2023-09-22 21:14:05 -07:00
  • 3b027a9e58 add license master WangXuan95 2023-09-14 21:00:15 +08:00
  • 49eb022d52 BSP板级支持包 xiaowuzxc 2022-11-26 20:39:07 +08:00
  • d781b88ce1 update WangXuan95 2022-04-17 19:07:27 +08:00
  • ceda0f04c3 update WangXuan95 2022-04-08 14:24:46 +08:00
  • 69f9d22ffa rm .gitignore WangXuan95 2022-04-07 17:17:41 +08:00
  • 7b3af4c460 update WangXuan95 2022-04-07 17:12:33 +08:00
  • ce41504ca2 update readme WangXuan95 2022-04-01 00:35:49 +08:00
  • d6bd312793
         Update README.md X.Wang 2022-03-05 14:55:33 +08:00
  • 7e476f5948
         Update README.md X.Wang 2022-03-05 14:50:36 +08:00
  • 0de5ca4e7a
         Delete LICENSE X.Wang 2021-10-27 14:44:22 +08:00
  • 464f955305
         对依元素ARTIX7开发板进行支持 rabbit-timmy 2019-12-09 10:55:31 +08:00
  • fd2130f23d add Arty7 Board WangXuan95 2019-09-01 21:51:23 +08:00
  • b345b615e2 Merge branch 'master' of https://github.com/WangXuan95/USTCRVSoC WangXuan95 2019-08-25 19:08:52 +08:00
  • 024bb0fd33 update README WangXuan95 2019-08-03 23:13:56 +08:00
  • a4c4d4f804
         Update README.md 王轩 2019-07-09 15:30:30 +08:00
  • e20c1f6442
         Update README.md 王轩 2019-07-09 15:28:57 +08:00
  • b907a107ac
         Update README.md 王轩 2019-07-09 15:16:16 +08:00
  • 577c1620de
         Create LICENSE 王轩 2019-06-08 13:39:50 +08:00
  • 78c1b78bd6
         Merge pull request #1 from kdurant/master 王轩 2019-04-22 22:31:06 +08:00
  • 17e71956c6 chore: questa10.6c仿真环境 kdurant_h 2019-04-22 22:11:21 +08:00
  • cac1b99f6e chore: 添加modelsim和quartus工程的gitignore kdurant_h 2019-04-22 22:02:50 +08:00
  • df43dd1898 完善README WangXuan95 2019-03-21 10:25:47 +08:00
  • 8fa76aa015 完善README WangXuan95 2019-03-21 10:05:29 +08:00
  • 60d9f5d53d 删除多余目录 WangXuan95 2019-03-21 02:17:45 +08:00
  • 5c9244f6b3 重构图片 WangXuan95 2019-03-21 01:46:26 +08:00
  • c85a8428bf 完善README WangXuan95 2019-03-21 01:43:09 +08:00
  • d4859ffd77 完善README WangXuan95 2019-03-21 01:41:55 +08:00
  • 6c395afde1 完善README WangXuan95 2019-03-21 01:33:47 +08:00
  • b48d610c63 完善README WangXuan95 2019-03-21 01:28:31 +08:00
  • 56f1f735da 完善README WangXuan95 2019-03-21 00:14:36 +08:00
  • 62ae41de46 完善README WangXuan95 2019-03-21 00:12:09 +08:00
  • 4ee38db502 简化流水线 WangXuan95 2019-03-13 02:49:52 +08:00
  • 51c599dc7c 简化指令总线接口 WangXuan95 2019-03-10 22:42:33 +08:00
  • 52b5e214bc 简化指令总线接口 WangXuan95 2019-03-10 22:41:16 +08:00
  • 87e580c4af 修正forward与branch同时发生时的bug WangXuan95 2019-03-08 02:34:24 +08:00
  • 192393aab3 添加一些汇编测试样例 WangXuan95 2019-03-06 18:39:59 +08:00
  • 9dc7bb0145 优化regfile资源占用 WangXuan95 2019-03-04 13:19:13 +08:00
  • c5d3b371e2 delete .suo WangXuan95 2019-03-04 13:17:09 +08:00
  • 97fc852568 优化regfile资源占用 WangXuan95 2019-03-03 16:02:00 +08:00
  • fda5b623ec 优化regfile资源占用 WangXuan95 2019-03-03 16:01:25 +08:00
  • fee391c8f5 优化regfile资源占用 WangXuan95 2019-03-03 16:00:37 +08:00
  • 72108ce6b6 优化regfile资源占用 WangXuan95 2019-03-03 15:58:27 +08:00
  • 337027642b 优化Core和VGA的资源消耗 WangXuan95 2019-03-03 02:44:10 +08:00
  • e36557d90f 优化Core和VGA的资源消耗 WangXuan95 2019-03-03 02:42:38 +08:00
  • 6ac644f407 修正readme WangXuan95 2019-02-28 13:47:08 +08:00
  • d575a41c58 remove test WangXuan95 2019-02-26 20:01:54 +08:00
  • dfb750b8d5 合并ISP-UART和USER-UART，添加Nexys4开发板工程 WangXuan95 2019-02-26 19:50:47 +08:00
  • 0840f54aa6 合并ISP-UART和USER-UART，添加Nexys4开发板工程 WangXuan95 2019-02-26 19:45:11 +08:00
  • b5c93cb6ce 合并ISP-UART和USER-UART，添加Nexys4开发板工程 WangXuan95 2019-02-26 19:36:30 +08:00
  • 61656055c5 add USTCRVSoC-tool source files WangXuan95 2019-02-16 15:12:48 +08:00
  • 3c5624a703 add USTCRVSoC-tool source files WangXuan95 2019-02-16 15:12:18 +08:00
  • ccb6d06344 add USTCRVSoC-tool source files WangXuan95 2019-02-16 15:10:01 +08:00
  • f341b05171 add USTCRVSoC source code WangXuan95 2019-02-16 15:02:27 +08:00
  • 7ca3838f7c new readme WangXuan95 2019-02-11 21:50:31 +08:00
  • 5d06a5f041 new readme WangXuan95 2019-02-11 21:40:34 +08:00
  • 1265d3feb1 new WangXuan95 2019-02-11 17:31:09 +08:00
  • 1052db682c add USTCRVSoC tool WangXuan95 2019-02-11 17:23:53 +08:00
  • 4abb2fe48a add USTCRVSoC-tool WangXuan95 2019-02-11 17:01:30 +08:00
  • 03c5b6e19a add USTCRVSoC-tool WangXuan95 2019-02-11 16:56:18 +08:00
  • 60629d6755 add instr ram WangXuan95 2019-02-08 00:38:18 +08:00
  • 1bde11bf98 modify readme WangXuan95 2019-02-07 19:36:33 +08:00
  • f7afec8097 优化VGA电路面积、并向ISP-UART中加入设置boot-addr的功能 WangXuan95 2019-02-07 15:30:28 +08:00
  • e48645e52a add readme WangXuan95 2019-02-05 21:24:26 +08:00
  • ecd130b427 add readme WangXuan95 2019-02-05 21:22:07 +08:00
  • eb9ba55969 add readme WangXuan95 2019-02-05 21:20:39 +08:00
  • 23a684c5fc add readme WangXuan95 2019-02-05 21:19:18 +08:00
  • 95111fe668 add readme WangXuan95 2019-02-05 17:00:24 +08:00
  • d12408b6d7 first commit WangXuan95 2019-02-05 16:19:46 +08:00