module Nexys4_USTCRVSoC_top(
    input  logic       CLK100MHZ,
    output logic [2:0] LED,
    output logic       UART_TX,
    input  logic       UART_RX,
    output logic       VGA_HS, VGA_VS,
    output logic [3:0] VGA_R, VGA_G, VGA_B
);

logic  clk; // 50MHz, SoC driving clock, generated by MMCM


// Show UART on LED2, LED1
assign LED[2:1] = ~{UART_RX, UART_TX};


// VGA assignment
logic vga_red, vga_green, vga_blue;
assign VGA_R = {4{vga_red}};
assign VGA_G = {4{vga_green}};
assign VGA_B = {4{vga_blue}};


//------------------------------------------------------------------------------------------------------
// SoC
//------------------------------------------------------------------------------------------------------
soc_top #(
    .UART_RX_CLK_DIV  ( 108       ),   // 50MHz/4/115200 = 108
    .UART_TX_CLK_DIV  ( 434       ),   // 50MHz/1/115200 = 434
    .VGA_CLK_DIV      ( 1         )
) soc_i (
    .clk              ( clk       ),
    .isp_uart_rx      ( UART_RX   ),
    .isp_uart_tx      ( UART_TX   ),
    .vga_hsync        ( VGA_HS    ),
    .vga_vsync        ( VGA_VS    ),
    .vga_red          ( vga_red   ),
    .vga_green        ( vga_green ),
    .vga_blue         ( vga_blue  )
);


//------------------------------------------------------------------------------------------------------
// MMCM primitive, generate SoC driving clock, equivalent to clock wizard IP
//------------------------------------------------------------------------------------------------------
wire clkin_buf, clkfb, clkfb_buf, clkout_unbuf;

BUFG bufg_clkin  ( .O(clkin_buf), .I(CLK100MHZ) );
BUFG bufg_clkfb  ( .O(clkfb_buf), .I(clkfb) );
BUFG bufg_clkout ( .O(clk), .I(clkout_unbuf) );

MMCME2_ADV #(
    .BANDWIDTH           ( "HIGH"       ),
    .CLKOUT4_CASCADE     ( "FALSE"      ),
    .COMPENSATION        ( "ZHOLD"      ),
    .STARTUP_WAIT        ( "FALSE"      ),
    .DIVCLK_DIVIDE       ( 1            ),
    .CLKFBOUT_MULT_F     ( 8.000        ),  // f(clkfb) = f(clkin) * 8
    .CLKFBOUT_PHASE      ( 0.000        ),
    .CLKFBOUT_USE_FINE_PS( "FALSE"      ),
    .CLKOUT0_DIVIDE_F    ( 16.000       ),  // f(clkout) = f(clkfb) / 16
    .CLKOUT0_PHASE       ( 0.000        ),
    .CLKOUT0_DUTY_CYCLE  ( 0.500        ),
    .CLKOUT0_USE_FINE_PS ( "FALSE"      ),
    .CLKIN1_PERIOD       ( 10.000       )   // T=10ns, f=100MHz
) mmcm_adv_i (
    .CLKFBOUT            ( clkfb        ),
    .CLKFBOUTB           (              ),
    .CLKOUT0             ( clkout_unbuf ),
    .CLKOUT0B(), .CLKOUT1(), .CLKOUT1B(), .CLKOUT2(), .CLKOUT2B(), .CLKOUT3(), .CLKOUT3B(), .CLKOUT4(), .CLKOUT5(), .CLKOUT6(),
    .CLKFBIN             ( clkfb_buf    ),
    .CLKIN1              ( clkin_buf    ),
    .CLKIN2              ( 1'b0         ),
    .CLKINSEL            ( 1'b1         ),
    .DADDR               ( 7'h0         ),
    .DCLK                ( 1'b0         ),
    .DEN                 ( 1'b0         ),
    .DI                  ( 16'h0        ),
    .DO                  (              ),
    .DRDY                (              ),
    .DWE                 ( 1'b0         ),
    .PSCLK               ( 1'b0         ),
    .PSEN                ( 1'b0         ),
    .PSINCDEC            ( 1'b0         ),
    .PSDONE              (              ),
    .LOCKED              ( LED[0]       ),
    .CLKINSTOPPED        (              ),
    .CLKFBSTOPPED        (              ),
    .PWRDWN              ( 1'b0         ),
    .RST                 ( 1'b0         )
);


endmodule