mirror of
https://github.com/WangXuan95/USTC-RVSoC.git
synced 2024-12-24 22:58:56 +08:00
96 lines
3.5 KiB
Systemverilog
96 lines
3.5 KiB
Systemverilog
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module Nexys4_USTCRVSoC_top(
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input logic CLK100MHZ,
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output logic [2:0] LED,
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output logic UART_TX,
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input logic UART_RX,
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output logic VGA_HS, VGA_VS,
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output logic [3:0] VGA_R, VGA_G, VGA_B
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);
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logic clk; // 50MHz, SoC driving clock, generated by MMCM
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// Show UART on LED2, LED1
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assign LED[2:1] = ~{UART_RX, UART_TX};
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// VGA assignment
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logic vga_red, vga_green, vga_blue;
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assign VGA_R = {4{vga_red}};
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assign VGA_G = {4{vga_green}};
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assign VGA_B = {4{vga_blue}};
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//------------------------------------------------------------------------------------------------------
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// SoC
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//------------------------------------------------------------------------------------------------------
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soc_top #(
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.UART_RX_CLK_DIV ( 108 ), // 50MHz/4/115200 = 108
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.UART_TX_CLK_DIV ( 434 ), // 50MHz/1/115200 = 434
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.VGA_CLK_DIV ( 1 )
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) soc_i (
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.clk ( clk ),
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.isp_uart_rx ( UART_RX ),
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.isp_uart_tx ( UART_TX ),
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.vga_hsync ( VGA_HS ),
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.vga_vsync ( VGA_VS ),
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.vga_red ( vga_red ),
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.vga_green ( vga_green ),
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.vga_blue ( vga_blue )
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);
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//------------------------------------------------------------------------------------------------------
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// MMCM primitive, generate SoC driving clock, equivalent to clock wizard IP
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//------------------------------------------------------------------------------------------------------
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wire clkin_buf, clkfb, clkfb_buf, clkout_unbuf;
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BUFG bufg_clkin ( .O(clkin_buf), .I(CLK100MHZ) );
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BUFG bufg_clkfb ( .O(clkfb_buf), .I(clkfb) );
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BUFG bufg_clkout ( .O(clk), .I(clkout_unbuf) );
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MMCME2_ADV #(
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.BANDWIDTH ( "HIGH" ),
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.CLKOUT4_CASCADE ( "FALSE" ),
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.COMPENSATION ( "ZHOLD" ),
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.STARTUP_WAIT ( "FALSE" ),
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.DIVCLK_DIVIDE ( 1 ),
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.CLKFBOUT_MULT_F ( 8.000 ), // f(clkfb) = f(clkin) * 8
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.CLKFBOUT_PHASE ( 0.000 ),
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.CLKFBOUT_USE_FINE_PS( "FALSE" ),
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.CLKOUT0_DIVIDE_F ( 16.000 ), // f(clkout) = f(clkfb) / 16
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.CLKOUT0_PHASE ( 0.000 ),
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.CLKOUT0_DUTY_CYCLE ( 0.500 ),
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.CLKOUT0_USE_FINE_PS ( "FALSE" ),
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.CLKIN1_PERIOD ( 10.000 ) // T=10ns, f=100MHz
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) mmcm_adv_i (
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.CLKFBOUT ( clkfb ),
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.CLKFBOUTB ( ),
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.CLKOUT0 ( clkout_unbuf ),
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.CLKOUT0B(), .CLKOUT1(), .CLKOUT1B(), .CLKOUT2(), .CLKOUT2B(), .CLKOUT3(), .CLKOUT3B(), .CLKOUT4(), .CLKOUT5(), .CLKOUT6(),
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.CLKFBIN ( clkfb_buf ),
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.CLKIN1 ( clkin_buf ),
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.CLKIN2 ( 1'b0 ),
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.CLKINSEL ( 1'b1 ),
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.DADDR ( 7'h0 ),
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.DCLK ( 1'b0 ),
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.DEN ( 1'b0 ),
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.DI ( 16'h0 ),
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.DO ( ),
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.DRDY ( ),
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.DWE ( 1'b0 ),
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.PSCLK ( 1'b0 ),
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.PSEN ( 1'b0 ),
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.PSINCDEC ( 1'b0 ),
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.PSDONE ( ),
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.LOCKED ( LED[0] ),
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.CLKINSTOPPED ( ),
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.CLKFBSTOPPED ( ),
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.PWRDWN ( 1'b0 ),
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.RST ( 1'b0 )
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);
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endmodule
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