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42 lines
1.1 KiB
Systemverilog
42 lines
1.1 KiB
Systemverilog
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module instr_rom(
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input logic clk,
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naive_bus.slave bus
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);
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localparam INSTR_CNT = 30'd18;
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wire [31:0] instr_rom_cell [INSTR_CNT] = '{
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32'h000062b3, // 0x00000000
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32'h000302b7, // 0x00000004
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32'h06806313, // 0x00000008
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32'h00628023, // 0x0000000c
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32'h06506313, // 0x00000010
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32'h00628023, // 0x00000014
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32'h06c06313, // 0x00000018
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32'h00628023, // 0x0000001c
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32'h06c06313, // 0x00000020
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32'h00628023, // 0x00000024
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32'h06f06313, // 0x00000028
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32'h00628023, // 0x0000002c
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32'h00a06313, // 0x00000030
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32'h00628023, // 0x00000034
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32'h00c003b7, // 0x00000038
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32'hfff38393, // 0x0000003c
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32'hfe039ee3, // 0x00000040
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32'hfc5ff06f // 0x00000044
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};
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logic [29:0] cell_rd_addr;
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assign bus.rd_gnt = bus.rd_req;
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assign bus.wr_gnt = bus.wr_req;
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assign cell_rd_addr = bus.rd_addr[31:2];
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always @ (posedge clk)
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if(bus.rd_req)
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bus.rd_data <= (cell_rd_addr>=INSTR_CNT) ? 0 : instr_rom_cell[cell_rd_addr];
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endmodule
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