mirror of
https://github.com/WangXuan95/USTC-RVSoC.git
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86 lines
2.6 KiB
Systemverilog
86 lines
2.6 KiB
Systemverilog
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module video_ram #(
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parameter VGA_CLK_DIV = 1
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)(
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input logic clk, rstn,
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output logic o_hsync, o_vsync,
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output logic o_red, o_green, o_blue,
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naive_bus.slave bus
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);
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logic vga_req;
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logic [ 9:0] vga_addr_h;
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logic [ 1:0] vga_addr_l, vga_addr_l_latch = 2'b00;
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logic [ 7:0] vga_ascii;
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logic [ 9:0] cell_wr_addr, cell_rd_addr;
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logic [ 7:0] vga_rdata [4];
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assign bus.rd_gnt = (~vga_req) & bus.rd_req;
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assign bus.wr_gnt = bus.wr_req;
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assign bus.rd_data = {vga_rdata[3],vga_rdata[2],vga_rdata[1],vga_rdata[0]};
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assign cell_wr_addr = bus.wr_addr[11:2];
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assign cell_rd_addr = vga_req ? vga_addr_h : bus.rd_addr[11:2];
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always @ (posedge clk or negedge rstn)
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if(~rstn)
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vga_addr_l_latch <= 2'b00;
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else
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vga_addr_l_latch <= vga_addr_l;
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ram ram_i0(
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.clk ( clk ),
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.i_we ( bus.wr_req & bus.wr_be[0] ),
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.i_waddr ( cell_wr_addr ),
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.i_wdata ( bus.wr_data[ 7: 0] ),
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.i_raddr ( cell_rd_addr ),
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.o_rdata ( vga_rdata[0] )
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);
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ram ram_i1(
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.clk ( clk ),
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.i_we ( bus.wr_req & bus.wr_be[1] ),
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.i_waddr ( cell_wr_addr ),
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.i_wdata ( bus.wr_data[15: 8] ),
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.i_raddr ( cell_rd_addr ),
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.o_rdata ( vga_rdata[1] )
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);
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ram ram_i2(
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.clk ( clk ),
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.i_we ( bus.wr_req & bus.wr_be[2] ),
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.i_waddr ( cell_wr_addr ),
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.i_wdata ( bus.wr_data[23:16] ),
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.i_raddr ( cell_rd_addr ),
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.o_rdata ( vga_rdata[2] )
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);
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ram ram_i3(
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.clk ( clk ),
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.i_we ( bus.wr_req & bus.wr_be[3] ),
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.i_waddr ( cell_wr_addr ),
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.i_wdata ( bus.wr_data[31:24] ),
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.i_raddr ( cell_rd_addr ),
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.o_rdata ( vga_rdata[3] )
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);
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always_comb
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case(vga_addr_l_latch)
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2'b00 : vga_ascii <= vga_rdata[0];
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2'b01 : vga_ascii <= vga_rdata[1];
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2'b10 : vga_ascii <= vga_rdata[2];
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2'b11 : vga_ascii <= vga_rdata[3];
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endcase
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vga_char_86x32 #(
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.VGA_CLK_DIV ( VGA_CLK_DIV )
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) vga_char_86x32_i (
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.clk ( clk ),
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.hsync ( o_hsync ),
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.vsync ( o_vsync ),
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.red ( o_red ),
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.green ( o_green ),
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.blue ( o_blue ),
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.req ( vga_req ),
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.addr ( {vga_addr_h,vga_addr_l} ),
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.ascii ( vga_ascii )
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);
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endmodule
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