mirror of
https://github.com/WangXuan95/USTC-RVSoC.git
synced 2024-12-24 22:58:56 +08:00
70 lines
2.5 KiB
Systemverilog
70 lines
2.5 KiB
Systemverilog
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`timescale 1ps/1ps
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module tb_cpu #(
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// Specify the instruction&data stream file to be run here
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// notice: this is the file path in my PC, please modify it to the path in your PC
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parameter INSTRUCTION_STREAM_FILE = "E:/FPGAcommon/USTC-RVSoC/SIM-CPU/rv32i_test/a_instr_stream.txt" // I provide three test instruction streams here, which are split from the official test of RISC-V RV32I
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// b_instr_stream.txt"
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// c_instr_stream.txt"
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)();
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logic clk = 1'b1;
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logic rstn = 1'b0;
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always #10000 clk = ~clk; // 50MHz clock
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initial begin repeat(4) @(posedge clk); rstn <= 1'b1; end
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naive_bus bus_masters[2]();
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naive_bus bus_slaves [1]();
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// RV32I Core
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core_top core_top_i (
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.clk ( clk ),
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.rstn ( rstn ),
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.i_boot_addr ( 0 ),
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.instr_master ( bus_masters[1] ),
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.data_master ( bus_masters[0] )
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);
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naive_bus_router #(
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.N_MASTER ( 2 ),
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.N_SLAVE ( 1 ),
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.SLAVES_MASK ( { 32'h0000_ffff } ),
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.SLAVES_BASE ( { 32'h0000_0000 } )
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) soc_bus_router_i (
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.clk ( clk ),
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.rstn ( rstn ),
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.masters ( bus_masters ),
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.slaves ( bus_slaves )
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);
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assign bus_slaves[0].rd_gnt = 1'b1;
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assign bus_slaves[0].wr_gnt = 1'b1;
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//----------------------------------------------------------------------------------------------------------
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// this ram stores both instruction and data
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//----------------------------------------------------------------------------------------------------------
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logic [31:0] ram [4096];
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initial $readmemh(INSTRUCTION_STREAM_FILE, ram);
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always @ (posedge clk or negedge rstn)
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if(~rstn)
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bus_slaves[0].rd_data <= 0;
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else
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bus_slaves[0].rd_data <= ram[bus_slaves[0].rd_addr[14:2]];
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always @ (posedge clk) begin
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if(bus_slaves[0].wr_be[0])
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ram[bus_slaves[0].wr_addr[14:2]][ 7: 0] <= bus_slaves[0].wr_data[ 7: 0];
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if(bus_slaves[0].wr_be[1])
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ram[bus_slaves[0].wr_addr[14:2]][15: 8] <= bus_slaves[0].wr_data[15: 8];
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if(bus_slaves[0].wr_be[2])
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ram[bus_slaves[0].wr_addr[14:2]][23:16] <= bus_slaves[0].wr_data[23:16];
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if(bus_slaves[0].wr_be[3])
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ram[bus_slaves[0].wr_addr[14:2]][31:24] <= bus_slaves[0].wr_data[31:24];
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end
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endmodule
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