mirror of
https://github.com/WangXuan95/USTC-RVSoC.git
synced 2025-01-30 23:02:55 +08:00
47 lines
1.4 KiB
Systemverilog
47 lines
1.4 KiB
Systemverilog
module DE0_Nano_USTCRVSoC_top(
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//////////// CLOCK //////////
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input CLOCK_50,
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//////////// LED, KEY, Switch //////////
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output [7:0] LED,
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input [1:0] KEY,
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input [3:0] SW,
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//////////// GPIO Header 1 //////////
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input [1:0] GPIO_0_IN,
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inout [33:0] GPIO_0,
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input [1:0] GPIO_1_IN,
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inout [33:0] GPIO_1,
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//////////// ADC //////////
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output ADC_CS_N, ADC_SADDR, ADC_SCLK,
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input ADC_SDAT,
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//////////// Accelerometer and EEPROM //////////
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output G_SENSOR_CS_N,
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input G_SENSOR_INT,
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output I2C_SCLK,
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inout I2C_SDAT,
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//////////// SDRAM //////////
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output [12:0] DRAM_ADDR,
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output [1:0] DRAM_BA,
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output DRAM_CAS_N, DRAM_CKE, DRAM_CLK, DRAM_CS_N, DRAM_RAS_N, DRAM_WE_N,
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inout [15:0] DRAM_DQ,
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output [1:0] DRAM_DQM
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);
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soc_top soc_inst(
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.clk ( CLOCK_50 ),
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.isp_uart_rx ( GPIO_1_IN[0] ),
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.isp_uart_tx ( GPIO_1[0] ),
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.user_uart_rx ( GPIO_1_IN[1] ),
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.user_uart_tx ( GPIO_1[1] ),
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.vga_hsync ( GPIO_0[33] ),
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.vga_vsync ( GPIO_0[32] ),
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.vga_pixel ( GPIO_0[31:16] )
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);
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// 在开发板的LED上显示ISP-UART和USER-UART的发送灯和接收灯
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assign LED[7:4] = ~{GPIO_1_IN[0],GPIO_1[0],GPIO_1_IN[1],GPIO_1[1]};
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// VGA GND
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assign GPIO_0[12] = 1'b0;
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endmodule
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