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https://github.com/WangXuan95/USTC-RVSoC.git
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48 lines
1.3 KiB
Systemverilog
48 lines
1.3 KiB
Systemverilog
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module uart_tx_line #(
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parameter UART_TX_CLK_DIV = 434 // 50MHz/1/115200Hz=434
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)(
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input logic clk,
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output logic o_tx,
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input logic i_start,
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input logic [7:0][7:0] i_data
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);
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logic [31:0] cnt = 0;
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logic [ 6:0] tx_cnt = 0;
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logic [90:0] tx_buffer, tx_shift;
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initial tx_shift = 91'h0;
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initial o_tx = 1'b1;
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assign tx_buffer = {2'b11, 8'h0A , // 0x0A = \n , a end of line
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2'b01, i_data[0],
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2'b01, i_data[1],
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2'b01, i_data[2],
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2'b01, i_data[3],
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2'b01, i_data[4],
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2'b01, i_data[5],
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2'b01, i_data[6],
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2'b01, i_data[7],
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1'b0};
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always @ (posedge clk)
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cnt <= (cnt<UART_TX_CLK_DIV-1) ? cnt+1 : 0;
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always @ (posedge clk)
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if(tx_cnt>7'd0) begin
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if(cnt==0) begin
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{tx_shift, o_tx} <= {1'b1, tx_shift};
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tx_cnt <= tx_cnt - 7'd1;
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end
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end else begin
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o_tx <= 1'b1;
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if(i_start) begin
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tx_cnt <= 7'd93;
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tx_shift <= tx_buffer;
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end else begin
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tx_cnt <= 7'd0;
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end
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end
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endmodule
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