mirror of
https://github.com/WangXuan95/USTC-RVSoC.git
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102 lines
2.9 KiB
Systemverilog
102 lines
2.9 KiB
Systemverilog
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module core_regfile(
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input logic clk, rstn,
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input logic rd_latch,
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// Read port 1
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input logic i_re1,
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input logic [4:0] i_raddr1,
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output logic [31:0] o_rdata1,
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// Read port 2
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input logic i_re2,
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input logic [4:0] i_raddr2,
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output logic [31:0] o_rdata2,
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// forward port 1
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input logic i_forward1,
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input logic [4:0] i_faddr1,
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input logic [31:0] i_fdata1,
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// forward port 2
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input logic i_forward2,
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input logic [4:0] i_faddr2,
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input logic [31:0] i_fdata2,
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// Write port
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input logic i_we,
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input logic [4:0] i_waddr,
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input logic [31:0] i_wdata
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);
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logic [31:0] reg_rdata1 = 0;
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logic [31:0] reg_rdata2 = 0;
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logic [31:0] forward_data1, forward_data2;
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logic from_fw1, from_fw2;
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assign o_rdata1 = from_fw1 ? forward_data1 : reg_rdata1;
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assign o_rdata2 = from_fw2 ? forward_data2 : reg_rdata2;
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always @ (posedge clk or negedge rstn)
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if(~rstn) begin
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from_fw1 <= 1'b0;
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forward_data1 <= 0;
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end else begin
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if(rd_latch) begin
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from_fw1 <= 1'b1;
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forward_data1 <= o_rdata1;
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end else if((~i_re1) || i_raddr1==5'h0 ) begin
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from_fw1 <= 1'b1;
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forward_data1 <= 0;
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end else if(i_forward1 && i_faddr1==i_raddr1) begin
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from_fw1 <= 1'b1;
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forward_data1 <= i_fdata1;
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end else if(i_forward2 && i_faddr2==i_raddr1) begin
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from_fw1 <= 1'b1;
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forward_data1 <= i_fdata2;
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end else if(i_we && i_waddr ==i_raddr1) begin
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from_fw1 <= 1'b1;
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forward_data1 <= i_wdata;
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end else begin
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from_fw1 <= 1'b0;
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forward_data1 <= 0;
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end
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end
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always @ (posedge clk or negedge rstn)
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if(~rstn) begin
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from_fw2 <= 1'b0;
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forward_data2 <= 0;
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end else begin
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if(rd_latch) begin
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from_fw2 <= 1'b1;
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forward_data2 <= o_rdata2;
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end else if((~i_re2) || i_raddr2==5'h0 ) begin
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from_fw2 <= 1'b1;
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forward_data2 <= 0;
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end else if(i_forward1 && i_faddr1==i_raddr2) begin
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from_fw2 <= 1'b1;
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forward_data2 <= i_fdata1;
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end else if(i_forward2 && i_faddr2==i_raddr2) begin
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from_fw2 <= 1'b1;
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forward_data2 <= i_fdata2;
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end else if(i_we && i_waddr ==i_raddr2) begin
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from_fw2 <= 1'b1;
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forward_data2 <= i_wdata;
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end else begin
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from_fw2 <= 1'b0;
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forward_data2 <= 0;
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end
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end
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// 32bit * 32 regfile
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logic [31:0] regfile [32];
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always @ (posedge clk)
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reg_rdata1 <= regfile[i_raddr1];
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always @ (posedge clk)
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reg_rdata2 <= regfile[i_raddr2];
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always @ (posedge clk)
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if(i_we)
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regfile[i_waddr] <= i_wdata;
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endmodule
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