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https://github.com/WangXuan95/USTC-RVSoC.git
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28 lines
750 B
Systemverilog
28 lines
750 B
Systemverilog
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`timescale 1ps/1ps
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module tb_soc();
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logic clk = 1'b1;
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always #10000 clk = ~clk; // 50MHz clock
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wire uart_tx;
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wire vga_hsync, vga_vsync, vga_red, vga_green, vga_blue;
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soc_top #(
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.UART_RX_CLK_DIV ( 108 ), // 50MHz/4/115200 = 108
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.UART_TX_CLK_DIV ( 434 ), // 50MHz/1/115200 = 434
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.VGA_CLK_DIV ( 1 )
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) soc_i (
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.clk ( clk ),
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.isp_uart_rx ( 1'b1 ),
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.isp_uart_tx ( uart_tx ),
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.vga_hsync ( vga_hsync ),
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.vga_vsync ( vga_vsync ),
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.vga_red ( vga_red ),
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.vga_green ( vga_green ),
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.vga_blue ( vga_blue )
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);
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endmodule
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