WangXuan95 03c5b6e19a add USTCRVSoC-tool

2019-02-11 16:56:18 +08:00

..

core_alu.sv

first commit

2019-02-05 16:19:46 +08:00

core_bus_wrapper.sv

first commit

2019-02-05 16:19:46 +08:00

core_ex_branch_judge.sv

first commit

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core_id_stage.sv

first commit

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core_regfile.sv

first commit

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core_top.sv

add instr ram

2019-02-08 00:38:18 +08:00

instr_rom.sv

add USTCRVSoC-tool

2019-02-11 16:56:18 +08:00

isp_uart.sv

add instr ram

2019-02-08 00:38:18 +08:00

naive_bus_router.sv

first commit

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naive_bus.sv

first commit

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ram_bus_wrapper.sv

first commit

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ram.sv

first commit

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soc_top_tb.sv

优化VGA电路面积、并向ISP-UART中加入设置boot-addr的功能

2019-02-07 15:30:28 +08:00

soc_top.sv

add USTCRVSoC-tool

2019-02-11 16:56:18 +08:00

uart_rx.sv

first commit

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uart_tx_line.sv

first commit

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user_uart_tx.sv

first commit

2019-02-05 16:19:46 +08:00

video_ram.sv

modify readme

2019-02-07 19:36:33 +08:00