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https://github.com/WangXuan95/USTC-RVSoC.git
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50 lines
2.2 KiB
Systemverilog
50 lines
2.2 KiB
Systemverilog
module core_alu(
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input logic [ 6:0] i_opcode, i_funct7,
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input logic [ 2:0] i_funct3,
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input logic [31:0] i_num1u, i_num2u, i_immu,
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output logic [31:0] o_res
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);
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logic [4:0] shamt_rs, shamt_imm;
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logic [31:0] shifted;
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logic signed [31:0] i_num1s, i_num2s, i_imms;
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assign shamt_imm = i_immu[4:0];
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assign shamt_rs = i_num2u[4:0];
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assign i_num1s = i_num1u;
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assign i_num2s = i_num2u;
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assign i_imms = i_immu;
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always_comb
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casex({i_funct7,i_funct3,i_opcode})
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// 算术类
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17'b0000000_000_0110011 : o_res <= i_num1u + i_num2u; // ADD
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17'bxxxxxxx_000_0010011 : o_res <= i_num1u + i_immu ; // ADDI
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17'b0100000_000_0110011 : o_res <= i_num1u - i_num2u; // SUB
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// LUI类
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17'bxxxxxxx_xxx_0110111 : o_res <= i_immu; // LUI
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// 逻辑类
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17'b0000000_100_0110011 : o_res <= i_num1u ^ i_num2u; // XOR
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17'bxxxxxxx_100_0010011 : o_res <= i_num1u ^ i_immu ; // XORI
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17'b0000000_110_0110011 : o_res <= i_num1u | i_num2u; // OR
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17'bxxxxxxx_110_0010011 : o_res <= i_num1u | i_immu ; // ORI
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17'b0000000_111_0110011 : o_res <= i_num1u & i_num2u; // AND
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17'bxxxxxxx_111_0010011 : o_res <= i_num1u & i_immu ; // ANDI
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// 位移类
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17'b0000000_001_0110011 : o_res <= i_num1u << shamt_rs ; // SLL
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17'b0000000_001_0010011 : o_res <= i_num1u << shamt_imm; // SLLI
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17'b0000000_101_0110011 : o_res <= i_num1u >> shamt_rs ; // SRL
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17'b0000000_101_0010011 : o_res <= i_num1u >> shamt_imm; // SRL
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17'b0100000_101_0110011 : o_res <= i_num1s >> shamt_rs ; // SRA
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17'b0100000_101_0010011 : o_res <= i_num1s >> shamt_imm; // SRAI
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// 比较类
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17'b0000000_010_0110011 : o_res <= (i_num1s < i_num2s) ? 1 : 0; // SLT
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17'bxxxxxxx_010_0010011 : o_res <= (i_num1s < i_imms ) ? 1 : 0; // SLTI
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17'b0000000_011_0110011 : o_res <= (i_num1u < i_num2u) ? 1 : 0; // SLTU
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17'bxxxxxxx_011_0010011 : o_res <= (i_num1u < i_immu ) ? 1 : 0; // SLTIU
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// 无操作
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default : o_res <= 0;
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endcase
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endmodule
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