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27 lines
858 B
Systemverilog
27 lines
858 B
Systemverilog
module core_ex_branch_judge(
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input logic i_branch,
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input logic [31:0] i_num1u, i_num2u,
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input logic [ 2:0] i_funct3,
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output logic o_branch
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);
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logic branch_judge_res;
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assign o_branch = i_branch & branch_judge_res;
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logic signed [31:0] i_num1s, i_num2s;
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assign i_num1s = i_num1u;
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assign i_num2s = i_num2u;
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always_comb
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case(i_funct3)
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3'b000 : branch_judge_res <= (i_num1u == i_num2u); // BEQ
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3'b001 : branch_judge_res <= (i_num1u != i_num2u); // BNE
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3'b100 : branch_judge_res <= (i_num1s < i_num2s); // BLT
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3'b101 : branch_judge_res <= (i_num1s >= i_num2s); // BGE
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3'b110 : branch_judge_res <= (i_num1u < i_num2u); // BLTU
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3'b111 : branch_judge_res <= (i_num1u >= i_num2u); // BGEU
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default: branch_judge_res <= 1'b0;
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endcase
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endmodule
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