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31 lines
727 B
Systemverilog
31 lines
727 B
Systemverilog
module ram( // 1024B
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input logic clk, rst_n,
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input logic i_we,
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input logic [ 9:0] i_waddr, i_raddr, i_raddr2,
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input logic [ 7:0] i_wdata,
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output logic [ 7:0] o_rdata, o_rdata2
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);
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initial begin o_rdata = 8'h0; o_rdata2 = 8'h0; end
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localparam SIZE = 1024;
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logic [SIZE-1:0] [7:0] data_ram_cell;
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always @ (posedge clk or negedge rst_n)
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if(~rst_n)
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o_rdata <= 0;
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else
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o_rdata <= data_ram_cell[i_raddr];
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always @ (posedge clk or negedge rst_n)
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if(~rst_n)
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o_rdata2 <= 0;
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else
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o_rdata2 <= data_ram_cell[i_raddr2];
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always @ (posedge clk)
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if(i_we)
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data_ram_cell[i_waddr] <= i_wdata;
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endmodule
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