mirror of
https://github.com/WangXuan95/USTC-RVSoC.git
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108 lines
3.2 KiB
Systemverilog
108 lines
3.2 KiB
Systemverilog
module soc_top #(
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parameter UART_RX_CLK_DIV = 108, // 50MHz/4/115200Hz=108
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parameter UART_TX_CLK_DIV = 434, // 50MHz/1/115200Hz=434
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parameter VGA_CLK_DIV = 1
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)(
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// clock, typically 50MHz, UART_RX_CLK_DIV and UART_TX_CLK_DIV and VGA_CLK_DIV must be modify when clk is not 50MHz
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input logic clk,
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// debug uart and user uart shared signal
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input logic isp_uart_rx,
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output logic isp_uart_tx,
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// VGA signal
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output logic vga_hsync, vga_vsync,
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output logic vga_red, vga_green, vga_blue
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);
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logic rst_n;
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logic [31:0] boot_addr;
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naive_bus bus_masters[3]();
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naive_bus bus_slaves[5]();
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// shared debug uart and user uart module
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isp_uart #(
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.UART_RX_CLK_DIV ( UART_RX_CLK_DIV),
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.UART_TX_CLK_DIV ( UART_TX_CLK_DIV)
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) isp_uart_inst(
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.clk ( clk ),
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.i_uart_rx ( isp_uart_rx ),
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.o_uart_tx ( isp_uart_tx ),
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.o_rst_n ( rst_n ),
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.o_boot_addr ( boot_addr ),
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.bus ( bus_masters[0] ),
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.user_uart_bus ( bus_slaves[4] )
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);
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// RV32I Core
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core_top core_top_inst(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.i_boot_addr ( boot_addr ),
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.instr_master ( bus_masters[2] ),
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.data_master ( bus_masters[1] )
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);
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// 指令ROM
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instr_rom instr_rom_inst(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.bus ( bus_slaves[0] )
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);
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// 指令RAM
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ram_bus_wrapper instr_ram_inst(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.bus ( bus_slaves[1] )
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);
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// 数据RAM
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ram_bus_wrapper data_ram_inst(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.bus ( bus_slaves[2] )
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);
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// 显存
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video_ram #(
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.VGA_CLK_DIV ( VGA_CLK_DIV )
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)video_ram_inst(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.bus ( bus_slaves[3] ),
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.o_vsync ( vga_vsync ),
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.o_hsync ( vga_hsync ),
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.o_red ( vga_red ),
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.o_green ( vga_green ),
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.o_blue ( vga_blue )
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);
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// 3<><33>?5从<35>?<3F>线仲裁<E4BBB2><E8A381>?
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//
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// 主（越靠前优先级越高）：
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// 0. UART Debugger?
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// 1. Core Data Master
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// 2. Core Instruction Master
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//
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// 从：
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// 1. 指令ROM<4F><4D>? 地址空间 00000000~00000fff
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// 2. 指令RAM<41><4D>? 地址空间 00008000~00008fff
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// 3. 数据RAM<41><4D>? 地址空间 00010000~00010fff
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// 4. 显存RAM<41><4D>? 地址空间 00020000~00020fff
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// 5. 用户UART， 地址空间 00030000~00030003
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naive_bus_router #(
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.N_MASTER ( 3 ),
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.N_SLAVE ( 5 ),
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.SLAVES_MASK ( { 32'h0000_0003 , 32'h0000_0fff , 32'h0000_0fff , 32'h0000_0fff , 32'h0000_0fff } ),
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.SLAVES_BASE ( { 32'h0003_0000 , 32'h0002_0000 , 32'h0001_0000 , 32'h0000_8000 , 32'h0000_0000 } )
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) soc_bus_router_inst (
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.clk ( clk ),
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.rst_n ( rst_n ),
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.masters ( bus_masters ),
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.slaves ( bus_slaves )
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);
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endmodule
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